[llvm-commits] [llvm] r86328 - in /llvm/trunk: lib/CodeGen/MachineLICM.cpp lib/CodeGen/TargetInstrInfoImpl.cpp lib/Target/ARM/ARMConstantPoolValue.cpp lib/Target/ARM/ARMConstantPoolValue.h lib/Target/ARM/Thumb2InstrInfo.cpp lib/Target/ARM/Thumb2InstrInfo.h test/CodeGen/Thumb2/machine-licm.ll
Evan Cheng
evan.cheng at apple.com
Fri Nov 6 19:52:03 PST 2009
Author: evancheng
Date: Fri Nov 6 21:52:02 2009
New Revision: 86328
URL: http://llvm.org/viewvc/llvm-project?rev=86328&view=rev
Log:
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
Modified:
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp
llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h
llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=86328&r1=86327&r2=86328&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Fri Nov 6 21:52:02 2009
@@ -22,6 +22,7 @@
#define DEBUG_TYPE "machine-licm"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
@@ -43,6 +44,7 @@
namespace {
class MachineLICM : public MachineFunctionPass {
+ MachineConstantPool *MCP;
const TargetMachine *TM;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
@@ -111,6 +113,11 @@
/// be hoistable.
MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
+ /// LookForDuplicate - Find an instruction amount PrevMIs that is a
+ /// duplicate of MI. Return this instruction if it's found.
+ const MachineInstr *LookForDuplicate(const MachineInstr *MI,
+ std::vector<const MachineInstr*> &PrevMIs);
+
/// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
/// the preheader that compute the same value. If it's found, do a RAU on
/// with the definition of the existing instruction rather than hoisting
@@ -153,6 +160,7 @@
DEBUG(errs() << "******** Machine LICM ********\n");
Changed = FirstInLoop = false;
+ MCP = MF.getConstantPool();
TM = &MF.getTarget();
TII = TM->getInstrInfo();
TRI = TM->getRegisterInfo();
@@ -432,32 +440,12 @@
}
}
-static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
- std::vector<const MachineInstr*> &PrevMIs,
- MachineRegisterInfo *RegInfo) {
- unsigned NumOps = MI->getNumOperands();
+const MachineInstr*
+MachineLICM::LookForDuplicate(const MachineInstr *MI,
+ std::vector<const MachineInstr*> &PrevMIs) {
for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
const MachineInstr *PrevMI = PrevMIs[i];
- unsigned NumOps2 = PrevMI->getNumOperands();
- if (NumOps != NumOps2)
- continue;
- bool IsSame = true;
- for (unsigned j = 0; j != NumOps; ++j) {
- const MachineOperand &MO = MI->getOperand(j);
- if (MO.isReg() && MO.isDef()) {
- if (RegInfo->getRegClass(MO.getReg()) !=
- RegInfo->getRegClass(PrevMI->getOperand(j).getReg())) {
- IsSame = false;
- break;
- }
- continue;
- }
- if (!MO.isIdenticalTo(PrevMI->getOperand(j))) {
- IsSame = false;
- break;
- }
- }
- if (IsSame)
+ if (TII->isIdentical(MI, PrevMI, RegInfo))
return PrevMI;
}
return 0;
@@ -465,18 +453,19 @@
bool MachineLICM::EliminateCSE(MachineInstr *MI,
DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) {
- if (CI != CSEMap.end()) {
- if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second, RegInfo)) {
- DEBUG(errs() << "CSEing " << *MI << " with " << *Dup);
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg() && MO.isDef())
- RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
- }
- MI->eraseFromParent();
- ++NumCSEed;
- return true;
+ if (CI == CSEMap.end())
+ return false;
+
+ if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
+ DEBUG(errs() << "CSEing " << *MI << " with " << *Dup);
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg() && MO.isDef())
+ RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
}
+ MI->eraseFromParent();
+ ++NumCSEed;
+ return true;
}
return false;
}
Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=86328&r1=86327&r2=86328&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Fri Nov 6 21:52:02 2009
@@ -143,6 +143,37 @@
MBB.insert(I, MI);
}
+bool
+TargetInstrInfoImpl::isIdentical(const MachineInstr *MI,
+ const MachineInstr *Other,
+ const MachineRegisterInfo *MRI) const {
+ if (MI->getOpcode() != Other->getOpcode() ||
+ MI->getNumOperands() != Other->getNumOperands())
+ return false;
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ const MachineOperand &OMO = Other->getOperand(i);
+ if (MO.isReg() && MO.isDef()) {
+ assert(OMO.isReg() && OMO.isDef());
+ unsigned Reg = MO.getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
+ if (Reg != OMO.getReg())
+ return false;
+ } else if (MRI->getRegClass(MO.getReg()) !=
+ MRI->getRegClass(OMO.getReg()))
+ return false;
+
+ continue;
+ }
+
+ if (!MO.isIdenticalTo(OMO))
+ return false;
+ }
+
+ return true;
+}
+
unsigned
TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
unsigned FnSize = 0;
Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp?rev=86328&r1=86327&r2=86328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.cpp Fri Nov 6 21:52:02 2009
@@ -62,9 +62,10 @@
ARMConstantPoolValue *CPV =
(ARMConstantPoolValue *)Constants[i].Val.MachineCPVal;
if (CPV->CVal == CVal &&
- CPV->S == S &&
CPV->LabelId == LabelId &&
- CPV->PCAdjust == PCAdjust)
+ CPV->PCAdjust == PCAdjust &&
+ (CPV->S == S || strcmp(CPV->S, S) == 0) &&
+ (CPV->Modifier == Modifier || strcmp(CPV->Modifier, Modifier) == 0))
return i;
}
}
@@ -84,6 +85,23 @@
ID.AddInteger(PCAdjust);
}
+bool
+ARMConstantPoolValue::hasSameValue(ARMConstantPoolValue *ACPV) {
+ if (ACPV->Kind == Kind &&
+ ACPV->CVal == CVal &&
+ ACPV->PCAdjust == PCAdjust &&
+ (ACPV->S == S || strcmp(ACPV->S, S) == 0) &&
+ (ACPV->Modifier == Modifier || strcmp(ACPV->Modifier, Modifier) == 0)) {
+ if (ACPV->LabelId == LabelId)
+ return true;
+ // Two PC relative constpool entries containing the same GV address or
+ // external symbols. FIXME: What about blockaddress?
+ if (Kind == ARMCP::CPValue || Kind == ARMCP::CPExtSymbol)
+ return true;
+ }
+ return false;
+}
+
void ARMConstantPoolValue::dump() const {
errs() << " " << *this;
}
Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h?rev=86328&r1=86327&r2=86328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h Fri Nov 6 21:52:02 2009
@@ -81,6 +81,10 @@
virtual void AddSelectionDAGCSEId(FoldingSetNodeID &ID);
+ /// hasSameValue - Return true if this ARM constpool value
+ /// can share the same constantpool entry as another ARM constpool value.
+ bool hasSameValue(ARMConstantPoolValue *ACPV);
+
void print(raw_ostream *O) const { if (O) print(*O); }
void print(raw_ostream &O) const;
void dump() const;
Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=86328&r1=86327&r2=86328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Fri Nov 6 21:52:02 2009
@@ -175,6 +175,32 @@
NewMI->getOperand(0).setSubReg(SubIdx);
}
+bool Thumb2InstrInfo::isIdentical(const MachineInstr *MI0,
+ const MachineInstr *MI1,
+ const MachineRegisterInfo *MRI) const {
+ unsigned Opcode = MI0->getOpcode();
+ if (Opcode == ARM::t2LDRpci_pic) {
+ const MachineOperand &MO0 = MI0->getOperand(1);
+ const MachineOperand &MO1 = MI1->getOperand(1);
+ if (MO0.getOffset() != MO1.getOffset())
+ return false;
+
+ const MachineFunction *MF = MI0->getParent()->getParent();
+ const MachineConstantPool *MCP = MF->getConstantPool();
+ int CPI0 = MO0.getIndex();
+ int CPI1 = MO1.getIndex();
+ const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
+ const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
+ ARMConstantPoolValue *ACPV0 =
+ static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
+ ARMConstantPoolValue *ACPV1 =
+ static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
+ return ACPV0->hasSameValue(ACPV1);
+ }
+
+ return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
+}
+
void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI, DebugLoc dl,
unsigned DestReg, unsigned BaseReg, int NumBytes,
Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h?rev=86328&r1=86327&r2=86328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h Fri Nov 6 21:52:02 2009
@@ -54,6 +54,10 @@
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const;
+ bool isIdentical(const MachineInstr *MI,
+ const MachineInstr *Other,
+ const MachineRegisterInfo *MRI) const;
+
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=86328&r1=86327&r2=86328&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Fri Nov 6 21:52:02 2009
@@ -15,11 +15,13 @@
bb.nph: ; preds = %entry
; CHECK: BB#1
-; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_0
-; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_1
-; CHECK: add r{{[0-9]+}}, pc
-; CHECK: add r{{[0-9]+}}, pc
+; CHECK: ldr.n r2, LCPI1_0
+; CHECK: add r2, pc
+; CHECK: ldr r{{[0-9]+}}, [r2]
; CHECK: LBB1_2
+; CHECK: LCPI1_0:
+; CHECK-NOT: LCPI1_1:
+; CHECK: .section
%.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
br label %bb
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