[llvm-commits] [llvm] r85280 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Bob Wilson]

Author: bwilson
Date: Tue Oct 27 14:52:03 2009
New Revision: 85280

URL: http://llvm.org/viewvc/llvm-project?rev=85280&view=rev
Log:
Do not clear the "S" bit for RSCri and RSCrs.  They inherit from the "sI"
instruction format that already takes care of setting this.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=85280&r1=85279&r2=85280&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 27 14:52:03 2009
@@ -1131,7 +1131,6 @@
                  DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
                  [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
                  Requires<[IsARM, CarryDefIsUnused]> {
-    let Inst{20} = 0;
     let Inst{25} = 1;
 }
 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
@@ -1140,7 +1139,6 @@
                  Requires<[IsARM, CarryDefIsUnused]> {
     let Inst{4} = 1;
     let Inst{7} = 0;
-    let Inst{20} = 0;
     let Inst{25} = 0;
 }
 }