[llvm-commits] [llvm] r84431 - in /llvm/trunk: lib/Target/X86/X86Subtarget.h test/CodeGen/X86/2007-01-08-InstrSched.ll test/CodeGen/X86/2008-07-11-SpillerBug.ll test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll test/CodeGen/X86/2009-09-19-SchedCustom

Evan Cheng evan.cheng at apple.com
Thu Oct 22 19:10:50 PDT 2009


On Oct 22, 2009, at 7:04 PM, Sandeep Patel wrote:

> This is breaking our canadian cross that runs on MinGW.
> 
> An example of the problem from gcc.o:record_temp_file (the first
> function in gcc.o to exhibit the problem, but not the cause of the
> crash):
> 
> bad code:
> 5d: a3 14 00 00 00  mov    %eax,0x14	5e: dir32	.bss
> 62: 89 48 04        mov    %ecx,0x4(%eax)
> 65: 89 38           mov    %edi,(%eax)
> 
> good code:
> 5d: 89 48 04        mov    %ecx,0x4(%eax)
> 60: 89 38           mov    %edi,(%eax)
> 62: a3 14 00 00 00  mov    %eax,0x14	63: dir32	.bss

What's wrong with the "bad code"?

You can disable it for MinGW to workaround the problem for now.

Evan

> 
> deep
> 
> On Sun, Oct 18, 2009 at 7:57 PM, Evan Cheng <evan.cheng at apple.com> wrote:
>> Author: evancheng
>> Date: Sun Oct 18 14:57:27 2009
>> New Revision: 84431
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=84431&view=rev
>> Log:
>> Turn on post-alloc scheduling for x86.
>> 
>> Modified:
>>    llvm/trunk/lib/Target/X86/X86Subtarget.h
>>    llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll
>>    llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll
>>    llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
>>    llvm/trunk/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
>>    llvm/trunk/test/CodeGen/X86/abi-isel.ll
>>    llvm/trunk/test/CodeGen/X86/fastcc.ll
>>    llvm/trunk/test/CodeGen/X86/peep-test-3.ll
>>    llvm/trunk/test/CodeGen/X86/pic.ll
>>    llvm/trunk/test/CodeGen/X86/sink-hoist.ll
>>    llvm/trunk/test/CodeGen/X86/sse2.ll
>>    llvm/trunk/test/CodeGen/X86/sse3.ll
>>    llvm/trunk/test/CodeGen/X86/tailcallstack64.ll
>>    llvm/trunk/test/CodeGen/X86/widen_arith-3.ll
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Sun Oct 18 14:57:27 2009
>> @@ -219,8 +219,7 @@
>>   /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
>>   /// at 'More' optimization level.
>>   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
>> -    // FIXME: This causes llvm to miscompile itself on i386. :-(
>> -    return false /*OptLevel >= CodeGenOpt::Default*/;
>> +    return OptLevel >= CodeGenOpt::Default;
>>   }
>>  };
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2007-01-08-InstrSched.ll Sun Oct 18 14:57:27 2009
>> @@ -11,9 +11,12 @@
>>     %tmp14 = fadd float %tmp12, %tmp7
>>     ret float %tmp14
>> 
>> -; CHECK:      mulss    LCPI1_2(%rip)
>> +; CHECK:      mulss    LCPI1_3(%rip)
>> +; CHECK-NEXT: mulss    LCPI1_0(%rip)
>> +; CHECK-NEXT: mulss    LCPI1_1(%rip)
>> +; CHECK-NEXT: mulss    LCPI1_2(%rip)
>> +; CHECK-NEXT: addss
>>  ; CHECK-NEXT: addss
>> -; CHECK-NEXT: mulss    LCPI1_3(%rip)
>>  ; CHECK-NEXT: addss
>>  ; CHECK-NEXT: ret
>>  }
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2008-07-11-SpillerBug.ll Sun Oct 18 14:57:27 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim | FileCheck %s
>> +; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim -post-RA-scheduler=false | FileCheck %s
>>  ; PR2536
>> 
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll Sun Oct 18 14:57:27 2009
>> @@ -1,5 +1,5 @@
>>  ; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic \
>> -; RUN:     -disable-fp-elim -mattr=-sse41,-sse3,+sse2 < %s | \
>> +; RUN:     -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false < %s | \
>>  ; RUN:   FileCheck %s
>>  ; rdar://6808032
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll Sun Oct 18 14:57:27 2009
>> @@ -9,9 +9,7 @@
>>   br label %bb
>> 
>>  bb:                                               ; preds = %bb1, %entry
>> -; CHECK:      movl %e
>> -; CHECK-NEXT: addl $1
>> -; CHECK-NEXT: movl %e
>> +; CHECK:      addl $1
>>  ; CHECK-NEXT: adcl $0
>>   %i.0 = phi i64 [ 0, %entry ], [ %0, %bb1 ]      ; <i64> [#uses=1]
>>   %0 = add nsw i64 %i.0, 1                        ; <i64> [#uses=2]
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Sun Oct 18 14:57:27 2009
>> @@ -1,16 +1,16 @@
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-STATIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-PIC
>> 
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-STATIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-PIC
>> 
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC
>> -
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
>> -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-STATIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-PIC
>> +
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-STATIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
>> +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-PIC
>> 
>>  @src = external global [131072 x i32]
>>  @dst = external global [131072 x i32]
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/fastcc.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fastcc.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/fastcc.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/fastcc.ll Sun Oct 18 14:57:27 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
>> +; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -post-RA-scheduler=false | FileCheck %s
>>  ; CHECK: movsd %xmm0, 8(%esp)
>>  ; CHECK: xorl %ecx, %ecx
>> 
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/peep-test-3.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/peep-test-3.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/peep-test-3.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/peep-test-3.ll Sun Oct 18 14:57:27 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -march=x86 | FileCheck %s
>> +; RUN: llc < %s -march=x86 -post-RA-scheduler=false | FileCheck %s
>>  ; rdar://7226797
>> 
>>  ; LLVM should omit the testl and use the flags result from the orl.
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/pic.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pic.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/pic.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/pic.ll Sun Oct 18 14:57:27 2009
>> @@ -1,4 +1,4 @@
>> -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false | FileCheck %s -check-prefix=LINUX
>> +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX
>> 
>>  @ptr = external global i32*
>>  @dst = external global i32
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/sink-hoist.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sink-hoist.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/sink-hoist.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/sink-hoist.ll Sun Oct 18 14:57:27 2009
>> @@ -6,10 +6,10 @@
>>  ; that it's conditionally evaluated.
>> 
>>  ; CHECK: foo:
>> -; CHECK-NEXT: divsd
>> -; CHECK:      testb $1, %dil
>> -; CHECK-NEXT: jne
>>  ; CHECK:      divsd
>> +; CHECK-NEXT: testb $1, %dil
>> +; CHECK-NEXT: jne
>> +; CHECK-NEXT: divsd
>> 
>>  define double @foo(double %x, double %y, i1 %c) nounwind {
>>   %a = fdiv double %x, 3.2
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/sse2.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/sse2.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/sse2.ll Sun Oct 18 14:57:27 2009
>> @@ -10,10 +10,10 @@
>> 
>>  ; CHECK: t1:
>>  ; CHECK:       movl    8(%esp), %eax
>> +; CHECK-NEXT:  movl    4(%esp), %ecx
>>  ; CHECK-NEXT:  movapd  (%eax), %xmm0
>>  ; CHECK-NEXT:  movlpd  12(%esp), %xmm0
>> -; CHECK-NEXT:  movl    4(%esp), %eax
>> -; CHECK-NEXT:  movapd  %xmm0, (%eax)
>> +; CHECK-NEXT:  movapd  %xmm0, (%ecx)
>>  ; CHECK-NEXT:  ret
>>  }
>> 
>> @@ -26,9 +26,9 @@
>> 
>>  ; CHECK: t2:
>>  ; CHECK:       movl    8(%esp), %eax
>> +; CHECK-NEXT:  movl    4(%esp), %ecx
>>  ; CHECK-NEXT:  movapd  (%eax), %xmm0
>>  ; CHECK-NEXT:  movhpd  12(%esp), %xmm0
>> -; CHECK-NEXT:  movl    4(%esp), %eax
>> -; CHECK-NEXT:  movapd  %xmm0, (%eax)
>> +; CHECK-NEXT:  movapd  %xmm0, (%ecx)
>>  ; CHECK-NEXT:  ret
>>  }
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/sse3.ll Sun Oct 18 14:57:27 2009
>> @@ -17,8 +17,8 @@
>> 
>>  ; X64: t0:
>>  ; X64:         movddup (%rsi), %xmm0
>> -; X64:  pshuflw        $0, %xmm0, %xmm0
>>  ; X64: xorl    %eax, %eax
>> +; X64:  pshuflw        $0, %xmm0, %xmm0
>>  ; X64: pinsrw  $0, %eax, %xmm0
>>  ; X64: movaps  %xmm0, (%rdi)
>>  ; X64: ret
>> @@ -167,18 +167,12 @@
>>         store <4 x i16> %6, <4 x i16>* @g2, align 8
>>         ret void
>>  ; X64:         t10:
>> -; X64:                 movq    _g1 at GOTPCREL(%rip), %rax
>> -; X64:                 movaps  (%rax), %xmm0
>>  ; X64:                 pextrw  $4, %xmm0, %eax
>> -; X64:                 movaps  %xmm0, %xmm1
>> +; X64:                 pextrw  $6, %xmm0, %edx
>>  ; X64:                 movlhps %xmm1, %xmm1
>>  ; X64:                 pshuflw $8, %xmm1, %xmm1
>>  ; X64:                 pinsrw  $2, %eax, %xmm1
>> -; X64:                 pextrw  $6, %xmm0, %eax
>> -; X64:                 pinsrw  $3, %eax, %xmm1
>> -; X64:                 movq    _g2 at GOTPCREL(%rip), %rax
>> -; X64:                 movq    %xmm1, (%rax)
>> -; X64:                 ret
>> +; X64:                 pinsrw  $3, %edx, %xmm1
>>  }
>> 
>> 
>> @@ -189,8 +183,8 @@
>>        ret <8 x i16> %tmp7
>> 
>>  ; X64: t11:
>> -; X64: movd    %xmm1, %eax
>>  ; X64: movlhps %xmm0, %xmm0
>> +; X64: movd    %xmm1, %eax
>>  ; X64: pshuflw $1, %xmm0, %xmm0
>>  ; X64: pinsrw  $1, %eax, %xmm0
>>  ; X64: ret
>> @@ -203,8 +197,8 @@
>>        ret <8 x i16> %tmp9
>> 
>>  ; X64: t12:
>> -; X64:         pextrw  $3, %xmm1, %eax
>>  ; X64:         movlhps %xmm0, %xmm0
>> +; X64:         pextrw  $3, %xmm1, %eax
>>  ; X64:         pshufhw $3, %xmm0, %xmm0
>>  ; X64:         pinsrw  $5, %eax, %xmm0
>>  ; X64:         ret
>> @@ -256,18 +250,12 @@
>>         %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0,  <16 x i32> < i32 0, i32 1, i32 2, i32 17,  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
>>         ret <16 x i8> %tmp9
>>  ; X64:         t16:
>> -; X64:                 movaps  LCPI17_0(%rip), %xmm1
>> -; X64:                 movd    %xmm1, %eax
>>  ; X64:                 pinsrw  $0, %eax, %xmm1
>>  ; X64:                 pextrw  $8, %xmm0, %eax
>>  ; X64:                 pinsrw  $1, %eax, %xmm1
>>  ; X64:                 pextrw  $1, %xmm1, %ecx
>>  ; X64:                 movd    %xmm1, %edx
>>  ; X64:                 pinsrw  $0, %edx, %xmm1
>> -; X64:                 movzbl  %cl, %ecx
>> -; X64:                 andw    $-256, %ax
>> -; X64:                 orw     %cx, %ax
>> -; X64:                 movaps  %xmm1, %xmm0
>>  ; X64:                 pinsrw  $1, %eax, %xmm0
>>  ; X64:                 ret
>>  }
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/tailcallstack64.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcallstack64.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/tailcallstack64.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/tailcallstack64.ll Sun Oct 18 14:57:27 2009
>> @@ -3,19 +3,18 @@
>>  ; Check that lowered arguments on the stack do not overwrite each other.
>>  ; Add %in1 %p1 to a different temporary register (%eax).
>>  ; CHECK: movl  %edi, %eax
>> -; CHECK: addl  32(%rsp), %eax
>>  ; Move param %in1 to temp register (%r10d).
>>  ; CHECK: movl  40(%rsp), %r10d
>> -; Move result of addition to stack.
>> -; CHECK: movl  %eax, 40(%rsp)
>>  ; Move param %in2 to stack.
>>  ; CHECK: movl  %r10d, 32(%rsp)
>> +; Move result of addition to stack.
>> +; CHECK: movl  %eax, 40(%rsp)
>>  ; Eventually, do a TAILCALL
>>  ; CHECK: TAILCALL
>> 
>> -declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b)
>> +declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind
>> 
>> -define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) {
>> +define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
>>  entry:
>>         %tmp = add i32 %in1, %p1
>>         %retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/widen_arith-3.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-3.ll?rev=84431&r1=84430&r2=84431&view=diff
>> 
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/widen_arith-3.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/widen_arith-3.ll Sun Oct 18 14:57:27 2009
>> @@ -1,7 +1,7 @@
>>  ; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
>>  ; CHECK: paddw
>> -; CHECK: movd
>>  ; CHECK: pextrw
>> +; CHECK: movd
>> 
>>  ; Widen a v3i16 to v8i16 to do a vector add
>> 
>> 
>> 
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