[llvm-commits] Add some ARM instruction encoding bits for "register" and "register-shifted register"

[Evan Cheng]

On Oct 14, 2009, at 1:45 PM, Bob Wilson wrote:

> 
> On Oct 14, 2009, at 1:26 PM, Evan Cheng wrote:
> 
>> LLVM ARM's so_reg operand can potentially encode "rrx" shifter op as well. In that case, bit 4 is 0, not 1. However, I believe it's only possible to use rrx when the instruction is a mov. So this should be ok. But please add comment to state that it's ok to set bit 4 because rrx cannot be used.
> 
> Yes, it's OK -- there is a separate MOVrx instruction pattern.  In fact, I don't see anything that uses rrx as a shift op, and it's not listed in the definition of so_reg:
> 
> def so_reg : Operand<i32>,    // reg reg imm
>            ComplexPattern<i32, 3, "SelectShifterOperandReg",
>                            [shl,srl,sra,rotr]> {
>  let PrintMethod = "printSORegOperand";
>  let MIOperandInfo = (ops GPR, GPR, i32imm);
> }
> 
> The only place I can see using RRX is the ARMrrx node created by LowerShift() in ARMISelLowering.cpp.  Am I missing something?  If not, it seems like maybe we should remove rrx from the list of shift ops.

I would just document it for now. ARMInstrInfo.td needs some refactoring to split out instructions in the same way as ARMInstrThumb2.td. But we don't want to tackle it now.

Evan