[llvm-commits] Add some ARM instruction encoding bits for "register" and "register-shifted register"

[Evan Cheng]

LLVM ARM's so_reg operand can potentially encode "rrx" shifter op as well. In that case, bit 4 is 0, not 1. However, I believe it's only possible to use rrx when the instruction is a mov. So this should be ok. But please add comment to state that it's ok to set bit 4 because rrx cannot be used.

Evan

On Oct 14, 2009, at 10:03 AM, Johnny Chen wrote:

> For 'r', add:
> 
>  let Inst{4} = 0;
> 
> For 's', add:
> 
>  let Inst{4} = 1;
>  let Inst{7} = 0;
> 
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