[llvm-commits] [llvm] r83145 - in /llvm/trunk/lib/Target/ARM: ARMTargetMachine.cpp ARMTargetMachine.h

[Evan Cheng]

Author: evancheng
Date: Wed Sep 30 03:53:01 2009
New Revision: 83145

URL: http://llvm.org/viewvc/llvm-project?rev=83145&view=rev
Log:
Add a option which would move ld/st multiple pass before post-alloc scheduling.

Modified:
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.h

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=83145&r1=83144&r2=83145&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Sep 30 03:53:01 2009
@@ -22,6 +22,10 @@
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
+static cl::opt<bool>
+LdStBeforeSched("ldstopti-before-sched2", cl::Hidden,
+            cl::desc("Move ld / st multiple pass before postalloc scheduling"));
+
 static const MCAsmInfo *createMCAsmInfo(const Target &T,
                                         const StringRef &TT) {
   Triple TheTriple(TT);
@@ -101,11 +105,22 @@
   return true;
 }
 
+bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel) {
+  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
+  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
+    if (LdStBeforeSched)
+      PM.add(createARMLoadStoreOptimizationPass());
+
+  return true;
+}
+
 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
                                           CodeGenOpt::Level OptLevel) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
-    PM.add(createARMLoadStoreOptimizationPass());
+    if (!LdStBeforeSched)
+      PM.add(createARMLoadStoreOptimizationPass());
     PM.add(createIfConverterPass());
   }
 

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=83145&r1=83144&r2=83145&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Sep 30 03:53:01 2009
@@ -50,6 +50,7 @@
   // Pass Pipeline Configuration
   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+  virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
                               MachineCodeEmitter &MCE);