[llvm-commits] [llvm] r83077 - /llvm/trunk/lib/CodeGen/RegisterScavenging.cpp

[Jim Grosbach]

Done. Thanks, Evan.

-j

On Sep 29, 2009, at 11:54 AM, Evan Cheng wrote:

> Please call TargetRegisterInfo::isVirtualRegister() instead of TRI->  
> per convention. Thanks.
>
> Evan
>
> On Sep 29, 2009, at 10:24 AM, Jim Grosbach wrote:
>
>> Author: grosbach
>> Date: Tue Sep 29 12:24:37 2009
>> New Revision: 83077
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=83077&view=rev
>> Log:
>> Moving register scavenging to a post pass results in virtual  
>> registers in
>> the instruction we're scavenging for. The scavenger needs to know  
>> to avoid
>> them when analyzing register usage.
>>
>>
>> Modified:
>>   llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
>>
>> Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=83077&r1=83076&r2=83077&view=diff
>>
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> = 
>> =====================================================================
>> --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Tue Sep 29  
>> 12:24:37 2009
>> @@ -241,7 +241,8 @@
>>    // Remove any candidates touched by instruction.
>>    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
>>      const MachineOperand &MO = MI->getOperand(i);
>> -      if (!MO.isReg() || MO.isUndef() || !MO.getReg())
>> +      if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
>> +          TRI->isVirtualRegister(MO.getReg()))
>>        continue;
>>      Candidates.reset(MO.getReg());
>>      for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
>> @@ -279,7 +280,7 @@
>>  // Exclude all the registers being used by the instruction.
>>  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
>>    MachineOperand &MO = I->getOperand(i);
>> -    if (MO.isReg())
>> +    if (MO.isReg() && !TRI->isVirtualRegister(MO.getReg()))
>>      Candidates.reset(MO.getReg());
>>  }
>>
>>
>>
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