[llvm-commits] [llvm] r78896 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td
Bob Wilson
bob.wilson at apple.com
Wed Aug 12 22:58:56 PDT 2009
Author: bwilson
Date: Thu Aug 13 00:58:56 2009
New Revision: 78896
URL: http://llvm.org/viewvc/llvm-project?rev=78896&view=rev
Log:
Revert r78852 for now. I want to do this differently, but I don't have time
to fix it tonight.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=78896&r1=78895&r2=78896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 13 00:58:56 2009
@@ -487,7 +487,6 @@
case ARMISD::VREV64: return "ARMISD::VREV64";
case ARMISD::VREV32: return "ARMISD::VREV32";
case ARMISD::VREV16: return "ARMISD::VREV16";
- case ARMISD::VSPLAT0: return "ARMISD::VSPLAT0";
}
}
@@ -2443,8 +2442,6 @@
// DAG nodes, instead of keeping them as shuffles and matching them again
// during code selection. This is more efficient and avoids the possibility
// of inconsistencies between legalization and selection.
- if (SVN->isSplat() && SVN->getSplatIndex() == 0)
- return DAG.getNode(ARMISD::VSPLAT0, dl, VT, SVN->getOperand(0));
if (isVREVMask(SVN, 64))
return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
if (isVREVMask(SVN, 32))
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=78896&r1=78895&r2=78896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Aug 13 00:58:56 2009
@@ -129,8 +129,7 @@
// Vector shuffles:
VREV64, // reverse elements within 64-bit doublewords
VREV32, // reverse elements within 32-bit words
- VREV16, // reverse elements within 16-bit halfwords
- VSPLAT0 // duplicate element 0 into all elements
+ VREV16 // reverse elements within 16-bit halfwords
};
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78896&r1=78895&r2=78896&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Aug 13 00:58:56 2009
@@ -99,7 +99,6 @@
def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
-def NEONvsplat0 : SDNode<"ARMISD::VSPLAT0", SDTARMVSHUF>;
//===----------------------------------------------------------------------===//
// NEON operand definitions
@@ -1745,14 +1744,20 @@
// VDUP : Vector Duplicate (from ARM core register to all elements)
+def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
+ (vector_shuffle node:$lhs, node:$rhs), [{
+ ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
+ return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
+}]>;
+
class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
: NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
- [(set DPR:$dst, (Ty (NEONvsplat0 (scalar_to_vector GPR:$src))))]>;
+ [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
: NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
- [(set QPR:$dst, (Ty (NEONvsplat0 (scalar_to_vector GPR:$src))))]>;
+ [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
@@ -1763,14 +1768,16 @@
def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", ".32\t$dst, $src",
- [(set DPR:$dst,
- (v2f32 (NEONvsplat0 (scalar_to_vector
- (f32 (bitconvert GPR:$src))))))]>;
+ [(set DPR:$dst, (v2f32 (splat_lo
+ (scalar_to_vector
+ (f32 (bitconvert GPR:$src))),
+ undef)))]>;
def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
NoItinerary, "vdup", ".32\t$dst, $src",
- [(set QPR:$dst,
- (v4f32 (NEONvsplat0 (scalar_to_vector
- (f32 (bitconvert GPR:$src))))))]>;
+ [(set QPR:$dst, (v4f32 (splat_lo
+ (scalar_to_vector
+ (f32 (bitconvert GPR:$src))),
+ undef)))]>;
// VDUP : Vector Duplicate Lane (from scalar to all elements)
@@ -1812,14 +1819,16 @@
def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
(outs DPR:$dst), (ins SPR:$src),
NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
- [(set DPR:$dst, (v2f32 (NEONvsplat0
- (scalar_to_vector SPR:$src))))]>;
+ [(set DPR:$dst, (v2f32 (splat_lo
+ (scalar_to_vector SPR:$src),
+ undef)))]>;
def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
(outs QPR:$dst), (ins SPR:$src),
NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
- [(set QPR:$dst, (v4f32 (NEONvsplat0
- (scalar_to_vector SPR:$src))))]>;
+ [(set QPR:$dst, (v4f32 (splat_lo
+ (scalar_to_vector SPR:$src),
+ undef)))]>;
// VMOVN : Vector Narrowing Move
defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
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