[llvm-commits] [llvm] r78850 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td
Chris Lattner
clattner at apple.com
Wed Aug 12 15:56:08 PDT 2009
On Aug 12, 2009, at 3:31 PM, Bob Wilson wrote:
> Author: bwilson
> Date: Wed Aug 12 17:31:50 2009
> New Revision: 78850
>
> URL: http://llvm.org/viewvc/llvm-project?rev=78850&view=rev
> Log:
> Recognize Neon VREV shuffles during legalization instead of selection.
Very nice Bob!
>
> static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
> + ShuffleVectorSDNode *SVN =
> dyn_cast<ShuffleVectorSDNode>(Op.getNode());
> + assert(SVN != 0 && "Expected a ShuffleVectorSDNode in
> LowerVECTOR_SHUFFLE");
This is very nice and clean. It might be a good idea to give some
comment description for how this works, along with a testcase. Also,
you can just use cast<> instead of dyn_cast<> here, which allows you
to drop the assert.
> + DebugLoc dl = Op.getDebugLoc();
> + EVT VT = Op.getValueType();
> +
> + if (isVREVMask(SVN, 64))
> + return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
> + if (isVREVMask(SVN, 32))
> + return DAG.getNode(ARMISD::VREV32, dl, VT, SVN->getOperand(0));
> + if (isVREVMask(SVN, 16))
> + return DAG.getNode(ARMISD::VREV16, dl, VT, SVN->getOperand(0));
If the .ll file has a "vrev" shuffle vector on 4 x float and another
on 4 x i32, they won't be CSE'd here, will they? I'd expect a bitcast
to the designated "canonical type" then a bitcast back if needed.
This ensures that all 4-wide ones are of the same type so they get
CSE'd.
-Chris
> +
> return Op;
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=78850&r1=78849&r2=78850&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Aug 12 17:31:50
> 2009
> @@ -124,7 +124,12 @@
> VLD4D,
> VST2D,
> VST3D,
> - VST4D
> + VST4D,
> +
> + // Vector shuffles:
> + VREV64, // reverse elements within 64-bit doublewords
> + VREV32, // reverse elements within 32-bit words
> + VREV16 // reverse elements within 16-bit halfwords
> };
> }
>
> @@ -135,11 +140,6 @@
> /// return the constant being splatted. The ByteSize field
> indicates the
> /// number of bytes of each element [1248].
> SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG
> &DAG);
> -
> - /// isVREVMask - Check if a vector shuffle corresponds to a VREV
> - /// instruction with the specified blocksize. (The order of
> the elements
> - /// within each block of the vector is reversed.)
> - bool isVREVMask(ShuffleVectorSDNode *N, unsigned blocksize);
> }
>
> //
> =
> =
> =--------------------------------------------------------------------
> ===//
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78850&r1=78849&r2=78850&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Aug 12 17:31:50 2009
> @@ -95,6 +95,11 @@
> def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
> [SDNPHasChain, SDNPMayStore]>;
>
> +def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>,
> SDTCisSameAs<0, 1>]>;
> +def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
> +def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
> +def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
> +
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> // NEON operand definitions
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> @@ -1881,25 +1886,7 @@
> def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
> v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
>
> -// VREV : Vector Reverse
> -
> -def vrev64_shuffle : PatFrag<(ops node:$in),
> - (vector_shuffle node:$in, undef), [{
> - ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
> - return ARM::isVREVMask(SVOp, 64);
> -}]>;
> -
> -def vrev32_shuffle : PatFrag<(ops node:$in),
> - (vector_shuffle node:$in, undef), [{
> - ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
> - return ARM::isVREVMask(SVOp, 32);
> -}]>;
> -
> -def vrev16_shuffle : PatFrag<(ops node:$in),
> - (vector_shuffle node:$in, undef), [{
> - ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
> - return ARM::isVREVMask(SVOp, 16);
> -}]>;
> +// Vector Reverse.
>
> // VREV64 : Vector Reverse elements within 64-bit doublewords
>
> @@ -1907,12 +1894,12 @@
> : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
> (ins DPR:$src), NoItinerary,
> !strconcat(OpcodeStr, "\t$dst, $src"), "",
> - [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
> + [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
> class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
> : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
> (ins QPR:$src), NoItinerary,
> !strconcat(OpcodeStr, "\t$dst, $src"), "",
> - [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
> + [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
>
> def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
> def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
> @@ -1930,12 +1917,12 @@
> : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
> (ins DPR:$src), NoItinerary,
> !strconcat(OpcodeStr, "\t$dst, $src"), "",
> - [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
> + [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
> class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
> : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
> (ins QPR:$src), NoItinerary,
> !strconcat(OpcodeStr, "\t$dst, $src"), "",
> - [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
> + [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
>
> def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
> def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
> @@ -1949,12 +1936,12 @@
> : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
> (ins DPR:$src), NoItinerary,
> !strconcat(OpcodeStr, "\t$dst, $src"), "",
> - [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
> + [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
> class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
> : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
> (ins QPR:$src), NoItinerary,
> !strconcat(OpcodeStr, "\t$dst, $src"), "",
> - [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
> + [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
>
> def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
> def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
>
>
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