[llvm-commits] [llvm] r78563 - in /llvm/trunk: include/llvm/CodeGen/ScheduleHazardRecognizer.h include/llvm/Target/TargetInstrItineraries.h lib/CodeGen/CMakeLists.txt lib/CodeGen/ExactHazardRecognizer.cpp lib/CodeGen/ExactHazardRecognizer.h lib/CodeGen/PostRASchedulerList.cpp lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/SimpleHazardRecognizer.h

[Dan Gohman]

Hi David,

This looks good. One question:

On Aug 10, 2009, at 8:55 AM, David Goodwin wrote:
>     } else if (!HasNoopHazards) {
>       // Otherwise, we have a pipeline stall, but no other problem,  
> just advance
>       // the current cycle and try again.
>
> Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=78563&r1=78562&r2=78563&view=diff
>
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> = 
> ======================================================================
> --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
> +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Mon Aug 10 10:55:25  
> 2009
> @@ -174,16 +174,20 @@
>       assert(TRI->isPhysicalRegister(Reg) && "Virtual register  
> encountered!");
>       std::vector<SUnit *> &UseList = Uses[Reg];
>       std::vector<SUnit *> &DefList = Defs[Reg];
> -      // Optionally add output and anti dependencies.
> -      // TODO: Using a latency of 1 here assumes there's no cost for
> -      //       reusing registers.
> +      // Optionally add output and anti dependencies. For anti
> +      // dependencies we use a latency of 0 because for a multi-issue
> +      // target we want to allow the defining instruction to issue
> +      // in the same cycle as the using instruction.
> +      // TODO: Using a latency of 1 here for output dependencies  
> assumes
> +      //       there's no cost for reusing registers.
>       SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
> +      unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1;

I don't see how anti and output dependencies are different here. If
two instructions with an anti-dependence can be issued in the same
cycle, could not two instructions with an output-dependence also be
issued in the same cycle?

Dan