[llvm-commits] [llvm] r78610 [1/2] - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/AsmPrinter/ lib/Target/XCore/ lib/Transforms/Scalar/ lib/VMCore/ utils/TableGen/
Owen Anderson
resistor at mac.com
Mon Aug 10 15:56:31 PDT 2009
Author: resistor
Date: Mon Aug 10 17:56:29 2009
New Revision: 78610
URL: http://llvm.org/viewvc/llvm-project?rev=78610&view=rev
Log:
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
Modified:
llvm/trunk/include/llvm/CodeGen/CallingConvLower.h
llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
llvm/trunk/include/llvm/CodeGen/FastISel.h
llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/trunk/include/llvm/CodeGen/ValueTypes.h
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h
llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPUOperands.td
llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
llvm/trunk/lib/Target/TargetRegisterInfo.cpp
llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
llvm/trunk/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
llvm/trunk/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/trunk/lib/VMCore/Function.cpp
llvm/trunk/lib/VMCore/ValueTypes.cpp
llvm/trunk/lib/VMCore/Verifier.cpp
llvm/trunk/utils/TableGen/CallingConvEmitter.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/trunk/utils/TableGen/CodeGenDAGPatterns.h
llvm/trunk/utils/TableGen/CodeGenIntrinsics.h
llvm/trunk/utils/TableGen/CodeGenRegisters.h
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.h
llvm/trunk/utils/TableGen/DAGISelEmitter.cpp
llvm/trunk/utils/TableGen/FastISelEmitter.cpp
llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
llvm/trunk/utils/TableGen/TGValueTypes.cpp
Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original)
+++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Mon Aug 10 17:56:29 2009
@@ -54,14 +54,14 @@
LocInfo HTP : 6;
/// ValVT - The type of the value being assigned.
- MVT ValVT;
+ EVT ValVT;
/// LocVT - The type of the location being assigned to.
- MVT LocVT;
+ EVT LocVT;
public:
- static CCValAssign getReg(unsigned ValNo, MVT ValVT,
- unsigned RegNo, MVT LocVT,
+ static CCValAssign getReg(unsigned ValNo, EVT ValVT,
+ unsigned RegNo, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret.ValNo = ValNo;
@@ -74,8 +74,8 @@
return Ret;
}
- static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
- unsigned RegNo, MVT LocVT,
+ static CCValAssign getCustomReg(unsigned ValNo, EVT ValVT,
+ unsigned RegNo, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
@@ -83,8 +83,8 @@
return Ret;
}
- static CCValAssign getMem(unsigned ValNo, MVT ValVT,
- unsigned Offset, MVT LocVT,
+ static CCValAssign getMem(unsigned ValNo, EVT ValVT,
+ unsigned Offset, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret.ValNo = ValNo;
@@ -97,8 +97,8 @@
return Ret;
}
- static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
- unsigned Offset, MVT LocVT,
+ static CCValAssign getCustomMem(unsigned ValNo, EVT ValVT,
+ unsigned Offset, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
@@ -107,7 +107,7 @@
}
unsigned getValNo() const { return ValNo; }
- MVT getValVT() const { return ValVT; }
+ EVT getValVT() const { return ValVT; }
bool isRegLoc() const { return !isMem; }
bool isMemLoc() const { return isMem; }
@@ -116,7 +116,7 @@
unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
- MVT getLocVT() const { return LocVT; }
+ EVT getLocVT() const { return LocVT; }
LocInfo getLocInfo() const { return HTP; }
bool isExtInLoc() const {
@@ -127,15 +127,15 @@
/// CCAssignFn - This function assigns a location for Val, updating State to
/// reflect the change.
-typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
+typedef bool CCAssignFn(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
/// CCCustomFn - This function assigns a location for Val, possibly updating
/// all args to reflect changes and indicates if it handled it. It must set
/// isCustom if it handles the arg and returns true.
-typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
- MVT &LocVT, CCValAssign::LocInfo &LocInfo,
+typedef bool CCCustomFn(unsigned &ValNo, EVT &ValVT,
+ EVT &LocVT, CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags, CCState &State);
/// CCState - This class holds information needed while lowering arguments and
@@ -189,7 +189,7 @@
/// AnalyzeCallOperands - Same as above except it takes vectors of types
/// and argument flags.
- void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
+ void AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
CCAssignFn Fn);
@@ -200,7 +200,7 @@
/// AnalyzeCallResult - Same as above except it's specialized for calls which
/// produce a single value.
- void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
+ void AnalyzeCallResult(EVT VT, CCAssignFn Fn);
/// getFirstUnallocated - Return the first unallocated register in the set, or
/// NumRegs if they are all allocated.
@@ -269,8 +269,8 @@
// HandleByVal - Allocate a stack slot large enough to pass an argument by
// value. The size and alignment information of the argument is encoded in its
// parameter attribute.
- void HandleByVal(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
+ void HandleByVal(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
private:
Modified: llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h (original)
+++ llvm/trunk/include/llvm/CodeGen/DAGISelHeader.h Mon Aug 10 17:56:29 2009
@@ -35,7 +35,7 @@
return false;
if (Chain->getNumOperands() > 0) {
SDValue C0 = Chain->getOperand(0);
- if (C0.getValueType() == MVT::Other)
+ if (C0.getValueType() == EVT::Other)
return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
}
return true;
Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon Aug 10 17:56:29 2009
@@ -137,24 +137,24 @@
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode
/// be emitted.
- virtual unsigned FastEmit_(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operand be emitted.
///
- virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode, unsigned Op0);
/// FastEmit_rr - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operands be emitted.
///
- virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1);
@@ -162,8 +162,8 @@
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm);
@@ -171,8 +171,8 @@
/// to request that an instruction with the given type, opcode, and
/// register and floating-point immediate operands be emitted.
///
- virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm);
@@ -180,8 +180,8 @@
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1, uint64_t Imm);
@@ -189,33 +189,33 @@
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_ri_(MVT::SimpleValueType VT,
+ unsigned FastEmit_ri_(EVT::SimpleValueType VT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- MVT::SimpleValueType ImmType);
+ EVT::SimpleValueType ImmType);
/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
/// to emit an instruction with an immediate operand using FastEmit_rf.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_rf_(MVT::SimpleValueType VT,
+ unsigned FastEmit_rf_(EVT::SimpleValueType VT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- MVT::SimpleValueType ImmType);
+ EVT::SimpleValueType ImmType);
/// FastEmit_i - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// immediate operand be emitted.
- virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_i(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
uint64_t Imm);
/// FastEmit_f - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// floating-point immediate operand be emitted.
- virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_f(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
ConstantFP *FPImm);
@@ -268,12 +268,12 @@
/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
/// from a specified index of a superregister to a specified type.
- unsigned FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
+ unsigned FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx);
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
- unsigned FastEmitZExtFromI1(MVT::SimpleValueType VT,
+ unsigned FastEmitZExtFromI1(EVT::SimpleValueType VT,
unsigned Op);
/// FastEmitBranch - Emit an unconditional branch to the given block,
Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Mon Aug 10 17:56:29 2009
@@ -237,27 +237,27 @@
/// getFPEXT - Return the FPEXT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
- Libcall getFPEXT(MVT OpVT, MVT RetVT);
+ Libcall getFPEXT(EVT OpVT, EVT RetVT);
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
- Libcall getFPROUND(MVT OpVT, MVT RetVT);
+ Libcall getFPROUND(EVT OpVT, EVT RetVT);
/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
- Libcall getFPTOSINT(MVT OpVT, MVT RetVT);
+ Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
- Libcall getFPTOUINT(MVT OpVT, MVT RetVT);
+ Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
- Libcall getSINTTOFP(MVT OpVT, MVT RetVT);
+ Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
- Libcall getUINTTOFP(MVT OpVT, MVT RetVT);
+ Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
}
}
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Aug 10 17:56:29 2009
@@ -193,7 +193,7 @@
/// setRoot - Set the current root tag of the SelectionDAG.
///
const SDValue &setRoot(SDValue N) {
- assert((!N.getNode() || N.getValueType() == MVT::Other) &&
+ assert((!N.getNode() || N.getValueType() == EVT::Other) &&
"DAG root value is not a chain!");
return Root = N;
}
@@ -244,70 +244,70 @@
/// getVTList - Return an SDVTList that represents the list of values
/// specified.
- SDVTList getVTList(MVT VT);
- SDVTList getVTList(MVT VT1, MVT VT2);
- SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3);
- SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4);
- SDVTList getVTList(const MVT *VTs, unsigned NumVTs);
+ SDVTList getVTList(EVT VT);
+ SDVTList getVTList(EVT VT1, EVT VT2);
+ SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
+ SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
+ SDVTList getVTList(const EVT *VTs, unsigned NumVTs);
//===--------------------------------------------------------------------===//
// Node creation methods.
//
- SDValue getConstant(uint64_t Val, MVT VT, bool isTarget = false);
- SDValue getConstant(const APInt &Val, MVT VT, bool isTarget = false);
- SDValue getConstant(const ConstantInt &Val, MVT VT, bool isTarget = false);
+ SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
+ SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
+ SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
SDValue getIntPtrConstant(uint64_t Val, bool isTarget = false);
- SDValue getTargetConstant(uint64_t Val, MVT VT) {
+ SDValue getTargetConstant(uint64_t Val, EVT VT) {
return getConstant(Val, VT, true);
}
- SDValue getTargetConstant(const APInt &Val, MVT VT) {
+ SDValue getTargetConstant(const APInt &Val, EVT VT) {
return getConstant(Val, VT, true);
}
- SDValue getTargetConstant(const ConstantInt &Val, MVT VT) {
+ SDValue getTargetConstant(const ConstantInt &Val, EVT VT) {
return getConstant(Val, VT, true);
}
- SDValue getConstantFP(double Val, MVT VT, bool isTarget = false);
- SDValue getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
- SDValue getConstantFP(const ConstantFP &CF, MVT VT, bool isTarget = false);
- SDValue getTargetConstantFP(double Val, MVT VT) {
+ SDValue getConstantFP(double Val, EVT VT, bool isTarget = false);
+ SDValue getConstantFP(const APFloat& Val, EVT VT, bool isTarget = false);
+ SDValue getConstantFP(const ConstantFP &CF, EVT VT, bool isTarget = false);
+ SDValue getTargetConstantFP(double Val, EVT VT) {
return getConstantFP(Val, VT, true);
}
- SDValue getTargetConstantFP(const APFloat& Val, MVT VT) {
+ SDValue getTargetConstantFP(const APFloat& Val, EVT VT) {
return getConstantFP(Val, VT, true);
}
- SDValue getTargetConstantFP(const ConstantFP &Val, MVT VT) {
+ SDValue getTargetConstantFP(const ConstantFP &Val, EVT VT) {
return getConstantFP(Val, VT, true);
}
- SDValue getGlobalAddress(const GlobalValue *GV, MVT VT,
+ SDValue getGlobalAddress(const GlobalValue *GV, EVT VT,
int64_t offset = 0, bool isTargetGA = false,
unsigned char TargetFlags = 0);
- SDValue getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
+ SDValue getTargetGlobalAddress(const GlobalValue *GV, EVT VT,
int64_t offset = 0,
unsigned char TargetFlags = 0) {
return getGlobalAddress(GV, VT, offset, true, TargetFlags);
}
- SDValue getFrameIndex(int FI, MVT VT, bool isTarget = false);
- SDValue getTargetFrameIndex(int FI, MVT VT) {
+ SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false);
+ SDValue getTargetFrameIndex(int FI, EVT VT) {
return getFrameIndex(FI, VT, true);
}
- SDValue getJumpTable(int JTI, MVT VT, bool isTarget = false,
+ SDValue getJumpTable(int JTI, EVT VT, bool isTarget = false,
unsigned char TargetFlags = 0);
- SDValue getTargetJumpTable(int JTI, MVT VT, unsigned char TargetFlags = 0) {
+ SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags = 0) {
return getJumpTable(JTI, VT, true, TargetFlags);
}
- SDValue getConstantPool(Constant *C, MVT VT,
+ SDValue getConstantPool(Constant *C, EVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false,
unsigned char TargetFlags = 0);
- SDValue getTargetConstantPool(Constant *C, MVT VT,
+ SDValue getTargetConstantPool(Constant *C, EVT VT,
unsigned Align = 0, int Offset = 0,
unsigned char TargetFlags = 0) {
return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
}
- SDValue getConstantPool(MachineConstantPoolValue *C, MVT VT,
+ SDValue getConstantPool(MachineConstantPoolValue *C, EVT VT,
unsigned Align = 0, int Offs = 0, bool isT=false,
unsigned char TargetFlags = 0);
SDValue getTargetConstantPool(MachineConstantPoolValue *C,
- MVT VT, unsigned Align = 0,
+ EVT VT, unsigned Align = 0,
int Offset = 0, unsigned char TargetFlags=0) {
return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
}
@@ -315,19 +315,19 @@
// to provide debug info for the BB at that time, so keep this one around.
SDValue getBasicBlock(MachineBasicBlock *MBB);
SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
- SDValue getExternalSymbol(const char *Sym, MVT VT);
- SDValue getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT);
- SDValue getTargetExternalSymbol(const char *Sym, MVT VT,
+ SDValue getExternalSymbol(const char *Sym, EVT VT);
+ SDValue getExternalSymbol(const char *Sym, DebugLoc dl, EVT VT);
+ SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
unsigned char TargetFlags = 0);
- SDValue getValueType(MVT);
- SDValue getRegister(unsigned Reg, MVT VT);
+ SDValue getValueType(EVT);
+ SDValue getRegister(unsigned Reg, EVT VT);
SDValue getDbgStopPoint(DebugLoc DL, SDValue Root,
unsigned Line, unsigned Col, Value *CU);
SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
unsigned LabelID);
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
- return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
+ return getNode(ISD::CopyToReg, dl, EVT::Other, Chain,
getRegister(Reg, N.getValueType()), N);
}
@@ -336,7 +336,7 @@
// null) and that there should be a flag result.
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
SDValue Flag) {
- SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
+ SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
}
@@ -344,13 +344,13 @@
// Similar to last getCopyToReg() except parameter Reg is a SDValue
SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
SDValue Flag) {
- SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
+ SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
SDValue Ops[] = { Chain, Reg, N, Flag };
return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
}
- SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) {
- SDVTList VTs = getVTList(VT, MVT::Other);
+ SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) {
+ SDVTList VTs = getVTList(VT, EVT::Other);
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
}
@@ -358,9 +358,9 @@
// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
- SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT,
+ SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT,
SDValue Flag) {
- SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag);
+ SDVTList VTs = getVTList(VT, EVT::Other, EVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2);
}
@@ -369,7 +369,7 @@
/// Returns the ConvertRndSat Note: Avoid using this node because it may
/// disappear in the future and most targets don't support it.
- SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
+ SDValue getConvertRndSat(EVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
SDValue STy,
SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
@@ -377,21 +377,21 @@
/// elements in VT, which must be a vector type, must match the number of
/// mask elements NumElts. A integer mask element equal to -1 is treated as
/// undefined.
- SDValue getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
+ SDValue getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,
const int *MaskElts);
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
- SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
+ SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT SrcTy);
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
- SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
+ SDValue getNOT(DebugLoc DL, SDValue Val, EVT VT);
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
/// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a
/// useful DebugLoc.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
- SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
+ SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
SDValue Ops[] = { Chain, Op };
return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
VTs, Ops, 2);
@@ -402,7 +402,7 @@
/// a useful DebugLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
SDValue InFlag) {
- SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
+ SDVTList NodeTys = getVTList(EVT::Other, EVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(Chain);
Ops.push_back(Op1);
@@ -414,36 +414,36 @@
}
/// getUNDEF - Return an UNDEF node. UNDEF does not have a useful DebugLoc.
- SDValue getUNDEF(MVT VT) {
+ SDValue getUNDEF(EVT VT) {
return getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), VT);
}
/// getGLOBAL_OFFSET_TABLE - Return a GLOBAL_OFFSET_TABLE node. This does
/// not have a useful DebugLoc.
- SDValue getGLOBAL_OFFSET_TABLE(MVT VT) {
+ SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {
return getNode(ISD::GLOBAL_OFFSET_TABLE, DebugLoc::getUnknownLoc(), VT);
}
/// getNode - Gets or creates the specified node.
///
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT);
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N);
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2);
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT);
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N);
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2);
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3);
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4);
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5);
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
const SDUse *Ops, unsigned NumOps);
- SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+ SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL,
- const std::vector<MVT> &ResultTys,
+ const std::vector<EVT> &ResultTys,
const SDValue *Ops, unsigned NumOps);
- SDValue getNode(unsigned Opcode, DebugLoc DL, const MVT *VTs, unsigned NumVTs,
+ SDValue getNode(unsigned Opcode, DebugLoc DL, const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
@@ -482,7 +482,7 @@
/// getSetCC - Helper function to make it easier to build SetCC's if you just
/// have an ISD::CondCode instead of an SDValue.
///
- SDValue getSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
+ SDValue getSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
}
@@ -490,7 +490,7 @@
/// getVSetCC - Helper function to make it easier to build VSetCC's nodes
/// if you just have an ISD::CondCode instead of an SDValue.
///
- SDValue getVSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
+ SDValue getVSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond));
}
@@ -506,33 +506,33 @@
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
- SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
+ SDValue getVAArg(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
SDValue SV);
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 3 operands
- SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
+ SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
unsigned Alignment=0);
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 2 operands.
- SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
+ SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Val, const Value* PtrVal,
unsigned Alignment = 0);
/// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
/// result and takes a list of operands.
SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
- const MVT *VTs, unsigned NumVTs,
+ const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
+ EVT MemVT, const Value *srcValue, int SVOff,
unsigned Align = 0, bool Vol = false,
bool ReadMem = true, bool WriteMem = true);
SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
+ EVT MemVT, const Value *srcValue, int SVOff,
unsigned Align = 0, bool Vol = false,
bool ReadMem = true, bool WriteMem = true);
@@ -542,19 +542,19 @@
/// getLoad - Loads are not normal binary operators: their result type is not
/// determined by their operands, and they produce a value AND a token chain.
///
- SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
+ SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
- SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
+ SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
SDValue Chain, SDValue Ptr, const Value *SV,
- int SVOffset, MVT EVT, bool isVolatile=false,
+ int SVOffset, EVT EVT, bool isVolatile=false,
unsigned Alignment=0);
SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
- MVT VT, SDValue Chain,
+ EVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
- const Value *SV, int SVOffset, MVT EVT,
+ const Value *SV, int SVOffset, EVT EVT,
bool isVolatile=false, unsigned Alignment=0);
/// getStore - Helper function to build ISD::STORE nodes.
@@ -563,7 +563,7 @@
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
- const Value *SV, int SVOffset, MVT TVT,
+ const Value *SV, int SVOffset, EVT TVT,
bool isVolatile=false, unsigned Alignment=0);
SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
@@ -600,54 +600,54 @@
/// specified node to have the specified return type, Target opcode, and
/// operands. Note that target opcodes are stored as
/// ~TargetOpcode in the node opcode field. The resultant node is returned.
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDValue Op1);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
SDValue Op1, SDValue Op2);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
const SDValue *Ops, unsigned NumOps);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1, MVT VT2);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, const SDValue *Ops, unsigned NumOps);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
- SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, MVT VT1,
- MVT VT2, MVT VT3, MVT VT4, const SDValue *Ops,
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
+ EVT VT2, const SDValue *Ops, unsigned NumOps);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
+ EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps);
+ SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
+ EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops,
unsigned NumOps);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, SDValue Op1);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
- MVT VT2, MVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
+ EVT VT2, SDValue Op1);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
+ SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
+ EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
/// MorphNodeTo - These *mutate* the specified node to have the specified
/// return type, opcode, and operands.
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT, SDValue Op1);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT, SDValue Op1);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT,
SDValue Op1, SDValue Op2);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT,
SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT,
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT,
const SDValue *Ops, unsigned NumOps);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1, MVT VT2);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, const SDValue *Ops, unsigned NumOps);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, MVT VT3, const SDValue *Ops, unsigned NumOps);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, SDValue Op1);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2);
- SDNode *MorphNodeTo(SDNode *N, unsigned Opc, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1, EVT VT2);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
+ EVT VT2, const SDValue *Ops, unsigned NumOps);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
+ EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
+ EVT VT2, SDValue Op1);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2);
+ SDNode *MorphNodeTo(SDNode *N, unsigned Opc, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
@@ -657,33 +657,33 @@
/// Note that getTargetNode returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT);
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1);
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1,
SDValue Op2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
const SDValue *Ops, unsigned NumOps);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2);
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
SDValue Op1);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2);
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
const SDValue *Ops, unsigned NumOps);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2, SDValue Op3);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
const SDValue *Ops, unsigned NumOps);
- SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
- MVT VT4, const SDValue *Ops, unsigned NumOps);
+ SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3,
+ EVT VT4, const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
- const std::vector<MVT> &ResultTys, const SDValue *Ops,
+ const std::vector<EVT> &ResultTys, const SDValue *Ops,
unsigned NumOps);
/// getNodeIfExists - Get the specified node if it's already available, or
@@ -792,20 +792,20 @@
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
/// specified value type. If minAlign is specified, the slot size will have
/// at least that alignment.
- SDValue CreateStackTemporary(MVT VT, unsigned minAlign = 1);
+ SDValue CreateStackTemporary(EVT VT, unsigned minAlign = 1);
/// CreateStackTemporary - Create a stack temporary suitable for holding
/// either of the specified value types.
- SDValue CreateStackTemporary(MVT VT1, MVT VT2);
+ SDValue CreateStackTemporary(EVT VT1, EVT VT2);
/// FoldConstantArithmetic -
SDValue FoldConstantArithmetic(unsigned Opcode,
- MVT VT,
+ EVT VT,
ConstantSDNode *Cst1,
ConstantSDNode *Cst2);
/// FoldSetCC - Constant fold a setcc to true or false.
- SDValue FoldSetCC(MVT VT, SDValue N1,
+ SDValue FoldSetCC(EVT VT, SDValue N1,
SDValue N2, ISD::CondCode Cond, DebugLoc dl);
/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
@@ -855,7 +855,7 @@
void DeleteNodeNotInCSEMaps(SDNode *N);
void DeallocateNode(SDNode *N);
- unsigned getMVTAlignment(MVT MemoryVT) const;
+ unsigned getEVTAlignment(EVT MemoryVT) const;
void allnodes_clear();
@@ -866,7 +866,7 @@
std::vector<CondCodeSDNode*> CondCodeNodes;
std::vector<SDNode*> ValueTypeNodes;
- std::map<MVT, SDNode*, MVT::compareRawBits> ExtendedValueTypeNodes;
+ std::map<EVT, SDNode*, EVT::compareRawBits> ExtendedValueTypeNodes;
StringMap<SDNode*> ExternalSymbols;
std::map<std::pair<std::string, unsigned char>,SDNode*> TargetExternalSymbols;
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Mon Aug 10 17:56:29 2009
@@ -65,7 +65,7 @@
virtual bool runOnMachineFunction(MachineFunction &MF);
- unsigned MakeReg(MVT VT);
+ unsigned MakeReg(EVT VT);
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelect() = 0;
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Mon Aug 10 17:56:29 2009
@@ -52,7 +52,7 @@
/// SelectionDAG::getVTList(...).
///
struct SDVTList {
- const MVT *VTs;
+ const EVT *VTs;
unsigned int NumVTs;
};
@@ -856,7 +856,7 @@
/// getValueType - Return the ValueType of the referenced return value.
///
- inline MVT getValueType() const;
+ inline EVT getValueType() const;
/// getValueSizeInBits - Returns the size of the value in bits.
///
@@ -965,7 +965,7 @@
/// getResNo - Convenience function for get().getResNo().
unsigned getResNo() const { return Val.getResNo(); }
/// getValueType - Convenience function for get().getValueType().
- MVT getValueType() const { return Val.getValueType(); }
+ EVT getValueType() const { return Val.getValueType(); }
/// operator== - Convenience function for get().operator==
bool operator==(const SDValue &V) const {
@@ -1055,7 +1055,7 @@
/// ValueList - The types of the values this node defines. SDNode's may
/// define multiple values simultaneously.
- const MVT *ValueList;
+ const EVT *ValueList;
/// UseList - List of uses for this SDNode.
SDUse *UseList;
@@ -1067,7 +1067,7 @@
DebugLoc debugLoc;
/// getValueTypeList - Return a pointer to the specified value type.
- static const MVT *getValueTypeList(MVT VT);
+ static const EVT *getValueTypeList(EVT VT);
friend class SelectionDAG;
friend struct ilist_traits<SDNode>;
@@ -1241,7 +1241,7 @@
/// to which the flag operand points. Otherwise return NULL.
SDNode *getFlaggedNode() const {
if (getNumOperands() != 0 &&
- getOperand(getNumOperands()-1).getValueType() == MVT::Flag)
+ getOperand(getNumOperands()-1).getValueType() == EVT::Flag)
return getOperand(getNumOperands()-1).getNode();
return 0;
}
@@ -1269,18 +1269,18 @@
/// getValueType - Return the type of a specified result.
///
- MVT getValueType(unsigned ResNo) const {
+ EVT getValueType(unsigned ResNo) const {
assert(ResNo < NumValues && "Illegal result number!");
return ValueList[ResNo];
}
- /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
+ /// getValueSizeInBits - Returns EVT::getSizeInBits(getValueType(ResNo)).
///
unsigned getValueSizeInBits(unsigned ResNo) const {
return getValueType(ResNo).getSizeInBits();
}
- typedef const MVT* value_iterator;
+ typedef const EVT* value_iterator;
value_iterator value_begin() const { return ValueList; }
value_iterator value_end() const { return ValueList+NumValues; }
@@ -1307,7 +1307,7 @@
void addUse(SDUse &U) { U.addToList(&UseList); }
protected:
- static SDVTList getSDVTList(MVT VT) {
+ static SDVTList getSDVTList(EVT VT) {
SDVTList Ret = { getValueTypeList(VT), 1 };
return Ret;
}
@@ -1401,7 +1401,7 @@
inline unsigned SDValue::getOpcode() const {
return Node->getOpcode();
}
-inline MVT SDValue::getValueType() const {
+inline EVT SDValue::getValueType() const {
return Node->getValueType(ResNo);
}
inline unsigned SDValue::getNumOperands() const {
@@ -1501,7 +1501,7 @@
explicit HandleSDNode(SDValue X)
#endif
: SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)) {
+ getSDVTList(EVT::Other)) {
InitOperands(&Op, X);
}
~HandleSDNode();
@@ -1512,7 +1512,7 @@
class MemSDNode : public SDNode {
private:
// MemoryVT - VT of in-memory value.
- MVT MemoryVT;
+ EVT MemoryVT;
//! SrcValue - Memory location for alias analysis.
const Value *SrcValue;
@@ -1521,12 +1521,12 @@
int SVOffset;
public:
- MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
+ MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT MemoryVT,
const Value *srcValue, int SVOff,
unsigned alignment, bool isvolatile);
MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops,
- unsigned NumOps, MVT MemoryVT, const Value *srcValue, int SVOff,
+ unsigned NumOps, EVT MemoryVT, const Value *srcValue, int SVOff,
unsigned alignment, bool isvolatile);
/// Returns alignment and volatility of the memory access
@@ -1546,7 +1546,7 @@
int getSrcValueOffset() const { return SVOffset; }
/// getMemoryVT - Return the type of the in-memory value.
- MVT getMemoryVT() const { return MemoryVT; }
+ EVT getMemoryVT() const { return MemoryVT; }
/// getMemOperand - Return a MachineMemOperand object describing the memory
/// reference performed by operation.
@@ -1596,7 +1596,7 @@
// Swp: swap value
// SrcVal: address to update as a Value (used for MemOperand)
// Align: alignment of memory
- AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
+ AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
SDValue Chain, SDValue Ptr,
SDValue Cmp, SDValue Swp, const Value* SrcVal,
unsigned Align=0)
@@ -1604,7 +1604,7 @@
Align, /*isVolatile=*/true) {
InitOperands(Ops, Chain, Ptr, Cmp, Swp);
}
- AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
+ AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,
SDValue Chain, SDValue Ptr,
SDValue Val, const Value* SrcVal, unsigned Align=0)
: MemSDNode(Opc, dl, VTL, MemVT, SrcVal, /*SVOffset=*/0,
@@ -1647,7 +1647,7 @@
public:
MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
const SDValue *Ops, unsigned NumOps,
- MVT MemoryVT, const Value *srcValue, int SVO,
+ EVT MemoryVT, const Value *srcValue, int SVO,
unsigned Align, bool Vol, bool ReadMem, bool WriteMem)
: MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
ReadMem(ReadMem), WriteMem(WriteMem) {
@@ -1683,7 +1683,7 @@
const int *Mask;
protected:
friend class SelectionDAG;
- ShuffleVectorSDNode(MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
+ ShuffleVectorSDNode(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,
const int *M)
: SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
InitOperands(Ops, N1, N2);
@@ -1691,7 +1691,7 @@
public:
void getMask(SmallVectorImpl<int> &M) const {
- MVT VT = getValueType(0);
+ EVT VT = getValueType(0);
M.clear();
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
M.push_back(Mask[i]);
@@ -1706,7 +1706,7 @@
assert(isSplat() && "Cannot get splat index for non-splat!");
return Mask[0];
}
- static bool isSplatMask(const int *Mask, MVT VT);
+ static bool isSplatMask(const int *Mask, EVT VT);
static bool classof(const ShuffleVectorSDNode *) { return true; }
static bool classof(const SDNode *N) {
@@ -1717,7 +1717,7 @@
class ConstantSDNode : public SDNode {
const ConstantInt *Value;
friend class SelectionDAG;
- ConstantSDNode(bool isTarget, const ConstantInt *val, MVT VT)
+ ConstantSDNode(bool isTarget, const ConstantInt *val, EVT VT)
: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
}
@@ -1741,7 +1741,7 @@
class ConstantFPSDNode : public SDNode {
const ConstantFP *Value;
friend class SelectionDAG;
- ConstantFPSDNode(bool isTarget, const ConstantFP *val, MVT VT)
+ ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
: SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
}
@@ -1770,7 +1770,7 @@
}
bool isExactlyValue(const APFloat& V) const;
- bool isValueValidForType(MVT VT, const APFloat& Val);
+ bool isValueValidForType(EVT VT, const APFloat& Val);
static bool classof(const ConstantFPSDNode *) { return true; }
static bool classof(const SDNode *N) {
@@ -1784,7 +1784,7 @@
int64_t Offset;
unsigned char TargetFlags;
friend class SelectionDAG;
- GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, MVT VT,
+ GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, EVT VT,
int64_t o, unsigned char TargetFlags);
public:
@@ -1806,7 +1806,7 @@
class FrameIndexSDNode : public SDNode {
int FI;
friend class SelectionDAG;
- FrameIndexSDNode(int fi, MVT VT, bool isTarg)
+ FrameIndexSDNode(int fi, EVT VT, bool isTarg)
: SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), FI(fi) {
}
@@ -1825,7 +1825,7 @@
int JTI;
unsigned char TargetFlags;
friend class SelectionDAG;
- JumpTableSDNode(int jti, MVT VT, bool isTarg, unsigned char TF)
+ JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF)
: SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
}
@@ -1850,7 +1850,7 @@
unsigned Alignment; // Minimum alignment requirement of CP (not log2 value).
unsigned char TargetFlags;
friend class SelectionDAG;
- ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align,
+ ConstantPoolSDNode(bool isTarget, Constant *c, EVT VT, int o, unsigned Align,
unsigned char TF)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
DebugLoc::getUnknownLoc(),
@@ -1859,7 +1859,7 @@
Val.ConstVal = c;
}
ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
- MVT VT, int o, unsigned Align, unsigned char TF)
+ EVT VT, int o, unsigned Align, unsigned char TF)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Offset(o), Alignment(Align), TargetFlags(TF) {
@@ -1910,7 +1910,7 @@
/// harder. Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
: SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)), MBB(mbb) {
+ getSDVTList(EVT::Other)), MBB(mbb) {
}
public:
@@ -1961,7 +1961,7 @@
/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
: SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)), V(v) {}
+ getSDVTList(EVT::Other)), V(v) {}
public:
/// getValue - return the contained Value.
@@ -1983,7 +1983,7 @@
/// Create a MachineMemOperand node
explicit MemOperandSDNode(const MachineMemOperand &mo)
: SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)), MO(mo) {}
+ getSDVTList(EVT::Other)), MO(mo) {}
public:
/// MO - The contained MachineMemOperand.
@@ -1999,7 +1999,7 @@
class RegisterSDNode : public SDNode {
unsigned Reg;
friend class SelectionDAG;
- RegisterSDNode(unsigned reg, MVT VT)
+ RegisterSDNode(unsigned reg, EVT VT)
: SDNode(ISD::Register, DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Reg(reg) {
}
@@ -2022,7 +2022,7 @@
DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
Value *cu)
: SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) {
+ getSDVTList(EVT::Other)), Line(l), Column(c), CU(cu) {
InitOperands(&Chain, ch);
}
public:
@@ -2041,7 +2041,7 @@
unsigned LabelID;
friend class SelectionDAG;
LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
- : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
+ : SDNode(NodeTy, dl, getSDVTList(EVT::Other)), LabelID(id) {
InitOperands(&Chain, ch);
}
public:
@@ -2059,7 +2059,7 @@
unsigned char TargetFlags;
friend class SelectionDAG;
- ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, MVT VT)
+ ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EVT VT)
: SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) {
@@ -2081,7 +2081,7 @@
friend class SelectionDAG;
explicit CondCodeSDNode(ISD::CondCode Cond)
: SDNode(ISD::CONDCODE, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)), Condition(Cond) {
+ getSDVTList(EVT::Other)), Condition(Cond) {
}
public:
@@ -2098,7 +2098,7 @@
class CvtRndSatSDNode : public SDNode {
ISD::CvtCode CvtCode;
friend class SelectionDAG;
- explicit CvtRndSatSDNode(MVT VT, DebugLoc dl, const SDValue *Ops,
+ explicit CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops,
unsigned NumOps, ISD::CvtCode Code)
: SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
CvtCode(Code) {
@@ -2203,11 +2203,11 @@
///
struct InputArg {
ArgFlagsTy Flags;
- MVT VT;
+ EVT VT;
bool Used;
- InputArg() : VT(MVT::Other), Used(false) {}
- InputArg(ISD::ArgFlagsTy flags, MVT vt, bool used)
+ InputArg() : VT(EVT::Other), Used(false) {}
+ InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
: Flags(flags), VT(vt), Used(used) {
assert(VT.isSimple() &&
"InputArg value type must be Simple!");
@@ -2232,18 +2232,18 @@
};
}
-/// VTSDNode - This class is used to represent MVT's, which are used
+/// VTSDNode - This class is used to represent EVT's, which are used
/// to parameterize some operations.
class VTSDNode : public SDNode {
- MVT ValueType;
+ EVT ValueType;
friend class SelectionDAG;
- explicit VTSDNode(MVT VT)
+ explicit VTSDNode(EVT VT)
: SDNode(ISD::VALUETYPE, DebugLoc::getUnknownLoc(),
- getSDVTList(MVT::Other)), ValueType(VT) {
+ getSDVTList(EVT::Other)), ValueType(VT) {
}
public:
- MVT getVT() const { return ValueType; }
+ EVT getVT() const { return ValueType; }
static bool classof(const VTSDNode *) { return true; }
static bool classof(const SDNode *N) {
@@ -2264,7 +2264,7 @@
public:
LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands,
unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
- MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
+ EVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
: MemSDNode(NodeTy, dl, VTs, VT, SV, SVO, Align, Vol) {
assert(Align != 0 && "Loads and stores should have non-zero aligment");
SubclassData |= AM << 2;
@@ -2302,7 +2302,7 @@
class LoadSDNode : public LSBaseSDNode {
friend class SelectionDAG;
LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs,
- ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
+ ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT LVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3,
VTs, AM, LVT, SV, O, Align, Vol) {
@@ -2331,7 +2331,7 @@
class StoreSDNode : public LSBaseSDNode {
friend class SelectionDAG;
StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,
- ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
+ ISD::MemIndexedMode AM, bool isTrunc, EVT SVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
: LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4,
VTs, AM, SVT, SV, O, Align, Vol) {
Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Mon Aug 10 17:56:29 2009
@@ -25,7 +25,7 @@
class Type;
struct LLVMContext;
- struct MVT { // MVT = Machine Value Type
+ struct EVT { // EVT = Machine Value Type
public:
enum SimpleValueType {
// If you change this numbering, you must change the values in
@@ -78,7 +78,7 @@
LAST_VALUETYPE = 34, // This always remains at the end of the list.
// This is the current maximum for LAST_VALUETYPE.
- // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
+ // EVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
// This value must be a multiple of 32.
MAX_ALLOWED_VALUETYPE = 64,
@@ -111,7 +111,7 @@
private:
/// This union holds low-level value types. Valid values include any of
/// the values in the SimpleValueType enum, or any value returned from one
- /// of the MVT methods. Any value type equal to one of the SimpleValueType
+ /// of the EVT methods. Any value type equal to one of the SimpleValueType
/// enum values is a "simple" value type. All others are "extended".
///
/// Note that simple doesn't necessary mean legal for the target machine.
@@ -124,20 +124,20 @@
};
public:
- MVT() {}
- MVT(SimpleValueType S) : V(S) {}
+ EVT() {}
+ EVT(SimpleValueType S) : V(S) {}
- bool operator==(const MVT VT) const {
+ bool operator==(const EVT VT) const {
return getRawBits() == VT.getRawBits();
}
- bool operator!=(const MVT VT) const {
+ bool operator!=(const EVT VT) const {
return getRawBits() != VT.getRawBits();
}
- /// getFloatingPointVT - Returns the MVT that represents a floating point
+ /// getFloatingPointVT - Returns the EVT that represents a floating point
/// type with the given number of bits. There are two floating point types
/// with 128 bits - this returns f128 rather than ppcf128.
- static MVT getFloatingPointVT(unsigned BitWidth) {
+ static EVT getFloatingPointVT(unsigned BitWidth) {
switch (BitWidth) {
default:
assert(false && "Bad bit width!");
@@ -152,9 +152,9 @@
}
}
- /// getIntegerVT - Returns the MVT that represents an integer with the given
+ /// getIntegerVT - Returns the EVT that represents an integer with the given
/// number of bits.
- static MVT getIntegerVT(unsigned BitWidth) {
+ static EVT getIntegerVT(unsigned BitWidth) {
switch (BitWidth) {
default:
break;
@@ -174,9 +174,9 @@
return getExtendedIntegerVT(BitWidth);
}
- /// getVectorVT - Returns the MVT that represents a vector NumElements in
+ /// getVectorVT - Returns the EVT that represents a vector NumElements in
/// length, where each element is of type VT.
- static MVT getVectorVT(MVT VT, unsigned NumElements) {
+ static EVT getVectorVT(EVT VT, unsigned NumElements) {
switch (VT.V) {
default:
break;
@@ -218,7 +218,7 @@
/// getIntVectorWithNumElements - Return any integer vector type that has
/// the specified number of elements.
- static MVT getIntVectorWithNumElements(unsigned NumElts) {
+ static EVT getIntVectorWithNumElements(unsigned NumElts) {
switch (NumElts) {
default: return getVectorVT(i8, NumElts);
case 1: return v1i64;
@@ -229,13 +229,13 @@
}
}
- /// isSimple - Test if the given MVT is simple (as opposed to being
+ /// isSimple - Test if the given EVT is simple (as opposed to being
/// extended).
bool isSimple() const {
return V <= LastSimpleValueType;
}
- /// isExtended - Test if the given MVT is extended (as opposed to
+ /// isExtended - Test if the given EVT is extended (as opposed to
/// being simple).
bool isExtended() const {
return !isSimple();
@@ -296,33 +296,33 @@
}
/// bitsEq - Return true if this has the same number of bits as VT.
- bool bitsEq(MVT VT) const {
+ bool bitsEq(EVT VT) const {
return getSizeInBits() == VT.getSizeInBits();
}
/// bitsGT - Return true if this has more bits than VT.
- bool bitsGT(MVT VT) const {
+ bool bitsGT(EVT VT) const {
return getSizeInBits() > VT.getSizeInBits();
}
/// bitsGE - Return true if this has no less bits than VT.
- bool bitsGE(MVT VT) const {
+ bool bitsGE(EVT VT) const {
return getSizeInBits() >= VT.getSizeInBits();
}
/// bitsLT - Return true if this has less bits than VT.
- bool bitsLT(MVT VT) const {
+ bool bitsLT(EVT VT) const {
return getSizeInBits() < VT.getSizeInBits();
}
/// bitsLE - Return true if this has no more bits than VT.
- bool bitsLE(MVT VT) const {
+ bool bitsLE(EVT VT) const {
return getSizeInBits() <= VT.getSizeInBits();
}
/// getSimpleVT - Return the SimpleValueType held in the specified
- /// simple MVT.
+ /// simple EVT.
SimpleValueType getSimpleVT() const {
assert(isSimple() && "Expected a SimpleValueType!");
return SimpleValueType(V);
@@ -330,7 +330,7 @@
/// getVectorElementType - Given a vector type, return the type of
/// each element.
- MVT getVectorElementType() const {
+ EVT getVectorElementType() const {
assert(isVector() && "Invalid vector type!");
switch (V) {
default:
@@ -439,10 +439,10 @@
return (getSizeInBits() + 7)/8*8;
}
- /// getRoundIntegerType - Rounds the bit-width of the given integer MVT up
+ /// getRoundIntegerType - Rounds the bit-width of the given integer EVT up
/// to the nearest power of two (and at least to eight), and returns the
- /// integer MVT with that number of bits.
- MVT getRoundIntegerType() const {
+ /// integer EVT with that number of bits.
+ EVT getRoundIntegerType() const {
assert(isInteger() && !isVector() && "Invalid integer type!");
unsigned BitWidth = getSizeInBits();
if (BitWidth <= 8)
@@ -457,32 +457,32 @@
return !(NElts & (NElts - 1));
}
- /// getPow2VectorType - Widens the length of the given vector MVT up to
+ /// getPow2VectorType - Widens the length of the given vector EVT up to
/// the nearest power of 2 and returns that type.
- MVT getPow2VectorType() const {
+ EVT getPow2VectorType() const {
if (!isPow2VectorType()) {
unsigned NElts = getVectorNumElements();
unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
- return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
+ return EVT::getVectorVT(getVectorElementType(), Pow2NElts);
}
else {
return *this;
}
}
- /// getMVTString - This function returns value type as a string,
+ /// getEVTString - This function returns value type as a string,
/// e.g. "i32".
- std::string getMVTString() const;
+ std::string getEVTString() const;
- /// getTypeForMVT - This method returns an LLVM type corresponding to the
- /// specified MVT. For integer types, this returns an unsigned type. Note
+ /// getTypeForEVT - This method returns an LLVM type corresponding to the
+ /// specified EVT. For integer types, this returns an unsigned type. Note
/// that this will abort for types that cannot be represented.
- const Type *getTypeForMVT() const;
+ const Type *getTypeForEVT() const;
- /// getMVT - Return the value type corresponding to the specified type.
+ /// getEVT - Return the value type corresponding to the specified type.
/// This returns all pointers as iPTR. If HandleUnknown is true, unknown
/// types are returned as Other, otherwise they are invalid.
- static MVT getMVT(const Type *Ty, bool HandleUnknown = false);
+ static EVT getEVT(const Type *Ty, bool HandleUnknown = false);
/// getRawBits - Represent the type as a bunch of bits.
uintptr_t getRawBits() const { return V; }
@@ -490,7 +490,7 @@
/// compareRawBits - A meaningless but well-behaved order, useful for
/// constructing containers.
struct compareRawBits {
- bool operator()(MVT L, MVT R) const {
+ bool operator()(EVT L, EVT R) const {
return L.getRawBits() < R.getRawBits();
}
};
@@ -499,15 +499,15 @@
// Methods for handling the Extended-type case in functions above.
// These are all out-of-line to prevent users of this header file
// from having a dependency on Type.h.
- static MVT getExtendedIntegerVT(unsigned BitWidth);
- static MVT getExtendedVectorVT(MVT VT, unsigned NumElements);
+ static EVT getExtendedIntegerVT(unsigned BitWidth);
+ static EVT getExtendedVectorVT(EVT VT, unsigned NumElements);
bool isExtendedFloatingPoint() const;
bool isExtendedInteger() const;
bool isExtendedVector() const;
bool isExtended64BitVector() const;
bool isExtended128BitVector() const;
bool isExtended256BitVector() const;
- MVT getExtendedVectorElementType() const;
+ EVT getExtendedVectorElementType() const;
unsigned getExtendedVectorNumElements() const;
unsigned getExtendedSizeInBits() const;
};
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Aug 10 17:56:29 2009
@@ -111,8 +111,8 @@
bool isBigEndian() const { return !IsLittleEndian; }
bool isLittleEndian() const { return IsLittleEndian; }
- MVT::SimpleValueType getPointerTy() const { return PointerTy; }
- MVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
+ EVT::SimpleValueType getPointerTy() const { return PointerTy; }
+ EVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
/// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
/// codegen.
@@ -133,10 +133,10 @@
/// getSetCCResultType - Return the ValueType of the result of SETCC
/// operations. Also used to obtain the target's preferred type for
/// the condition operand of SELECT and BRCOND nodes. In the case of
- /// BRCOND the argument passed is MVT::Other since there are no other
+ /// BRCOND the argument passed is EVT::Other since there are no other
/// operands to get a type hint from.
virtual
- MVT::SimpleValueType getSetCCResultType(MVT VT) const;
+ EVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getBooleanContents - For targets without i1 registers, this gives the
/// nature of the high-bits of boolean values held in types wider than i1.
@@ -152,7 +152,7 @@
/// getRegClassFor - Return the register class that should be used for the
/// specified value type. This may only be called on legal types.
- TargetRegisterClass *getRegClassFor(MVT VT) const {
+ TargetRegisterClass *getRegClassFor(EVT VT) const {
assert(VT.isSimple() && "getRegClassFor called on illegal type!");
TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
assert(RC && "This value type is not natively supported!");
@@ -162,7 +162,7 @@
/// isTypeLegal - Return true if the target has native support for the
/// specified value type. This means that it has a register that directly
/// holds it without promotions or expansions.
- bool isTypeLegal(MVT VT) const {
+ bool isTypeLegal(EVT VT) const {
assert(!VT.isSimple() ||
(unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
@@ -172,8 +172,8 @@
/// ValueTypeActions - This is a bitvector that contains two bits for each
/// value type, where the two bits correspond to the LegalizeAction enum.
/// This can be queried with "getTypeAction(VT)".
- /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
- uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
+ /// dimension by (EVT::MAX_ALLOWED_VALUETYPE/32) * 2
+ uint32_t ValueTypeActions[(EVT::MAX_ALLOWED_VALUETYPE/32)*2];
public:
ValueTypeActionImpl() {
ValueTypeActions[0] = ValueTypeActions[1] = 0;
@@ -186,7 +186,7 @@
ValueTypeActions[3] = RHS.ValueTypeActions[3];
}
- LegalizeAction getTypeAction(MVT VT) const {
+ LegalizeAction getTypeAction(EVT VT) const {
if (VT.isExtended()) {
if (VT.isVector()) {
return VT.isPow2VectorType() ? Expand : Promote;
@@ -201,7 +201,7 @@
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
}
- void setTypeAction(MVT VT, LegalizeAction Action) {
+ void setTypeAction(EVT VT, LegalizeAction Action) {
unsigned I = VT.getSimpleVT();
assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
@@ -216,7 +216,7 @@
/// it is already legal (return 'Legal') or we need to promote it to a larger
/// type (return 'Promote'), or we need to expand it into multiple registers
/// of smaller integer type (return 'Expand'). 'Custom' is not an option.
- LegalizeAction getTypeAction(MVT VT) const {
+ LegalizeAction getTypeAction(EVT VT) const {
return ValueTypeActions.getTypeAction(VT);
}
@@ -226,43 +226,43 @@
/// than the largest integer register, this contains one step in the expansion
/// to get to the smaller register. For illegal floating point types, this
/// returns the integer type to transform to.
- MVT getTypeToTransformTo(MVT VT) const {
+ EVT getTypeToTransformTo(EVT VT) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
- MVT NVT = TransformToType[VT.getSimpleVT()];
+ EVT NVT = TransformToType[VT.getSimpleVT()];
assert(getTypeAction(NVT) != Promote &&
"Promote may not follow Expand or Promote");
return NVT;
}
if (VT.isVector()) {
- MVT NVT = VT.getPow2VectorType();
+ EVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Vector length is a power of 2 - split to half the size.
unsigned NumElts = VT.getVectorNumElements();
- MVT EltVT = VT.getVectorElementType();
- return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
+ EVT EltVT = VT.getVectorElementType();
+ return (NumElts == 1) ? EltVT : EVT::getVectorVT(EltVT, NumElts / 2);
}
// Promote to a power of two size, avoiding multi-step promotion.
return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
} else if (VT.isInteger()) {
- MVT NVT = VT.getRoundIntegerType();
+ EVT NVT = VT.getRoundIntegerType();
if (NVT == VT)
// Size is a power of two - expand to half the size.
- return MVT::getIntegerVT(VT.getSizeInBits() / 2);
+ return EVT::getIntegerVT(VT.getSizeInBits() / 2);
else
// Promote to a power of two size, avoiding multi-step promotion.
return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
}
assert(0 && "Unsupported extended type!");
- return MVT(MVT::Other); // Not reached
+ return EVT(EVT::Other); // Not reached
}
/// getTypeToExpandTo - For types supported by the target, this is an
/// identity function. For types that must be expanded (i.e. integer types
/// that are larger than the largest integer register or illegal floating
/// point types), this returns the largest legal type it will be expanded to.
- MVT getTypeToExpandTo(MVT VT) const {
+ EVT getTypeToExpandTo(EVT VT) const {
assert(!VT.isVector());
while (true) {
switch (getTypeAction(VT)) {
@@ -280,18 +280,18 @@
}
/// getVectorTypeBreakdown - Vector types are broken down into some number of
- /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
- /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
- /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
+ /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
+ /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
+ /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
///
/// This method returns the number of registers needed, and the VT for each
/// register. It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
///
- unsigned getVectorTypeBreakdown(MVT VT,
- MVT &IntermediateVT,
+ unsigned getVectorTypeBreakdown(EVT VT,
+ EVT &IntermediateVT,
unsigned &NumIntermediates,
- MVT &RegisterVT) const;
+ EVT &RegisterVT) const;
/// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
/// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
@@ -299,7 +299,7 @@
/// information into the IntrinsicInfo that was passed to the function.
typedef struct IntrinsicInfo {
unsigned opc; // target opcode
- MVT memVT; // memory VT
+ EVT memVT; // memory VT
const Value* ptrVal; // value representing memory location
int offset; // offset off of ptrVal
unsigned align; // alignment
@@ -315,10 +315,10 @@
/// getWidenVectorType: given a vector type, returns the type to widen to
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
- /// If there is no vector type that we want to widen to, returns MVT::Other
+ /// If there is no vector type that we want to widen to, returns EVT::Other
/// When and were to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
- virtual MVT getWidenVectorType(MVT VT) const;
+ virtual EVT getWidenVectorType(EVT VT) const;
typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
legal_fpimm_iterator legal_fpimm_begin() const {
@@ -333,7 +333,7 @@
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal.
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
- MVT VT) const {
+ EVT VT) const {
return true;
}
@@ -342,7 +342,7 @@
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
/// pool entry.
virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
- MVT VT) const {
+ EVT VT) const {
return false;
}
@@ -350,7 +350,7 @@
/// it is legal, needs to be promoted to a larger size, needs to be
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
- LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
+ LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
if (VT.isExtended()) return Expand;
assert(Op < array_lengthof(OpActions[0]) &&
(unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 &&
@@ -364,16 +364,16 @@
/// isOperationLegalOrCustom - Return true if the specified operation is
/// legal on this target or can be made legal with custom lowering. This
/// is used to help guide high-level lowering decisions.
- bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
- return (VT == MVT::Other || isTypeLegal(VT)) &&
+ bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
+ return (VT == EVT::Other || isTypeLegal(VT)) &&
(getOperationAction(Op, VT) == Legal ||
getOperationAction(Op, VT) == Custom);
}
/// isOperationLegal - Return true if the specified operation is legal on this
/// target.
- bool isOperationLegal(unsigned Op, MVT VT) const {
- return (VT == MVT::Other || isTypeLegal(VT)) &&
+ bool isOperationLegal(unsigned Op, EVT VT) const {
+ return (VT == EVT::Other || isTypeLegal(VT)) &&
getOperationAction(Op, VT) == Legal;
}
@@ -381,7 +381,7 @@
/// either it is legal, needs to be promoted to a larger size, needs to be
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
- LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
+ LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
assert(LType < array_lengthof(LoadExtActions) &&
(unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
"Table isn't big enough!");
@@ -390,7 +390,7 @@
/// isLoadExtLegal - Return true if the specified load with extension is legal
/// on this target.
- bool isLoadExtLegal(unsigned LType, MVT VT) const {
+ bool isLoadExtLegal(unsigned LType, EVT VT) const {
return VT.isSimple() &&
(getLoadExtAction(LType, VT) == Legal ||
getLoadExtAction(LType, VT) == Custom);
@@ -400,8 +400,8 @@
/// treated: either it is legal, needs to be promoted to a larger size, needs
/// to be expanded to some other code sequence, or the target has a custom
/// expander for it.
- LegalizeAction getTruncStoreAction(MVT ValVT,
- MVT MemVT) const {
+ LegalizeAction getTruncStoreAction(EVT ValVT,
+ EVT MemVT) const {
assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
(unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
"Table isn't big enough!");
@@ -411,7 +411,7 @@
/// isTruncStoreLegal - Return true if the specified store with truncation is
/// legal on this target.
- bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
+ bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
return isTypeLegal(ValVT) && MemVT.isSimple() &&
(getTruncStoreAction(ValVT, MemVT) == Legal ||
getTruncStoreAction(ValVT, MemVT) == Custom);
@@ -422,16 +422,16 @@
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction
- getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
+ getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
- ((unsigned)VT.getSimpleVT()) < MVT::LAST_VALUETYPE &&
+ ((unsigned)VT.getSimpleVT()) < EVT::LAST_VALUETYPE &&
"Table isn't big enough!");
return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode]));
}
/// isIndexedLoadLegal - Return true if the specified indexed load is legal
/// on this target.
- bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
+ bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
return VT.isSimple() &&
(getIndexedLoadAction(IdxMode, VT) == Legal ||
getIndexedLoadAction(IdxMode, VT) == Custom);
@@ -442,16 +442,16 @@
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction
- getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
+ getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
- (unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
+ (unsigned)VT.getSimpleVT() < EVT::LAST_VALUETYPE &&
"Table isn't big enough!");
return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode]));
}
/// isIndexedStoreLegal - Return true if the specified indexed load is legal
/// on this target.
- bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
+ bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
return VT.isSimple() &&
(getIndexedStoreAction(IdxMode, VT) == Legal ||
getIndexedStoreAction(IdxMode, VT) == Custom);
@@ -462,7 +462,7 @@
/// expanded to some other code sequence, or the target has a custom expander
/// for it.
LegalizeAction
- getConvertAction(MVT FromVT, MVT ToVT) const {
+ getConvertAction(EVT FromVT, EVT ToVT) const {
assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
(unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
"Table isn't big enough!");
@@ -472,7 +472,7 @@
/// isConvertLegal - Return true if the specified conversion is legal
/// on this target.
- bool isConvertLegal(MVT FromVT, MVT ToVT) const {
+ bool isConvertLegal(EVT FromVT, EVT ToVT) const {
return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
(getConvertAction(FromVT, ToVT) == Legal ||
getConvertAction(FromVT, ToVT) == Custom);
@@ -482,7 +482,7 @@
/// either it is legal, needs to be expanded to some other code sequence,
/// or the target has a custom expander for it.
LegalizeAction
- getCondCodeAction(ISD::CondCode CC, MVT VT) const {
+ getCondCodeAction(ISD::CondCode CC, EVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) &&
(unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
"Table isn't big enough!");
@@ -494,7 +494,7 @@
/// isCondCodeLegal - Return true if the specified condition code is legal
/// on this target.
- bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
+ bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
return getCondCodeAction(CC, VT) == Legal ||
getCondCodeAction(CC, VT) == Custom;
}
@@ -502,36 +502,36 @@
/// getTypeToPromoteTo - If the action for this operation is to promote, this
/// method returns the ValueType to promote to.
- MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
+ EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
assert(getOperationAction(Op, VT) == Promote &&
"This operation isn't promoted!");
// See if this has an explicit type specified.
- std::map<std::pair<unsigned, MVT::SimpleValueType>,
- MVT::SimpleValueType>::const_iterator PTTI =
+ std::map<std::pair<unsigned, EVT::SimpleValueType>,
+ EVT::SimpleValueType>::const_iterator PTTI =
PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
if (PTTI != PromoteToType.end()) return PTTI->second;
assert((VT.isInteger() || VT.isFloatingPoint()) &&
"Cannot autopromote this type, add it with AddPromotedToType.");
- MVT NVT = VT;
+ EVT NVT = VT;
do {
- NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
- assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
+ NVT = (EVT::SimpleValueType)(NVT.getSimpleVT()+1);
+ assert(NVT.isInteger() == VT.isInteger() && NVT != EVT::isVoid &&
"Didn't find type to promote to!");
} while (!isTypeLegal(NVT) ||
getOperationAction(Op, NVT) == Promote);
return NVT;
}
- /// getValueType - Return the MVT corresponding to this LLVM type.
+ /// getValueType - Return the EVT corresponding to this LLVM type.
/// This is fixed by the LLVM operations except for the pointer size. If
- /// AllowUnknown is true, this will return MVT::Other for types with no MVT
+ /// AllowUnknown is true, this will return EVT::Other for types with no EVT
/// counterpart (e.g. structs), otherwise it will assert.
- MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
- MVT VT = MVT::getMVT(Ty, AllowUnknown);
- return VT == MVT::iPTR ? PointerTy : VT;
+ EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
+ EVT VT = EVT::getEVT(Ty, AllowUnknown);
+ return VT == EVT::iPTR ? PointerTy : VT;
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
@@ -541,13 +541,13 @@
/// getRegisterType - Return the type of registers that this ValueType will
/// eventually require.
- MVT getRegisterType(MVT VT) const {
+ EVT getRegisterType(EVT VT) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
return RegisterTypeForVT[VT.getSimpleVT()];
}
if (VT.isVector()) {
- MVT VT1, RegisterVT;
+ EVT VT1, RegisterVT;
unsigned NumIntermediates;
(void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
return RegisterVT;
@@ -556,7 +556,7 @@
return getRegisterType(getTypeToTransformTo(VT));
}
assert(0 && "Unsupported extended type!");
- return MVT(MVT::Other); // Not reached
+ return EVT(EVT::Other); // Not reached
}
/// getNumRegisters - Return the number of registers that this ValueType will
@@ -565,13 +565,13 @@
/// into pieces. For types like i140, which are first promoted then expanded,
/// it is the number of registers needed to hold all the bits of the original
/// type. For an i140 on a 32 bit machine this means 5 registers.
- unsigned getNumRegisters(MVT VT) const {
+ unsigned getNumRegisters(EVT VT) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
return NumRegistersForVT[VT.getSimpleVT()];
}
if (VT.isVector()) {
- MVT VT1, VT2;
+ EVT VT1, VT2;
unsigned NumIntermediates;
return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
}
@@ -587,7 +587,7 @@
/// ShouldShrinkFPConstant - If true, then instruction selection should
/// seek to shrink the FP constant of the specified type to a smaller type
/// in order to save space and / or reduce runtime.
- virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
+ virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
/// hasTargetDAGCombine - If true, the target has custom DAG combine
/// transformations that it can perform for the specified node.
@@ -633,12 +633,12 @@
/// getOptimalMemOpType - Returns the target specific optimal type for load
/// and store operations as a result of memset, memcpy, and memmove lowering.
- /// It returns MVT::iAny if SelectionDAG should be responsible for
+ /// It returns EVT::iAny if SelectionDAG should be responsible for
/// determining it.
- virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
+ virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
bool isSrcConst, bool isSrcStr,
SelectionDAG &DAG) const {
- return MVT::iAny;
+ return EVT::iAny;
}
/// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
@@ -827,7 +827,7 @@
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
/// and cc. If it is unable to simplify it, return a null SDValue.
- SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
+ SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI, DebugLoc dl) const;
@@ -869,7 +869,7 @@
/// setShiftAmountType - Describe the type that should be used for shift
/// amounts. This type defaults to the pointer type.
- void setShiftAmountType(MVT::SimpleValueType VT) { ShiftAmountTy = VT; }
+ void setShiftAmountType(EVT::SimpleValueType VT) { ShiftAmountTy = VT; }
/// setBooleanContents - Specify how the target extends the result of a
/// boolean value from i1 to a wider type. See getBooleanContents.
@@ -932,7 +932,7 @@
/// addRegisterClass - Add the specified register class as an available
/// regclass for the specified value type. This indicates the selector can
/// handle values of that class natively.
- void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
+ void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
AvailableRegClasses.push_back(std::make_pair(VT, RC));
RegClassForVT[VT.getSimpleVT()] = RC;
@@ -944,7 +944,7 @@
/// setOperationAction - Indicate that the specified operation does not work
/// with the specified type and indicate what to do about it.
- void setOperationAction(unsigned Op, MVT::SimpleValueType VT,
+ void setOperationAction(unsigned Op, EVT::SimpleValueType VT,
LegalizeAction Action) {
unsigned I = (unsigned)VT;
unsigned J = I & 31;
@@ -955,7 +955,7 @@
/// setLoadExtAction - Indicate that the specified load with extension does
/// not work with the with specified type and indicate what to do about it.
- void setLoadExtAction(unsigned ExtType, MVT::SimpleValueType VT,
+ void setLoadExtAction(unsigned ExtType, EVT::SimpleValueType VT,
LegalizeAction Action) {
assert((unsigned)VT < sizeof(LoadExtActions[0])*4 &&
ExtType < array_lengthof(LoadExtActions) &&
@@ -966,8 +966,8 @@
/// setTruncStoreAction - Indicate that the specified truncating store does
/// not work with the with specified type and indicate what to do about it.
- void setTruncStoreAction(MVT::SimpleValueType ValVT,
- MVT::SimpleValueType MemVT,
+ void setTruncStoreAction(EVT::SimpleValueType ValVT,
+ EVT::SimpleValueType MemVT,
LegalizeAction Action) {
assert((unsigned)ValVT < array_lengthof(TruncStoreActions) &&
(unsigned)MemVT < sizeof(TruncStoreActions[0])*4 &&
@@ -980,9 +980,9 @@
/// does not work with the with specified type and indicate what to do abort
/// it. NOTE: All indexed mode loads are initialized to Expand in
/// TargetLowering.cpp
- void setIndexedLoadAction(unsigned IdxMode, MVT::SimpleValueType VT,
+ void setIndexedLoadAction(unsigned IdxMode, EVT::SimpleValueType VT,
LegalizeAction Action) {
- assert((unsigned)VT < MVT::LAST_VALUETYPE &&
+ assert((unsigned)VT < EVT::LAST_VALUETYPE &&
IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
"Table isn't big enough!");
IndexedModeActions[(unsigned)VT][0][IdxMode] = (uint8_t)Action;
@@ -992,9 +992,9 @@
/// does not work with the with specified type and indicate what to do about
/// it. NOTE: All indexed mode stores are initialized to Expand in
/// TargetLowering.cpp
- void setIndexedStoreAction(unsigned IdxMode, MVT::SimpleValueType VT,
+ void setIndexedStoreAction(unsigned IdxMode, EVT::SimpleValueType VT,
LegalizeAction Action) {
- assert((unsigned)VT < MVT::LAST_VALUETYPE &&
+ assert((unsigned)VT < EVT::LAST_VALUETYPE &&
IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
"Table isn't big enough!");
IndexedModeActions[(unsigned)VT][1][IdxMode] = (uint8_t)Action;
@@ -1002,7 +1002,7 @@
/// setConvertAction - Indicate that the specified conversion does or does
/// not work with the with specified type and indicate what to do about it.
- void setConvertAction(MVT::SimpleValueType FromVT, MVT::SimpleValueType ToVT,
+ void setConvertAction(EVT::SimpleValueType FromVT, EVT::SimpleValueType ToVT,
LegalizeAction Action) {
assert((unsigned)FromVT < array_lengthof(ConvertActions) &&
(unsigned)ToVT < sizeof(ConvertActions[0])*4 &&
@@ -1013,7 +1013,7 @@
/// setCondCodeAction - Indicate that the specified condition code is or isn't
/// supported on the target and indicate what to do about it.
- void setCondCodeAction(ISD::CondCode CC, MVT::SimpleValueType VT,
+ void setCondCodeAction(ISD::CondCode CC, EVT::SimpleValueType VT,
LegalizeAction Action) {
assert((unsigned)VT < sizeof(CondCodeActions[0])*4 &&
(unsigned)CC < array_lengthof(CondCodeActions) &&
@@ -1026,8 +1026,8 @@
/// promotion code defaults to trying a larger integer/fp until it can find
/// one that works. If that default is insufficient, this method can be used
/// by the target to override the default.
- void AddPromotedToType(unsigned Opc, MVT::SimpleValueType OrigVT,
- MVT::SimpleValueType DestVT) {
+ void AddPromotedToType(unsigned Opc, EVT::SimpleValueType OrigVT,
+ EVT::SimpleValueType DestVT) {
PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
}
@@ -1342,7 +1342,7 @@
Value *CallOperandVal;
/// ConstraintVT - The ValueType for the operand value.
- MVT ConstraintVT;
+ EVT ConstraintVT;
/// isMatchingInputConstraint - Return true of this is an input operand that
/// is a matching constraint like "4".
@@ -1355,7 +1355,7 @@
AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
: InlineAsm::ConstraintInfo(info),
ConstraintType(TargetLowering::C_Unknown),
- CallOperandVal(0), ConstraintVT(MVT::Other) {
+ CallOperandVal(0), ConstraintVT(EVT::Other) {
}
};
@@ -1379,7 +1379,7 @@
/// This should only be used for C_RegisterClass constraints.
virtual std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
/// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
/// {edx}), return the register number and the register class for the
@@ -1393,13 +1393,13 @@
/// this returns a register number of 0 and a null register class pointer..
virtual std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand. This returns null if there is no replacement to
/// make.
- virtual const char *LowerXConstraint(MVT ConstraintVT) const;
+ virtual const char *LowerXConstraint(EVT ConstraintVT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
@@ -1456,7 +1456,7 @@
return false;
}
- virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
+ virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
return false;
}
@@ -1472,14 +1472,14 @@
return false;
}
- virtual bool isZExtFree(MVT VT1, MVT VT2) const {
+ virtual bool isZExtFree(EVT VT1, EVT VT2) const {
return false;
}
/// isNarrowingProfitable - Return true if it's profitable to narrow
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
/// from i32 to i8 but not from i32 to i16.
- virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const {
+ virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
return false;
}
@@ -1527,7 +1527,7 @@
/// PointerTy - The type to use for pointers, usually i32 or i64.
///
- MVT::SimpleValueType PointerTy;
+ EVT::SimpleValueType PointerTy;
/// IsLittleEndian - True if this is a little endian target.
///
@@ -1562,7 +1562,7 @@
/// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
/// PointerTy is.
- MVT::SimpleValueType ShiftAmountTy;
+ EVT::SimpleValueType ShiftAmountTy;
/// BooleanContents - Information about the contents of the high-bits in
/// boolean values held in a type wider than i1. See getBooleanContents.
@@ -1608,16 +1608,16 @@
/// RegClassForVT - This indicates the default register class to use for
/// each ValueType the target supports natively.
- TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
- unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
- MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
+ TargetRegisterClass *RegClassForVT[EVT::LAST_VALUETYPE];
+ unsigned char NumRegistersForVT[EVT::LAST_VALUETYPE];
+ EVT RegisterTypeForVT[EVT::LAST_VALUETYPE];
/// TransformToType - For any value types we are promoting or expanding, this
/// contains the value type that we are changing to. For Expanded types, this
/// contains one step of the expand (e.g. i64 -> i32), even if there are
/// multiple steps required (e.g. i64 -> i16). For types natively supported
/// by the system, this holds the same type (e.g. i32 -> i32).
- MVT TransformToType[MVT::LAST_VALUETYPE];
+ EVT TransformToType[EVT::LAST_VALUETYPE];
/// OpActions - For each operation and each value type, keep a LegalizeAction
/// that indicates how instruction selection should deal with the operation.
@@ -1625,8 +1625,8 @@
/// operations that are not should be described. Note that operations on
/// non-legal value types are not described here.
/// This array is accessed using VT.getSimpleVT(), so it is subject to
- /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
- uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
+ /// the EVT::MAX_ALLOWED_VALUETYPE * 2 bits.
+ uint64_t OpActions[EVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
/// LoadExtActions - For each load of load extension type and each value type,
/// keep a LegalizeAction that indicates how instruction selection should deal
@@ -1635,7 +1635,7 @@
/// TruncStoreActions - For each truncating store, keep a LegalizeAction that
/// indicates how instruction selection should deal with the store.
- uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
+ uint64_t TruncStoreActions[EVT::LAST_VALUETYPE];
/// IndexedModeActions - For each indexed mode and each value type,
/// keep a pair of LegalizeAction that indicates how instruction
@@ -1643,14 +1643,14 @@
/// dimension is now the value_type for the reference. The second
/// dimension is the load [0] vs. store[1]. The third dimension
/// represents the various modes for load store.
- uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
+ uint8_t IndexedModeActions[EVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
/// ConvertActions - For each conversion from source type to destination type,
/// keep a LegalizeAction that indicates how instruction selection should
/// deal with the conversion.
/// Currently, this is used only for floating->floating conversions
/// (FP_EXTEND and FP_ROUND).
- uint64_t ConvertActions[MVT::LAST_VALUETYPE];
+ uint64_t ConvertActions[EVT::LAST_VALUETYPE];
/// CondCodeActions - For each condition code (ISD::CondCode) keep a
/// LegalizeAction that indicates how instruction selection should
@@ -1661,7 +1661,7 @@
std::vector<APFloat> LegalFPImmediates;
- std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
+ std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
/// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
@@ -1675,7 +1675,7 @@
///
/// Targets add entries to this map with AddPromotedToType(..), clients access
/// this with getTypeToPromoteTo(..).
- std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
+ std::map<std::pair<unsigned, EVT::SimpleValueType>, EVT::SimpleValueType>
PromoteToType;
/// LibcallRoutineNames - Stores the name each libcall.
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon Aug 10 17:56:29 2009
@@ -53,7 +53,7 @@
typedef const unsigned* iterator;
typedef const unsigned* const_iterator;
- typedef const MVT* vt_iterator;
+ typedef const EVT* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
unsigned ID;
@@ -70,7 +70,7 @@
public:
TargetRegisterClass(unsigned id,
const char *name,
- const MVT *vts,
+ const EVT *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
@@ -117,8 +117,8 @@
/// hasType - return true if this TargetRegisterClass has the ValueType vt.
///
- bool hasType(MVT vt) const {
- for(int i = 0; VTs[i] != MVT::Other; ++i)
+ bool hasType(EVT vt) const {
+ for(int i = 0; VTs[i] != EVT::Other; ++i)
if (VTs[i] == vt)
return true;
return false;
@@ -132,7 +132,7 @@
vt_iterator vt_end() const {
vt_iterator I = VTs;
- while (*I != MVT::Other) ++I;
+ while (*I != EVT::Other) ++I;
return I;
}
@@ -318,10 +318,10 @@
}
/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
- /// register of the given type. If type is MVT::Other, then just return any
+ /// register of the given type. If type is EVT::Other, then just return any
/// register class the register belongs to.
virtual const TargetRegisterClass *
- getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
+ getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not. If a register class is
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Aug 10 17:56:29 2009
@@ -512,48 +512,48 @@
}]>;
def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
}]>;
def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::f32;
}]>;
def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::f64;
}]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
}]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i1;
}]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
- return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<LoadSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
// store fragments.
@@ -573,23 +573,23 @@
}]>;
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
}]>;
def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f64;
}]>;
// indexed store fragments.
@@ -615,23 +615,23 @@
}]>;
def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i1;
}]>;
def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
}]>;
def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
@@ -647,23 +647,23 @@
}]>;
def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i1;
}]>;
def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset), [{
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
+ return cast<StoreSDNode>(N)->getMemoryVT() == EVT::f32;
}]>;
// setcc convenience fragments.
@@ -711,40 +711,40 @@
def atomic_cmp_swap_8 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def atomic_cmp_swap_16 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def atomic_cmp_swap_32 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
def atomic_cmp_swap_64 :
PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i64;
}]>;
multiclass binary_atomic_op<SDNode atomic_op> {
def _8 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i8;
}]>;
def _16 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i16;
}]>;
def _32 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i32;
}]>;
def _64 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val), [{
- return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+ return cast<AtomicSDNode>(N)->getMemoryVT() == EVT::i64;
}]>;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp Mon Aug 10 17:56:29 2009
@@ -33,8 +33,8 @@
// HandleByVal - Allocate a stack slot large enough to pass an argument by
// value. The size and alignment information of the argument is encoded in its
// parameter attribute.
-void CCState::HandleByVal(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
+void CCState::HandleByVal(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
int MinSize, int MinAlign,
ISD::ArgFlagsTy ArgFlags) {
unsigned Align = ArgFlags.getByValAlign();
@@ -65,12 +65,12 @@
unsigned NumArgs = Ins.size();
for (unsigned i = 0; i != NumArgs; ++i) {
- MVT ArgVT = Ins[i].VT;
+ EVT ArgVT = Ins[i].VT;
ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Formal argument #" << i << " has unhandled type "
- << ArgVT.getMVTString();
+ << ArgVT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -83,12 +83,12 @@
CCAssignFn Fn) {
// Determine which register each value should be copied into.
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
- MVT VT = Outs[i].Val.getValueType();
+ EVT VT = Outs[i].Val.getValueType();
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Return operand #" << i << " has unhandled type "
- << VT.getMVTString();
+ << VT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -102,12 +102,12 @@
CCAssignFn Fn) {
unsigned NumOps = Outs.size();
for (unsigned i = 0; i != NumOps; ++i) {
- MVT ArgVT = Outs[i].Val.getValueType();
+ EVT ArgVT = Outs[i].Val.getValueType();
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Call operand #" << i << " has unhandled type "
- << ArgVT.getMVTString();
+ << ArgVT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -116,17 +116,17 @@
/// AnalyzeCallOperands - Same as above except it takes vectors of types
/// and argument flags.
-void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
+void CCState::AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
CCAssignFn Fn) {
unsigned NumOps = ArgVTs.size();
for (unsigned i = 0; i != NumOps; ++i) {
- MVT ArgVT = ArgVTs[i];
+ EVT ArgVT = ArgVTs[i];
ISD::ArgFlagsTy ArgFlags = Flags[i];
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Call operand #" << i << " has unhandled type "
- << ArgVT.getMVTString();
+ << ArgVT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -138,12 +138,12 @@
void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
CCAssignFn Fn) {
for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
- MVT VT = Ins[i].VT;
+ EVT VT = Ins[i].VT;
ISD::ArgFlagsTy Flags = Ins[i].Flags;
if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
#ifndef NDEBUG
cerr << "Call result #" << i << " has unhandled type "
- << VT.getMVTString();
+ << VT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -152,11 +152,11 @@
/// AnalyzeCallResult - Same as above except it's specialized for calls which
/// produce a single value.
-void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
+void CCState::AnalyzeCallResult(EVT VT, CCAssignFn Fn) {
if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
#ifndef NDEBUG
cerr << "Call result has unhandled type "
- << VT.getMVTString();
+ << VT.getEVTString();
#endif
llvm_unreachable(0);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Aug 10 17:56:29 2009
@@ -215,12 +215,12 @@
SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
SDValue N3, ISD::CondCode CC,
bool NotExtCompare = false);
- SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
+ SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
DebugLoc DL, bool foldBooleans = true);
SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp);
- SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
- SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
+ SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
+ SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
SDValue BuildSDIV(SDNode *N);
SDValue BuildUDIV(SDNode *N);
SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
@@ -253,7 +253,7 @@
/// getShiftAmountTy - Returns a type large enough to hold any valid
/// shift amount - before type legalization these can be huge.
- MVT getShiftAmountTy() {
+ EVT getShiftAmountTy() {
return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
}
@@ -331,7 +331,7 @@
static char isNegatibleForFree(SDValue Op, bool LegalOperations,
unsigned Depth = 0) {
// No compile time optimizations on this type.
- if (Op.getValueType() == MVT::ppcf128)
+ if (Op.getValueType() == EVT::ppcf128)
return 0;
// fneg is removable even if it has multiple uses.
@@ -497,7 +497,7 @@
SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
SDValue N0, SDValue N1) {
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
if (isa<ConstantSDNode>(N1)) {
// reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
@@ -833,12 +833,12 @@
/// otherwise return a null sd operand.
static SDValue getInputChainForNode(SDNode *N) {
if (unsigned NumOps = N->getNumOperands()) {
- if (N->getOperand(0).getValueType() == MVT::Other)
+ if (N->getOperand(0).getValueType() == EVT::Other)
return N->getOperand(0);
- else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
+ else if (N->getOperand(NumOps-1).getValueType() == EVT::Other)
return N->getOperand(NumOps-1);
for (unsigned i = 1; i < NumOps-1; ++i)
- if (N->getOperand(i).getValueType() == MVT::Other)
+ if (N->getOperand(i).getValueType() == EVT::Other)
return N->getOperand(i);
}
return SDValue();
@@ -911,7 +911,7 @@
} else {
// New and improved token factor.
Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- MVT::Other, &Ops[0], Ops.size());
+ EVT::Other, &Ops[0], Ops.size());
}
// Don't add users to work list.
@@ -935,7 +935,7 @@
static
SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
SelectionDAG &DAG) {
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
@@ -959,7 +959,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -1082,13 +1082,13 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// If the flag result is dead, turn this into an ADD.
if (N->hasNUsesOfValue(0, 1))
return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), MVT::Flag));
+ N->getDebugLoc(), EVT::Flag));
// canonicalize constant to RHS.
if (N0C && !N1C)
@@ -1097,7 +1097,7 @@
// fold (addc x, 0) -> x + no carry out
if (N1C && N1C->isNullValue())
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), MVT::Flag));
+ N->getDebugLoc(), EVT::Flag));
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
APInt LHSZero, LHSOne;
@@ -1114,7 +1114,7 @@
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), MVT::Flag));
+ N->getDebugLoc(), EVT::Flag));
}
return SDValue();
@@ -1144,7 +1144,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -1217,7 +1217,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -1310,7 +1310,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -1397,7 +1397,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -1417,7 +1417,7 @@
if (N1.getOpcode() == ISD::SHL) {
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
if (SHC->getAPIntValue().isPowerOf2()) {
- MVT ADDVT = N1.getOperand(1).getValueType();
+ EVT ADDVT = N1.getOperand(1).getValueType();
SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
N1.getOperand(1),
DAG.getConstant(SHC->getAPIntValue()
@@ -1449,7 +1449,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (srem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
@@ -1491,7 +1491,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (urem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
@@ -1543,7 +1543,7 @@
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (mulhs x, 0) -> 0
if (N1C && N1C->isNullValue())
@@ -1564,7 +1564,7 @@
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (mulhu x, 0) -> 0
if (N1C && N1C->isNullValue())
@@ -1667,7 +1667,7 @@
/// two operands of the same opcode, try to simplify it.
SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
// For each of OP in AND/OR/XOR:
@@ -1713,7 +1713,7 @@
SDValue LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N1.getValueType();
+ EVT VT = N1.getValueType();
unsigned BitWidth = VT.getSizeInBits();
// fold vector ops
@@ -1824,7 +1824,7 @@
// fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
@@ -1846,7 +1846,7 @@
if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
@@ -1873,24 +1873,24 @@
LN0->isUnindexed() && N0.hasOneUse() &&
// Do not change the width of a volatile load.
!LN0->isVolatile()) {
- MVT EVT = MVT::Other;
+ EVT ExtVT = EVT::Other;
uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
- EVT = MVT::getIntegerVT(ActiveBits);
+ ExtVT = EVT::getIntegerVT(ActiveBits);
- MVT LoadedVT = LN0->getMemoryVT();
+ EVT LoadedVT = LN0->getMemoryVT();
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
- if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
- (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
- MVT PtrType = N0.getOperand(1).getValueType();
+ if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
+ (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
+ EVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to
// load the correct bytes. For little endian systems, we merely need to
// read fewer bytes from the same pointer.
unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
- unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
+ unsigned EVTStoreBytes = ExtVT.getStoreSizeInBits()/8;
unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
unsigned Alignment = LN0->getAlignment();
SDValue NewPtr = LN0->getBasePtr();
@@ -1905,7 +1905,7 @@
SDValue Load =
DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
- EVT, LN0->isVolatile(), Alignment);
+ ExtVT, LN0->isVolatile(), Alignment);
AddToWorkList(N);
CombineTo(N0.getNode(), Load, Load.getValue(1));
return SDValue(N, 0); // Return N so it doesn't get rechecked!
@@ -1922,7 +1922,7 @@
SDValue LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N1.getValueType();
+ EVT VT = N1.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -2062,7 +2062,7 @@
// a rot[lr].
SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
// Must be a legal type. Expanded 'n promoted things won't work with rotates.
- MVT VT = LHS.getValueType();
+ EVT VT = LHS.getValueType();
if (!TLI.isTypeLegal(VT)) return 0;
// The target must have at least one rotate flavor.
@@ -2223,7 +2223,7 @@
SDValue LHS, RHS, CC;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -2284,7 +2284,7 @@
}
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
- if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
+ if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
@@ -2391,7 +2391,7 @@
!isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
return SDValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// If this is a signed shift right, and the high bit is modified by the
// logical operation, do not perform the transformation. The highBitSet
@@ -2421,7 +2421,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
unsigned OpSizeInBits = VT.getSizeInBits();
// fold (shl c1, c2) -> c1<<c2
@@ -2446,7 +2446,7 @@
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
SDValue N101 = N1.getOperand(0).getOperand(1);
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
- MVT TruncVT = N1.getValueType();
+ EVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
APInt TruncC = N101C->getAPIntValue();
TruncC.trunc(TruncVT.getSizeInBits());
@@ -2513,7 +2513,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold (sra c1, c2) -> (sra c1, c2)
if (N0C && N1C)
@@ -2534,7 +2534,7 @@
// sext_inreg.
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
- MVT EVT = MVT::getIntegerVT(LowBits);
+ EVT EVT = EVT::getIntegerVT(LowBits);
if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
N0.getOperand(0), DAG.getValueType(EVT));
@@ -2561,8 +2561,8 @@
if (N01C && N1C) {
// Determine what the truncate's result bitsize and type would be.
unsigned VTValSize = VT.getSizeInBits();
- MVT TruncVT =
- MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
+ EVT TruncVT =
+ EVT::getIntegerVT(VTValSize - N1C->getZExtValue());
// Determine the residual right-shift amount.
signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
@@ -2592,7 +2592,7 @@
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
SDValue N101 = N1.getOperand(0).getOperand(1);
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
- MVT TruncVT = N1.getValueType();
+ EVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
APInt TruncC = N101C->getAPIntValue();
TruncC.trunc(TruncVT.getSizeInBits());
@@ -2623,7 +2623,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
unsigned OpSizeInBits = VT.getSizeInBits();
// fold (srl c1, c2) -> c1 >>u c2
@@ -2657,7 +2657,7 @@
// fold (srl (anyextend x), c) -> (anyextend (srl x, c))
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
// Shifting in all undef bits?
- MVT SmallVT = N0.getOperand(0).getValueType();
+ EVT SmallVT = N0.getOperand(0).getValueType();
if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
return DAG.getUNDEF(VT);
@@ -2716,7 +2716,7 @@
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
SDValue N101 = N1.getOperand(0).getOperand(1);
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
- MVT TruncVT = N1.getValueType();
+ EVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
APInt TruncC = N101C->getAPIntValue();
TruncC.trunc(TruncVT.getSizeInBits());
@@ -2740,7 +2740,7 @@
SDValue DAGCombiner::visitCTLZ(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (ctlz c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2750,7 +2750,7 @@
SDValue DAGCombiner::visitCTTZ(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (cttz c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2760,7 +2760,7 @@
SDValue DAGCombiner::visitCTPOP(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (ctpop c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2775,8 +2775,8 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
- MVT VT = N->getValueType(0);
- MVT VT0 = N0.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT VT0 = N0.getValueType();
// fold (select C, X, X) -> X
if (N1 == N2)
@@ -2788,11 +2788,11 @@
if (N0C && N0C->isNullValue())
return N2;
// fold (select C, 1, X) -> (or C, X)
- if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
+ if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1)
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select C, 0, 1) -> (xor C, 1)
if (VT.isInteger() &&
- (VT0 == MVT::i1 ||
+ (VT0 == EVT::i1 ||
(VT0.isInteger() &&
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
@@ -2808,27 +2808,27 @@
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
}
// fold (select C, 0, X) -> (and (not C), X)
- if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
+ if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
}
// fold (select C, X, 1) -> (or (not C), X)
- if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
+ if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
}
// fold (select C, X, 0) -> (and C, X)
- if (VT == MVT::i1 && N2C && N2C->isNullValue())
+ if (VT == EVT::i1 && N2C && N2C->isNullValue())
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// fold (select X, X, Y) -> (or X, Y)
// fold (select X, 1, Y) -> (or X, Y)
- if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
+ if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select X, Y, X) -> (and X, Y)
// fold (select X, Y, 0) -> (and X, Y)
- if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
+ if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// If we can fold this based on the true/false value, do so.
@@ -2838,10 +2838,10 @@
// fold selects based on a setcc into other things, such as min/max/abs
if (N0.getOpcode() == ISD::SETCC) {
// FIXME:
- // Check against MVT::Other for SELECT_CC, which is a workaround for targets
+ // Check against EVT::Other for SELECT_CC, which is a workaround for targets
// having to say they don't support SELECT_CC on every type the DAG knows
// about, since there is no way to mark an opcode illegal at all value types
- if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
+ if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) &&
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
N0.getOperand(0), N0.getOperand(1),
@@ -2962,7 +2962,7 @@
SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (sext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -3071,7 +3071,7 @@
if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
@@ -3127,7 +3127,7 @@
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (zext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -3231,7 +3231,7 @@
if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
@@ -3262,7 +3262,7 @@
SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (aext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -3367,7 +3367,7 @@
!ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
VT, LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
@@ -3437,8 +3437,8 @@
unsigned Opc = N->getOpcode();
ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
- MVT EVT = VT;
+ EVT VT = N->getValueType(0);
+ EVT ExtVT = VT;
// This transformation isn't valid for vector loads.
if (VT.isVector())
@@ -3448,12 +3448,12 @@
// extended to VT.
if (Opc == ISD::SIGN_EXTEND_INREG) {
ExtType = ISD::SEXTLOAD;
- EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
- if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
+ ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
return SDValue();
}
- unsigned EVTBits = EVT.getSizeInBits();
+ unsigned EVTBits = ExtVT.getSizeInBits();
unsigned ShAmt = 0;
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
@@ -3469,18 +3469,18 @@
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
- if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
+ if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
// Do not change the width of a volatile load.
!cast<LoadSDNode>(N0)->isVolatile()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT PtrType = N0.getOperand(1).getValueType();
+ EVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to adjust the offset to the pointer to
// load the correct bytes.
if (TLI.isBigEndian()) {
unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
- unsigned EVTStoreBits = EVT.getStoreSizeInBits();
+ unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
}
@@ -3497,7 +3497,7 @@
LN0->isVolatile(), NewAlign)
: DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
- EVT, LN0->isVolatile(), NewAlign);
+ ExtVT, LN0->isVolatile(), NewAlign);
// Replace the old load's chain with the new load's chain.
WorkListRemover DeadNodes(*this);
@@ -3514,8 +3514,8 @@
SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
- MVT VT = N->getValueType(0);
- MVT EVT = cast<VTSDNode>(N1)->getVT();
+ EVT VT = N->getValueType(0);
+ EVT EVT = cast<VTSDNode>(N1)->getVT();
unsigned VTBits = VT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
@@ -3610,7 +3610,7 @@
SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// noop truncate
if (N0.getValueType() == N->getValueType(0))
@@ -3660,14 +3660,14 @@
/// CombineConsecutiveLoads - build_pair (load, load) -> load
/// if load locations are consecutive.
-SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
+SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
assert(N->getOpcode() == ISD::BUILD_PAIR);
LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
return SDValue();
- MVT LD1VT = LD1->getValueType(0);
+ EVT LD1VT = LD1->getValueType(0);
const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
if (ISD::isNON_EXTLoad(LD2) &&
@@ -3679,7 +3679,7 @@
TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
unsigned Align = LD1->getAlignment();
unsigned NewAlign = TLI.getTargetData()->
- getABITypeAlignment(VT.getTypeForMVT());
+ getABITypeAlignment(VT.getTypeForEVT());
if (NewAlign <= Align &&
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
@@ -3693,7 +3693,7 @@
SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// If the input is a BUILD_VECTOR with all constant elements, fold this now.
// Only do this before legalize, since afterward the target may be depending
@@ -3711,7 +3711,7 @@
break;
}
- MVT DestEltVT = N->getValueType(0).getVectorElementType();
+ EVT DestEltVT = N->getValueType(0).getVectorElementType();
assert(!DestEltVT.isVector() &&
"Element type of vector ValueType must not be vector!");
if (isSimple)
@@ -3737,7 +3737,7 @@
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
unsigned Align = TLI.getTargetData()->
- getABITypeAlignment(VT.getTypeForMVT());
+ getABITypeAlignment(VT.getTypeForEVT());
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
@@ -3780,7 +3780,7 @@
isa<ConstantFPSDNode>(N0.getOperand(0)) &&
VT.isInteger() && !VT.isVector()) {
unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
- MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
+ EVT IntXVT = EVT::getIntegerVT(OrigXWidth);
if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
IntXVT, N0.getOperand(1));
@@ -3828,7 +3828,7 @@
}
SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
return CombineConsecutiveLoads(N, VT);
}
@@ -3836,8 +3836,8 @@
/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
/// destination element value type.
SDValue DAGCombiner::
-ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
- MVT SrcEltVT = BV->getValueType(0).getVectorElementType();
+ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
+ EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
// If this is already the right type, we're done.
if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
@@ -3859,7 +3859,7 @@
DstEltVT, Op));
AddToWorkList(Ops.back().getNode());
}
- MVT VT = MVT::getVectorVT(DstEltVT,
+ EVT VT = EVT::getVectorVT(DstEltVT,
BV->getValueType(0).getVectorNumElements());
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
&Ops[0], Ops.size());
@@ -3871,8 +3871,8 @@
if (SrcEltVT.isFloatingPoint()) {
// Convert the input float vector to a int vector where the elements are the
// same sizes.
- assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
- MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
+ assert((SrcEltVT == EVT::f32 || SrcEltVT == EVT::f64) && "Unknown FP VT!");
+ EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits());
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
SrcEltVT = IntVT;
}
@@ -3880,8 +3880,8 @@
// Now we know the input is an integer vector. If the output is a FP type,
// convert to integer first, then to FP of the right size.
if (DstEltVT.isFloatingPoint()) {
- assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
- MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
+ assert((DstEltVT == EVT::f32 || DstEltVT == EVT::f64) && "Unknown FP VT!");
+ EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits());
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
// Next, convert to FP elements of the same size.
@@ -3917,7 +3917,7 @@
Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
}
- MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
+ EVT VT = EVT::getVectorVT(DstEltVT, Ops.size());
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
@@ -3926,7 +3926,7 @@
// turns into multiple outputs.
bool isS2V = ISD::isScalarToVector(BV);
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
- MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
+ EVT VT = EVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
@@ -3963,7 +3963,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -3972,7 +3972,7 @@
}
// fold (fadd c1, c2) -> (fadd c1, c2)
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
@@ -4004,7 +4004,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -4013,7 +4013,7 @@
}
// fold (fsub c1, c2) -> c1-c2
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
// fold (fsub A, 0) -> A
if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
@@ -4038,7 +4038,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -4047,7 +4047,7 @@
}
// fold (fmul c1, c2) -> c1*c2
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
@@ -4093,7 +4093,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -4102,7 +4102,7 @@
}
// fold (fdiv c1, c2) -> c1/c2
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
@@ -4126,10 +4126,10 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (frem c1, c2) -> fmod(c1,c2)
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
return SDValue();
@@ -4140,9 +4140,9 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
- if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
+ if (N0CFP && N1CFP && VT != EVT::ppcf128) // Constant fold
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
if (N1CFP) {
@@ -4188,11 +4188,11 @@
SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
- MVT VT = N->getValueType(0);
- MVT OpVT = N0.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT OpVT = N0.getValueType();
// fold (sint_to_fp c1) -> c1fp
- if (N0C && OpVT != MVT::ppcf128)
+ if (N0C && OpVT != EVT::ppcf128)
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and SINT_TO_FP is not legal on this target,
@@ -4210,11 +4210,11 @@
SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
- MVT VT = N->getValueType(0);
- MVT OpVT = N0.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT OpVT = N0.getValueType();
// fold (uint_to_fp c1) -> c1fp
- if (N0C && OpVT != MVT::ppcf128)
+ if (N0C && OpVT != EVT::ppcf128)
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and UINT_TO_FP is not legal on this target,
@@ -4232,7 +4232,7 @@
SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fp_to_sint c1fp) -> c1
if (N0CFP)
@@ -4244,10 +4244,10 @@
SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fp_to_uint c1fp) -> c1
- if (N0CFP && VT != MVT::ppcf128)
+ if (N0CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
return SDValue();
@@ -4257,10 +4257,10 @@
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fp_round c1fp) -> c1fp
- if (N0CFP && N0.getValueType() != MVT::ppcf128)
+ if (N0CFP && N0.getValueType() != EVT::ppcf128)
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
// fold (fp_round (fp_extend x)) -> x
@@ -4290,8 +4290,8 @@
SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT VT = N->getValueType(0);
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
// fold (fp_round_inreg c1fp) -> c1fp
@@ -4306,7 +4306,7 @@
SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
if (N->hasOneUse() &&
@@ -4314,7 +4314,7 @@
return SDValue();
// fold (fp_extend c1fp) -> c1fp
- if (N0CFP && VT != MVT::ppcf128)
+ if (N0CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
@@ -4363,7 +4363,7 @@
N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) {
SDValue Int = N0.getOperand(0);
- MVT IntVT = Int.getValueType();
+ EVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
@@ -4379,10 +4379,10 @@
SDValue DAGCombiner::visitFABS(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fabs c1) -> fabs(c1)
- if (N0CFP && VT != MVT::ppcf128)
+ if (N0CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
// fold (fabs (fabs x)) -> (fabs x)
if (N0.getOpcode() == ISD::FABS)
@@ -4398,7 +4398,7 @@
N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) {
SDValue Int = N0.getOperand(0);
- MVT IntVT = Int.getValueType();
+ EVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
@@ -4422,12 +4422,12 @@
return Chain;
// unconditional branch
if (N1C && N1C->getAPIntValue() == 1)
- return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, Chain, N2);
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
// on the target.
if (N1.getOpcode() == ISD::SETCC &&
- TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
+ TLI.isOperationLegalOrCustom(ISD::BR_CC, EVT::Other)) {
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
Chain, N1.getOperand(2),
N1.getOperand(0), N1.getOperand(1), N2);
}
@@ -4475,7 +4475,7 @@
removeFromWorkList(N1.getNode());
DAG.DeleteNode(N1.getNode());
return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
- MVT::Other, Chain, SetCC, N2);
+ EVT::Other, Chain, SetCC, N2);
}
}
}
@@ -4500,7 +4500,7 @@
// fold br_cc true, dest -> br dest (unconditional branch)
if (SCCC && !SCCC->isNullValue())
- return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other,
N->getOperand(0), N->getOperand(4));
// fold br_cc false, dest -> unconditional fall through
if (SCCC && SCCC->isNullValue())
@@ -4508,7 +4508,7 @@
// fold to a simpler setcc
if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
N->getOperand(0), Simp.getOperand(2),
Simp.getOperand(0), Simp.getOperand(1),
N->getOperand(4));
@@ -4528,7 +4528,7 @@
bool isLoad = true;
SDValue Ptr;
- MVT VT;
+ EVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
@@ -4653,7 +4653,7 @@
bool isLoad = true;
SDValue Ptr;
- MVT VT;
+ EVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
@@ -4843,7 +4843,7 @@
// the updated indexed value in case of indexed loads), change uses of the
// chain value into uses of the chain input (i.e. delete the dead load).
if (!LD->isVolatile()) {
- if (N->getValueType(1) == MVT::Other) {
+ if (N->getValueType(1) == EVT::Other) {
// Unindexed loads.
if (N->hasNUsesOfValue(0, 0)) {
// It's not safe to use the two value CombineTo variant here. e.g.
@@ -4867,7 +4867,7 @@
}
} else {
// Indexed loads.
- assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
+ assert(N->getValueType(2) == EVT::Other && "Malformed indexed loads?");
if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
SDValue Undef = DAG.getUNDEF(N->getValueType(0));
DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
@@ -4926,7 +4926,7 @@
// Create token factor to keep old chain connected.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- MVT::Other, Chain, ReplLoad.getValue(1));
+ EVT::Other, Chain, ReplLoad.getValue(1));
// Replace uses with load result and token factor. Don't add users
// to work list.
@@ -4954,7 +4954,7 @@
SDValue Chain = ST->getChain();
SDValue Value = ST->getValue();
SDValue Ptr = ST->getBasePtr();
- MVT VT = Value.getValueType();
+ EVT VT = Value.getValueType();
if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
return SDValue();
@@ -4981,12 +4981,12 @@
unsigned ShAmt = Imm.countTrailingZeros();
unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
unsigned NewBW = NextPowerOf2(MSB - ShAmt);
- MVT NewVT = MVT::getIntegerVT(NewBW);
+ EVT NewVT = EVT::getIntegerVT(NewBW);
while (NewBW < BitWidth &&
!(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
TLI.isNarrowingProfitable(VT, NewVT))) {
NewBW = NextPowerOf2(NewBW);
- NewVT = MVT::getIntegerVT(NewBW);
+ NewVT = EVT::getIntegerVT(NewBW);
}
if (NewBW >= BitWidth)
return SDValue();
@@ -5008,7 +5008,7 @@
unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
if (NewAlign <
- TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT()))
+ TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT()))
return SDValue();
SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
@@ -5061,9 +5061,9 @@
if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
ST->isUnindexed()) {
unsigned OrigAlign = ST->getAlignment();
- MVT SVT = Value.getOperand(0).getValueType();
+ EVT SVT = Value.getOperand(0).getValueType();
unsigned Align = TLI.getTargetData()->
- getABITypeAlignment(SVT.getTypeForMVT());
+ getABITypeAlignment(SVT.getTypeForEVT());
if (Align <= OrigAlign &&
((!LegalOperations && !ST->isVolatile()) ||
TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
@@ -5082,40 +5082,40 @@
SDValue Tmp;
switch (CFP->getValueType(0).getSimpleVT()) {
default: llvm_unreachable("Unknown FP type");
- case MVT::f80: // We don't do this for these yet.
- case MVT::f128:
- case MVT::ppcf128:
+ case EVT::f80: // We don't do this for these yet.
+ case EVT::f128:
+ case EVT::ppcf128:
break;
- case MVT::f32:
- if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
+ case EVT::f32:
+ if (((TLI.isTypeLegal(EVT::i32) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
- bitcastToAPInt().getZExtValue(), MVT::i32);
+ bitcastToAPInt().getZExtValue(), EVT::i32);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
}
break;
- case MVT::f64:
- if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
+ case EVT::f64:
+ if (((TLI.isTypeLegal(EVT::i64) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i64)) {
Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- getZExtValue(), MVT::i64);
+ getZExtValue(), EVT::i64);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
} else if (!ST->isVolatile() &&
- TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
// Many FP stores are not made apparent until after legalize, e.g. for
// argument passing. Since this is so common, custom legalize the
// 64-bit integer store into two 32-bit stores.
uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
- SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
- SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
+ SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, EVT::i32);
+ SDValue Hi = DAG.getConstant(Val >> 32, EVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
int SVOffset = ST->getSrcValueOffset();
@@ -5133,7 +5133,7 @@
SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
Ptr, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
St0, St1);
}
@@ -5163,7 +5163,7 @@
// Create token to keep both nodes around.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- MVT::Other, Chain, ReplStore);
+ EVT::Other, Chain, ReplStore);
// Don't add users to work list.
return CombineTo(N, Token, false);
@@ -5248,8 +5248,8 @@
// BUILD_VECTOR with undef elements and the inserted element.
if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
isa<ConstantSDNode>(EltNo)) {
- MVT VT = InVec.getValueType();
- MVT EVT = VT.getVectorElementType();
+ EVT VT = InVec.getValueType();
+ EVT EVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
@@ -5269,7 +5269,7 @@
if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
// If the operand is wider than the vector element type then it is implicitly
// truncated. Make that explicit here.
- MVT EltVT = InVec.getValueType().getVectorElementType();
+ EVT EltVT = InVec.getValueType().getVectorElementType();
SDValue InOp = InVec.getOperand(0);
if (InOp.getValueType() != EltVT)
return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp);
@@ -5289,18 +5289,18 @@
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
bool NewLoad = false;
bool BCNumEltsChanged = false;
- MVT VT = InVec.getValueType();
- MVT EVT = VT.getVectorElementType();
- MVT LVT = EVT;
+ EVT VT = InVec.getValueType();
+ EVT ExtVT = VT.getVectorElementType();
+ EVT LVT = ExtVT;
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
- MVT BCVT = InVec.getOperand(0).getValueType();
- if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
+ EVT BCVT = InVec.getOperand(0).getValueType();
+ if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
return SDValue();
if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
BCNumEltsChanged = true;
InVec = InVec.getOperand(0);
- EVT = BCVT.getVectorElementType();
+ ExtVT = BCVT.getVectorElementType();
NewLoad = true;
}
@@ -5309,7 +5309,7 @@
if (ISD::isNormalLoad(InVec.getNode())) {
LN0 = cast<LoadSDNode>(InVec);
} else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
- InVec.getOperand(0).getValueType() == EVT &&
+ InVec.getOperand(0).getValueType() == ExtVT &&
ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
LN0 = cast<LoadSDNode>(InVec.getOperand(0));
} else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
@@ -5343,7 +5343,7 @@
// Check the resultant load doesn't need a higher alignment than the
// original load.
unsigned NewAlign =
- TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
+ TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT());
if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
return SDValue();
@@ -5354,7 +5354,7 @@
SDValue NewPtr = LN0->getBasePtr();
if (Elt) {
unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
- MVT PtrType = NewPtr.getValueType();
+ EVT PtrType = NewPtr.getValueType();
if (TLI.isBigEndian())
PtrOff = VT.getSizeInBits() / 8 - PtrOff;
NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
@@ -5371,8 +5371,8 @@
SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
unsigned NumInScalars = N->getNumOperands();
- MVT VT = N->getValueType(0);
- MVT EltType = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltType = VT.getVectorElementType();
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
// operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
@@ -5469,7 +5469,7 @@
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
return SDValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
unsigned NumElts = VT.getVectorNumElements();
SDValue N0 = N->getOperand(0);
@@ -5531,7 +5531,7 @@
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
/// vector_shuffle V, Zero, <0, 4, 2, 4>
SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
@@ -5554,12 +5554,12 @@
}
// Let's see if the target supports this vector_shuffle.
- MVT RVT = RHS.getValueType();
+ EVT RVT = RHS.getValueType();
if (!TLI.isVectorClearMaskLegal(Indices, RVT))
return SDValue();
// Return the new VECTOR_SHUFFLE node.
- MVT EVT = RVT.getVectorElementType();
+ EVT EVT = RVT.getVectorElementType();
SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
DAG.getConstant(0, EVT));
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
@@ -5580,10 +5580,10 @@
// things. Simplifying them may result in a loss of legality.
if (LegalOperations) return SDValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
- MVT EltType = VT.getVectorElementType();
+ EVT EltType = VT.getVectorElementType();
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue Shuffle = XformToShuffleWithZero(N);
@@ -5626,7 +5626,7 @@
}
if (Ops.size() == LHS.getNumOperands()) {
- MVT VT = LHS.getValueType();
+ EVT VT = LHS.getValueType();
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
@@ -5765,7 +5765,7 @@
// (x ? y : y) -> y.
if (N2 == N3) return N2;
- MVT VT = N2.getValueType();
+ EVT VT = N2.getValueType();
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
@@ -5857,8 +5857,8 @@
N2.getValueType().isInteger() &&
(N1C->isNullValue() || // (a < 0) ? b : 0
(N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
- MVT XType = N0.getValueType();
- MVT AType = N2.getValueType();
+ EVT XType = N0.getValueType();
+ EVT AType = N2.getValueType();
if (XType.bitsGE(AType)) {
// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
// single-bit constant.
@@ -5916,7 +5916,7 @@
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
} else {
- SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
+ SCC = DAG.getSetCC(N0.getDebugLoc(), EVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
}
@@ -5937,7 +5937,7 @@
// FIXME: Turn all of these into setcc if setcc if setcc is legal
// otherwise, go ahead with the folds.
if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
- MVT XType = N0.getValueType();
+ EVT XType = N0.getValueType();
if (!LegalOperations ||
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
@@ -5979,7 +5979,7 @@
if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
- MVT XType = N0.getValueType();
+ EVT XType = N0.getValueType();
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
DAG.getConstant(XType.getSizeInBits()-1,
getShiftAmountTy()));
@@ -5994,7 +5994,7 @@
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
- MVT XType = N0.getValueType();
+ EVT XType = N0.getValueType();
if (SubC->isNullValue() && XType.isInteger()) {
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
N0,
@@ -6013,7 +6013,7 @@
}
/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
-SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
+SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
SDValue N1, ISD::CondCode Cond,
DebugLoc DL, bool foldBooleans) {
TargetLowering::DAGCombinerInfo
@@ -6223,7 +6223,7 @@
}
// Construct a custom tailored token factor.
- SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
+ SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
&Aliases[0], Aliases.size());
// Make sure the old chain gets cleaned up.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Aug 10 17:56:29 2009
@@ -57,7 +57,7 @@
using namespace llvm;
unsigned FastISel::getRegForValue(Value *V) {
- MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
+ EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
// Don't handle non-simple values in FastISel.
if (!RealVT.isSimple())
return 0;
@@ -65,10 +65,10 @@
// Ignore illegal types. We must do this before looking up the value
// in ValueMap because Arguments are given virtual registers regardless
// of whether FastISel can handle them.
- MVT::SimpleValueType VT = RealVT.getSimpleVT();
+ EVT::SimpleValueType VT = RealVT.getSimpleVT();
if (!TLI.isTypeLegal(VT)) {
- // Promote MVT::i1 to a legal type though, because it's common and easy.
- if (VT == MVT::i1)
+ // Promote EVT::i1 to a legal type though, because it's common and easy.
+ if (VT == EVT::i1)
VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
else
return 0;
@@ -98,7 +98,7 @@
if (!Reg) {
const APFloat &Flt = CF->getValueAPF();
- MVT IntVT = TLI.getPointerTy();
+ EVT IntVT = TLI.getPointerTy();
uint64_t x[2];
uint32_t IntBitWidth = IntVT.getSizeInBits();
@@ -174,8 +174,8 @@
return 0;
// If the index is smaller or larger than intptr_t, truncate or extend it.
- MVT PtrVT = TLI.getPointerTy();
- MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
+ EVT PtrVT = TLI.getPointerTy();
+ EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
if (IdxVT.bitsLT(PtrVT))
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
ISD::SIGN_EXTEND, IdxN);
@@ -189,8 +189,8 @@
/// which has an opcode which directly corresponds to the given ISD opcode.
///
bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
- MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !VT.isSimple())
+ EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
+ if (VT == EVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -199,9 +199,9 @@
// under the assumption that i64 won't be used if the target doesn't
// support it.
if (!TLI.isTypeLegal(VT)) {
- // MVT::i1 is special. Allow AND, OR, or XOR because they
+ // EVT::i1 is special. Allow AND, OR, or XOR because they
// don't require additional zeroing, which makes them easy.
- if (VT == MVT::i1 &&
+ if (VT == EVT::i1 &&
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
ISDOpcode == ISD::XOR))
VT = TLI.getTypeToTransformTo(VT);
@@ -261,7 +261,7 @@
return false;
const Type *Ty = I->getOperand(0)->getType();
- MVT::SimpleValueType VT = TLI.getPointerTy();
+ EVT::SimpleValueType VT = TLI.getPointerTy();
for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
OI != E; ++OI) {
Value *Idx = *OI;
@@ -432,7 +432,7 @@
return true;
}
case Intrinsic::eh_exception: {
- MVT VT = TLI.getValueType(I->getType());
+ EVT VT = TLI.getValueType(I->getType());
switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
default: break;
case TargetLowering::Expand: {
@@ -452,12 +452,12 @@
}
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
- MVT VT = TLI.getValueType(I->getType());
+ EVT VT = TLI.getValueType(I->getType());
switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
default: break;
case TargetLowering::Expand: {
- MVT VT = (IID == Intrinsic::eh_selector_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (IID == Intrinsic::eh_selector_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
if (MBB->isLandingPad())
@@ -494,11 +494,11 @@
}
bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple())
+ if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
+ DstVT == EVT::Other || !DstVT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -506,7 +506,7 @@
// it may be i1 if we're doing a truncate because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(DstVT))
- if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
+ if (DstVT != EVT::i1 || Opcode != ISD::TRUNCATE)
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -514,7 +514,7 @@
// it may be i1 if we're doing zero-extension because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(SrcVT))
- if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
+ if (SrcVT != EVT::i1 || Opcode != ISD::ZERO_EXTEND)
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -524,14 +524,14 @@
return false;
// If the operand is i1, arrange for the high bits in the register to be zero.
- if (SrcVT == MVT::i1) {
+ if (SrcVT == EVT::i1) {
SrcVT = TLI.getTypeToTransformTo(SrcVT);
InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
if (!InputReg)
return false;
}
// If the result is i1, truncate to the target's type for i1 first.
- if (DstVT == MVT::i1)
+ if (DstVT == EVT::i1)
DstVT = TLI.getTypeToTransformTo(DstVT);
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
@@ -556,11 +556,11 @@
}
// Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
+ if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
+ DstVT == EVT::Other || !DstVT.isSimple() ||
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -710,8 +710,8 @@
case Instruction::IntToPtr: // Deliberate fall-through.
case Instruction::PtrToInt: {
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
if (DstVT.bitsGT(SrcVT))
return SelectCast(I, ISD::ZERO_EXTEND);
if (DstVT.bitsLT(SrcVT))
@@ -759,45 +759,45 @@
FastISel::~FastISel() {}
-unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType) {
return 0;
}
-unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_r(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_rr(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/,
unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_i(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_f(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_ri(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/,
uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_rf(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/,
ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType,
unsigned /*Op0*/, unsigned /*Op1*/,
uint64_t /*Imm*/) {
@@ -808,9 +808,9 @@
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
-unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- MVT::SimpleValueType ImmType) {
+ EVT::SimpleValueType ImmType) {
// First check if immediate type is legal. If not, we can't use the ri form.
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
if (ResultReg != 0)
@@ -825,9 +825,9 @@
/// to emit an instruction with a floating-point immediate operand using
/// FastEmit_rf. If that fails, it materializes the immediate into a register
/// and try FastEmit_rr instead.
-unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_rf_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- MVT::SimpleValueType ImmType) {
+ EVT::SimpleValueType ImmType) {
// First check if immediate type is legal. If not, we can't use the rf form.
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
if (ResultReg != 0)
@@ -843,7 +843,7 @@
// be replaced by code that creates a load from a constant-pool entry,
// which will require some target-specific work.
const APFloat &Flt = FPImm->getValueAPF();
- MVT IntVT = TLI.getPointerTy();
+ EVT IntVT = TLI.getPointerTy();
uint64_t x[2];
uint32_t IntBitWidth = IntVT.getSizeInBits();
@@ -988,7 +988,7 @@
return ResultReg;
}
-unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
+unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx) {
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
@@ -1009,6 +1009,6 @@
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
-unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
+unsigned FastISel::FastEmitZExtFromI1(EVT::SimpleValueType VT, unsigned Op) {
return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Aug 10 17:56:29 2009
@@ -100,13 +100,13 @@
/// getTypeAction - Return how we should legalize values of this type, either
/// it is already legal or we need to expand it into multiple registers of
/// smaller integer type, or we need to promote it to a larger type.
- LegalizeAction getTypeAction(MVT VT) const {
+ LegalizeAction getTypeAction(EVT VT) const {
return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
}
/// isTypeLegal - Return true if this type is legal on this target.
///
- bool isTypeLegal(MVT VT) const {
+ bool isTypeLegal(EVT VT) const {
return getTypeAction(VT) == Legal;
}
@@ -133,14 +133,14 @@
/// performs the same shuffe in terms of order or result bytes, but on a type
/// whose vector element type is narrower than the original shuffle type.
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
- SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
+ SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
SDValue N1, SDValue N2,
SmallVectorImpl<int> &Mask) const;
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
- void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
+ void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
DebugLoc dl);
SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
@@ -151,18 +151,18 @@
RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
RTLIB::Libcall Call_I128);
- SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
+ SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
SDValue ExpandBUILD_VECTOR(SDNode *Node);
SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
SDValue ExpandDBG_STOPPOINT(SDNode *Node);
void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
SmallVectorImpl<SDValue> &Results);
SDValue ExpandFCOPYSIGN(SDNode *Node);
- SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
+ SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
DebugLoc dl);
- SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
+ SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
DebugLoc dl);
- SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
+ SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
DebugLoc dl);
SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
@@ -181,10 +181,10 @@
/// whose vector element type is narrower than the original shuffle type.
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
SDValue
-SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
+SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
SDValue N1, SDValue N2,
SmallVectorImpl<int> &Mask) const {
- MVT EltVT = NVT.getVectorElementType();
+ EVT EltVT = NVT.getVectorElementType();
unsigned NumMaskElts = VT.getVectorNumElements();
unsigned NumDestElts = NVT.getVectorNumElements();
unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
@@ -213,7 +213,7 @@
CodeGenOpt::Level ol)
: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
+ assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
@@ -254,19 +254,19 @@
// The chain is usually at the end.
SDValue TheChain(Node, Node->getNumValues()-1);
- if (TheChain.getValueType() != MVT::Other) {
+ if (TheChain.getValueType() != EVT::Other) {
// Sometimes it's at the beginning.
TheChain = SDValue(Node, 0);
- if (TheChain.getValueType() != MVT::Other) {
+ if (TheChain.getValueType() != EVT::Other) {
// Otherwise, hunt for it.
for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
- if (Node->getValueType(i) == MVT::Other) {
+ if (Node->getValueType(i) == EVT::Other) {
TheChain = SDValue(Node, i);
break;
}
// Otherwise, we walked into a node without a chain.
- if (TheChain.getValueType() != MVT::Other)
+ if (TheChain.getValueType() != EVT::Other)
return 0;
}
}
@@ -290,7 +290,7 @@
assert(Node && "Didn't find callseq_start for a call??");
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
- assert(Node->getOperand(0).getValueType() == MVT::Other &&
+ assert(Node->getOperand(0).getValueType() == EVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
}
@@ -344,24 +344,24 @@
// double. This shrinks FP constants and canonicalizes them for targets where
// an FP extending load is the same cost as a normal load (such as on the x87
// fp stack or PPC FP unit).
- MVT VT = CFP->getValueType(0);
+ EVT VT = CFP->getValueType(0);
ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
if (!UseCP) {
- assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
+ assert((VT == EVT::f64 || VT == EVT::f32) && "Invalid type expansion");
return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
- (VT == MVT::f64) ? MVT::i64 : MVT::i32);
+ (VT == EVT::f64) ? EVT::i64 : EVT::i32);
}
- MVT OrigVT = VT;
- MVT SVT = VT;
- while (SVT != MVT::f32) {
- SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
+ EVT OrigVT = VT;
+ EVT SVT = VT;
+ while (SVT != EVT::f32) {
+ SVT = (EVT::SimpleValueType)(SVT.getSimpleVT() - 1);
if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
// Only do this if the target has a native EXTLOAD instruction from
// smaller type.
TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
TLI.ShouldShrinkFPConstant(OrigVT)) {
- const Type *SType = SVT.getTypeForMVT();
+ const Type *SType = SVT.getTypeForEVT();
LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
VT = SVT;
Extend = true;
@@ -386,13 +386,13 @@
SDValue Chain = ST->getChain();
SDValue Ptr = ST->getBasePtr();
SDValue Val = ST->getValue();
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
int SVOffset = ST->getSrcValueOffset();
DebugLoc dl = ST->getDebugLoc();
if (ST->getMemoryVT().isFloatingPoint() ||
ST->getMemoryVT().isVector()) {
- MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
+ EVT intVT = EVT::getIntegerVT(VT.getSizeInBits());
if (TLI.isTypeLegal(intVT)) {
// Expand to a bitconvert of the value to the integer type of the
// same size, then a (misaligned) int store.
@@ -403,9 +403,9 @@
} else {
// Do a (aligned) store to a stack slot, then copy from the stack slot
// to the final destination using (unaligned) integer loads and stores.
- MVT StoredVT = ST->getMemoryVT();
- MVT RegVT =
- TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
+ EVT StoredVT = ST->getMemoryVT();
+ EVT RegVT =
+ TLI.getRegisterType(EVT::getIntegerVT(StoredVT.getSizeInBits()));
unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
unsigned RegBytes = RegVT.getSizeInBits() / 8;
unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
@@ -439,7 +439,7 @@
// The last store may be partial. Do a truncating store. On big-endian
// machines this requires an extending load from the stack slot to ensure
// that the bits are in the right place.
- MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
+ EVT MemVT = EVT::getIntegerVT(8 * (StoredBytes - Offset));
// Load from the stack slot.
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
@@ -450,7 +450,7 @@
MemVT, ST->isVolatile(),
MinAlign(ST->getAlignment(), Offset)));
// The order of the stores doesn't matter - say it with a TokenFactor.
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
Stores.size());
}
}
@@ -458,8 +458,8 @@
!ST->getMemoryVT().isVector() &&
"Unaligned store of unknown type.");
// Get the half-size VT
- MVT NewStoredVT =
- (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
+ EVT NewStoredVT =
+ (EVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
int NumBits = NewStoredVT.getSizeInBits();
int IncrementSize = NumBits / 8;
@@ -480,7 +480,7 @@
ST->getSrcValue(), SVOffset + IncrementSize,
NewStoredVT, ST->isVolatile(), Alignment);
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2);
}
/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
@@ -490,11 +490,11 @@
int SVOffset = LD->getSrcValueOffset();
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
- MVT VT = LD->getValueType(0);
- MVT LoadedVT = LD->getMemoryVT();
+ EVT VT = LD->getValueType(0);
+ EVT LoadedVT = LD->getMemoryVT();
DebugLoc dl = LD->getDebugLoc();
if (VT.isFloatingPoint() || VT.isVector()) {
- MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
+ EVT intVT = EVT::getIntegerVT(LoadedVT.getSizeInBits());
if (TLI.isTypeLegal(intVT)) {
// Expand to a (misaligned) integer load of the same size,
// then bitconvert to floating point or vector.
@@ -510,7 +510,7 @@
} else {
// Copy the value to a (aligned) stack slot using (unaligned) integer
// loads and stores, then do a (aligned) load from the stack slot.
- MVT RegVT = TLI.getRegisterType(intVT);
+ EVT RegVT = TLI.getRegisterType(intVT);
unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
unsigned RegBytes = RegVT.getSizeInBits() / 8;
unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
@@ -540,7 +540,7 @@
}
// The last copy may be partial. Do an extending load.
- MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
+ EVT MemVT = EVT::getIntegerVT(8 * (LoadedBytes - Offset));
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
LD->getSrcValue(), SVOffset + Offset,
MemVT, LD->isVolatile(),
@@ -552,7 +552,7 @@
NULL, 0, MemVT));
// The order of the stores doesn't matter - say it with a TokenFactor.
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
Stores.size());
// Finally, perform the original load only redirected to the stack slot.
@@ -570,8 +570,8 @@
// Compute the new VT that is half the size of the old one. This is an
// integer MVT.
unsigned NumBits = LoadedVT.getSizeInBits();
- MVT NewLoadedVT;
- NewLoadedVT = MVT::getIntegerVT(NumBits/2);
+ EVT NewLoadedVT;
+ NewLoadedVT = EVT::getIntegerVT(NumBits/2);
NumBits >>= 1;
unsigned Alignment = LD->getAlignment();
@@ -607,7 +607,7 @@
SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
SDValue Ops[] = { Result, TF };
@@ -631,10 +631,10 @@
// with a "move to register" or "extload into register" instruction, then
// permute it into place, if the idx is a constant and if the idx is
// supported by the target.
- MVT VT = Tmp1.getValueType();
- MVT EltVT = VT.getVectorElementType();
- MVT IdxVT = Tmp3.getValueType();
- MVT PtrVT = TLI.getPointerTy();
+ EVT VT = Tmp1.getValueType();
+ EVT EltVT = VT.getVectorElementType();
+ EVT IdxVT = Tmp3.getValueType();
+ EVT PtrVT = TLI.getPointerTy();
SDValue StackPtr = DAG.CreateStackTemporary(VT);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
@@ -665,7 +665,7 @@
// SCALAR_TO_VECTOR requires that the type of the value being inserted
// match the element type of the vector being created, except for
// integers in which case the inserted value can be over width.
- MVT EltVT = Vec.getValueType().getVectorElementType();
+ EVT EltVT = Vec.getValueType().getVectorElementType();
if (Val.getValueType() == EltVT ||
(EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
@@ -702,27 +702,27 @@
bool isVolatile = ST->isVolatile();
DebugLoc dl = ST->getDebugLoc();
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
- if (CFP->getValueType(0) == MVT::f32 &&
- getTypeAction(MVT::i32) == Legal) {
+ if (CFP->getValueType(0) == EVT::f32 &&
+ getTypeAction(EVT::i32) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32),
- MVT::i32);
+ EVT::i32);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (CFP->getValueType(0) == MVT::f64) {
+ } else if (CFP->getValueType(0) == EVT::f64) {
// If this target supports 64-bit registers, do a single 64-bit store.
- if (getTypeAction(MVT::i64) == Legal) {
+ if (getTypeAction(EVT::i64) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- zextOrTrunc(64), MVT::i64);
+ zextOrTrunc(64), EVT::i64);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
+ } else if (getTypeAction(EVT::i32) == Legal && !ST->isVolatile()) {
// Otherwise, if the target supports 32-bit registers, use 2 32-bit
// stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it.
const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
- SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
- SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
+ SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), EVT::i32);
+ SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), EVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
@@ -732,7 +732,7 @@
Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
isVolatile, MinAlign(Alignment, 4U));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
}
}
@@ -777,7 +777,7 @@
case ISD::INTRINSIC_VOID:
case ISD::VAARG:
case ISD::STACKSAVE:
- Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
+ Action = TLI.getOperationAction(Node->getOpcode(), EVT::Other);
break;
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
@@ -787,7 +787,7 @@
break;
case ISD::FP_ROUND_INREG:
case ISD::SIGN_EXTEND_INREG: {
- MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
+ EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
break;
}
@@ -797,7 +797,7 @@
unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
Node->getOpcode() == ISD::SETCC ? 2 : 1;
unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
- MVT OpVT = Node->getOperand(CompareOperand).getValueType();
+ EVT OpVT = Node->getOperand(CompareOperand).getValueType();
ISD::CondCode CCCode =
cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
Action = TLI.getCondCodeAction(CCCode, OpVT);
@@ -882,7 +882,7 @@
case ISD::BR_CC:
case ISD::BRCOND:
// Branches tweak the chain to include LastCALLSEQ_END
- Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
+ Ops[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Ops[0],
LastCALLSEQ_END);
Ops[0] = LegalizeOp(Ops[0]);
LastCALLSEQ_END = DAG.getEntryNode();
@@ -979,7 +979,7 @@
// Merge in the last call, to ensure that this call start after the last
// call ended.
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
- Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
}
@@ -1026,7 +1026,7 @@
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Do not try to legalize the target-specific arguments (#1+), except for
// an optional flag input.
- if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
+ if (Node->getOperand(Node->getNumOperands()-1).getValueType() != EVT::Flag){
if (Tmp1 != Node->getOperand(0)) {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
@@ -1058,7 +1058,7 @@
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD) {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
Tmp3 = Result.getValue(0);
Tmp4 = Result.getValue(1);
@@ -1070,7 +1070,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
DAG, TLI);
@@ -1092,7 +1092,7 @@
// Only promote a load of vector type to another.
assert(VT.isVector() && "Cannot promote this load!");
// Change base type to a different vector type.
- MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
+ EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
@@ -1108,7 +1108,7 @@
AddLegalizedOperand(SDValue(Node, 1), Tmp4);
return Op.getResNo() ? Tmp4 : Tmp3;
} else {
- MVT SrcVT = LD->getMemoryVT();
+ EVT SrcVT = LD->getMemoryVT();
unsigned SrcWidth = SrcVT.getSizeInBits();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
@@ -1122,12 +1122,12 @@
// tells the optimizers that those bits are undefined. It would be
// nice to have an effective generic way of getting these benefits...
// Until such a way is found, don't insist on promoting i1 here.
- (SrcVT != MVT::i1 ||
- TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
+ (SrcVT != EVT::i1 ||
+ TLI.getLoadExtAction(ExtType, EVT::i1) == TargetLowering::Promote)) {
// Promote to a byte-sized load if not loading an integral number of
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
unsigned NewWidth = SrcVT.getStoreSizeInBits();
- MVT NVT = MVT::getIntegerVT(NewWidth);
+ EVT NVT = EVT::getIntegerVT(NewWidth);
SDValue Ch;
// The extra bits are guaranteed to be zero, since we stored them that
@@ -1165,8 +1165,8 @@
assert(ExtraWidth < RoundWidth);
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
"Load size not an integral number of bytes!");
- MVT RoundVT = MVT::getIntegerVT(RoundWidth);
- MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
+ EVT RoundVT = EVT::getIntegerVT(RoundWidth);
+ EVT ExtraVT = EVT::getIntegerVT(ExtraWidth);
SDValue Lo, Hi, Ch;
unsigned IncrementSize;
@@ -1189,7 +1189,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
@@ -1218,7 +1218,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
@@ -1253,7 +1253,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
DAG, TLI);
@@ -1267,7 +1267,7 @@
break;
case TargetLowering::Expand:
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
- if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
+ if (SrcVT == EVT::f32 && Node->getValueType(0) == EVT::f64) {
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
@@ -1323,7 +1323,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
- MVT VT = Tmp3.getValueType();
+ EVT VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) {
default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
@@ -1331,7 +1331,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
TLI);
@@ -1355,14 +1355,14 @@
} else {
Tmp3 = LegalizeOp(ST->getValue());
- MVT StVT = ST->getMemoryVT();
+ EVT StVT = ST->getMemoryVT();
unsigned StWidth = StVT.getSizeInBits();
if (StWidth != StVT.getStoreSizeInBits()) {
// Promote to a byte-sized store with upper bits zero if not
// storing an integral number of bytes. For example, promote
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
- MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
+ EVT NVT = EVT::getIntegerVT(StVT.getStoreSizeInBits());
Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, NVT, isVolatile, Alignment);
@@ -1376,8 +1376,8 @@
assert(ExtraWidth < RoundWidth);
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
"Store size not an integral number of bytes!");
- MVT RoundVT = MVT::getIntegerVT(RoundWidth);
- MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
+ EVT RoundVT = EVT::getIntegerVT(RoundWidth);
+ EVT ExtraVT = EVT::getIntegerVT(ExtraWidth);
SDValue Lo, Hi;
unsigned IncrementSize;
@@ -1416,7 +1416,7 @@
}
// The order of the stores doesn't matter.
- Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ Result = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
} else {
if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
Tmp2 != ST->getBasePtr())
@@ -1430,7 +1430,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
TLI);
@@ -1498,8 +1498,8 @@
// aligned object on the stack, store each element into it, then load
// the result as a vector.
// Create the stack frame object.
- MVT VT = Node->getValueType(0);
- MVT OpVT = Node->getOperand(0).getValueType();
+ EVT VT = Node->getValueType(0);
+ EVT OpVT = Node->getOperand(0).getValueType();
DebugLoc dl = Node->getDebugLoc();
SDValue FIPtr = DAG.CreateStackTemporary(VT);
int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
@@ -1524,7 +1524,7 @@
SDValue StoreChain;
if (!Stores.empty()) // Not all undef elements?
- StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ StoreChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&Stores[0], Stores.size());
else
StoreChain = DAG.getEntryNode();
@@ -1537,28 +1537,28 @@
DebugLoc dl = Node->getDebugLoc();
SDValue Tmp1 = Node->getOperand(0);
SDValue Tmp2 = Node->getOperand(1);
- assert((Tmp2.getValueType() == MVT::f32 ||
- Tmp2.getValueType() == MVT::f64) &&
+ assert((Tmp2.getValueType() == EVT::f32 ||
+ Tmp2.getValueType() == EVT::f64) &&
"Ugly special-cased code!");
// Get the sign bit of the RHS.
SDValue SignBit;
- MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
+ EVT IVT = Tmp2.getValueType() == EVT::f64 ? EVT::i64 : EVT::i32;
if (isTypeLegal(IVT)) {
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
} else {
assert(isTypeLegal(TLI.getPointerTy()) &&
- (TLI.getPointerTy() == MVT::i32 ||
- TLI.getPointerTy() == MVT::i64) &&
+ (TLI.getPointerTy() == EVT::i32 ||
+ TLI.getPointerTy() == EVT::i64) &&
"Legal type for load?!");
SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
SDValue Ch =
DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
- if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
+ if (Tmp2.getValueType() == EVT::f64 && TLI.isLittleEndian())
LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
LoadPtr, DAG.getIntPtrConstant(4));
SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
- Ch, LoadPtr, NULL, 0, MVT::i32);
+ Ch, LoadPtr, NULL, 0, EVT::i32);
}
SignBit =
DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
@@ -1577,8 +1577,8 @@
DebugLoc dl = Node->getDebugLoc();
DwarfWriter *DW = DAG.getDwarfWriter();
bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
- MVT::Other);
- bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
+ EVT::Other);
+ bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, EVT::Other);
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
@@ -1592,9 +1592,9 @@
// A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
// won't hurt anything.
if (useDEBUG_LOC) {
- return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
- DAG.getConstant(Line, MVT::i32),
- DAG.getConstant(Col, MVT::i32),
+ return DAG.getNode(ISD::DEBUG_LOC, dl, EVT::Other, Node->getOperand(0),
+ DAG.getConstant(Line, EVT::i32),
+ DAG.getConstant(Col, EVT::i32),
DAG.getSrcValue(CU.getGV()));
} else {
unsigned ID = DW->RecordSourceLine(Line, Col, CU);
@@ -1611,7 +1611,7 @@
assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
" not tell us which reg is the stack pointer!");
DebugLoc dl = Node->getDebugLoc();
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDValue Tmp1 = SDValue(Node, 0);
SDValue Tmp2 = SDValue(Node, 1);
SDValue Tmp3 = Node->getOperand(2);
@@ -1644,11 +1644,11 @@
/// condition code CC on the current target. This routine assumes LHS and rHS
/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
/// illegal condition code into AND / OR of multiple SETCC values.
-void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
+void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
SDValue &LHS, SDValue &RHS,
SDValue &CC,
DebugLoc dl) {
- MVT OpVT = LHS.getValueType();
+ EVT OpVT = LHS.getValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
switch (TLI.getCondCodeAction(CCCode, OpVT)) {
default: llvm_unreachable("Unknown condition code action!");
@@ -1690,13 +1690,13 @@
/// a load from the stack slot to DestVT, extending it if needed.
/// The resultant code need not be legal.
SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
- MVT SlotVT,
- MVT DestVT,
+ EVT SlotVT,
+ EVT DestVT,
DebugLoc dl) {
// Create the stack frame object.
unsigned SrcAlign =
TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
- getTypeForMVT());
+ getTypeForEVT());
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
@@ -1707,7 +1707,7 @@
unsigned SlotSize = SlotVT.getSizeInBits();
unsigned DestSize = DestVT.getSizeInBits();
unsigned DestAlign =
- TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
+ TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT());
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
@@ -1755,9 +1755,9 @@
unsigned NumElems = Node->getNumOperands();
SDValue Value1, Value2;
DebugLoc dl = Node->getDebugLoc();
- MVT VT = Node->getValueType(0);
- MVT OpVT = Node->getOperand(0).getValueType();
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = Node->getValueType(0);
+ EVT OpVT = Node->getOperand(0).getValueType();
+ EVT EltVT = VT.getVectorElementType();
// If the only non-undef value is the low element, turn this into a
// SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
@@ -1801,7 +1801,7 @@
CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
} else {
assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
- const Type *OpNTy = OpVT.getTypeForMVT();
+ const Type *OpNTy = OpVT.getTypeForEVT();
CV.push_back(UndefValue::get(OpNTy));
}
}
@@ -1854,8 +1854,8 @@
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- MVT ArgVT = Node->getOperand(i).getValueType();
- const Type *ArgTy = ArgVT.getTypeForMVT();
+ EVT ArgVT = Node->getOperand(i).getValueType();
+ const Type *ArgTy = ArgVT.getTypeForEVT();
Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
@@ -1865,7 +1865,7 @@
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
- const Type *RetTy = Node->getValueType(0).getTypeForMVT();
+ const Type *RetTy = Node->getValueType(0).getTypeForEVT();
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
0, CallingConv::C, false,
@@ -1888,10 +1888,10 @@
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
default: llvm_unreachable("Unexpected request for libcall!");
- case MVT::f32: LC = Call_F32; break;
- case MVT::f64: LC = Call_F64; break;
- case MVT::f80: LC = Call_F80; break;
- case MVT::ppcf128: LC = Call_PPCF128; break;
+ case EVT::f32: LC = Call_F32; break;
+ case EVT::f64: LC = Call_F64; break;
+ case EVT::f80: LC = Call_F80; break;
+ case EVT::ppcf128: LC = Call_PPCF128; break;
}
return ExpandLibCall(LC, Node, false);
}
@@ -1904,10 +1904,10 @@
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
default: llvm_unreachable("Unexpected request for libcall!");
- case MVT::i16: LC = Call_I16; break;
- case MVT::i32: LC = Call_I32; break;
- case MVT::i64: LC = Call_I64; break;
- case MVT::i128: LC = Call_I128; break;
+ case EVT::i16: LC = Call_I16; break;
+ case EVT::i32: LC = Call_I32; break;
+ case EVT::i64: LC = Call_I64; break;
+ case EVT::i128: LC = Call_I128; break;
}
return ExpandLibCall(LC, Node, isSigned);
}
@@ -1918,13 +1918,13 @@
/// legal for the target.
SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue Op0,
- MVT DestVT,
+ EVT DestVT,
DebugLoc dl) {
- if (Op0.getValueType() == MVT::i32) {
+ if (Op0.getValueType() == EVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
// Get the stack frame index of a 8 byte buffer.
- SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
+ SDValue StackSlot = DAG.CreateStackTemporary(EVT::f64);
// word offset constant for Hi/Lo address computation
SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
@@ -1939,8 +1939,8 @@
SDValue Op0Mapped;
if (isSigned) {
// constant used to invert sign bit (signed to unsigned mapping)
- SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
- Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
+ SDValue SignBit = DAG.getConstant(0x80000000u, EVT::i32);
+ Op0Mapped = DAG.getNode(ISD::XOR, dl, EVT::i32, Op0, SignBit);
} else {
Op0Mapped = Op0;
}
@@ -1948,28 +1948,28 @@
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
Op0Mapped, Lo, NULL, 0);
// initial hi portion of constructed double
- SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
+ SDValue InitialHi = DAG.getConstant(0x43300000u, EVT::i32);
// store the hi of the constructed double - biased exponent
SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
// load the constructed double
- SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
+ SDValue Load = DAG.getLoad(EVT::f64, dl, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result
SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL) :
BitsToDouble(0x4330000000000000ULL),
- MVT::f64);
+ EVT::f64);
// subtract the bias
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Load, Bias);
// final result
SDValue Result;
// handle final rounding
- if (DestVT == MVT::f64) {
+ if (DestVT == EVT::f64) {
// do nothing
Result = Sub;
- } else if (DestVT.bitsLT(MVT::f64)) {
+ } else if (DestVT.bitsLT(EVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
- } else if (DestVT.bitsGT(MVT::f64)) {
+ } else if (DestVT.bitsGT(EVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
return Result;
@@ -1990,10 +1990,10 @@
uint64_t FF;
switch (Op0.getValueType().getSimpleVT()) {
default: llvm_unreachable("Unsupported integer type!");
- case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
- case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
- case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
- case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
+ case EVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
+ case EVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
+ case EVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
+ case EVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
}
if (TLI.isLittleEndian()) FF <<= 32;
Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
@@ -2003,8 +2003,8 @@
CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
- if (DestVT == MVT::f32)
- FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
+ if (DestVT == EVT::f32)
+ FudgeInReg = DAG.getLoad(EVT::f32, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
else {
@@ -2012,7 +2012,7 @@
LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
- MVT::f32, false, Alignment));
+ EVT::f32, false, Alignment));
}
return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2024,17 +2024,17 @@
/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
/// operation that takes a larger input.
SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
- MVT DestVT,
+ EVT DestVT,
bool isSigned,
DebugLoc dl) {
// First step, figure out the appropriate *INT_TO_FP operation to use.
- MVT NewInTy = LegalOp.getValueType();
+ EVT NewInTy = LegalOp.getValueType();
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
while (1) {
- NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
+ NewInTy = (EVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
assert(NewInTy.isInteger() && "Ran out of possibilities!");
// If the target supports SINT_TO_FP of this type, use it.
@@ -2066,17 +2066,17 @@
/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
/// operation that returns a larger result.
SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
- MVT DestVT,
+ EVT DestVT,
bool isSigned,
DebugLoc dl) {
// First step, figure out the appropriate FP_TO*INT operation to use.
- MVT NewOutTy = DestVT;
+ EVT NewOutTy = DestVT;
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
while (1) {
- NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
+ NewOutTy = (EVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
assert(NewOutTy.isInteger() && "Ran out of possibilities!");
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
@@ -2104,16 +2104,16 @@
/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
///
SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
- MVT VT = Op.getValueType();
- MVT SHVT = TLI.getShiftAmountTy();
+ EVT VT = Op.getValueType();
+ EVT SHVT = TLI.getShiftAmountTy();
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
switch (VT.getSimpleVT()) {
default: llvm_unreachable("Unhandled Expand type in BSWAP!");
- case MVT::i16:
+ case EVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
- case MVT::i32:
+ case EVT::i32:
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
@@ -2123,7 +2123,7 @@
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
- case MVT::i64:
+ case EVT::i64:
Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
@@ -2160,8 +2160,8 @@
0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
};
- MVT VT = Op.getValueType();
- MVT ShVT = TLI.getShiftAmountTy();
+ EVT VT = Op.getValueType();
+ EVT ShVT = TLI.getShiftAmountTy();
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
@@ -2187,8 +2187,8 @@
// return popcount(~x);
//
// but see also: http://www.hackersdelight.org/HDcode/nlz.cc
- MVT VT = Op.getValueType();
- MVT ShVT = TLI.getShiftAmountTy();
+ EVT VT = Op.getValueType();
+ EVT ShVT = TLI.getShiftAmountTy();
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
@@ -2203,7 +2203,7 @@
// unless the target has ctlz but not ctpop, in which case we use:
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNOT(dl, Op, VT),
DAG.getNode(ISD::SUB, dl, VT, Op,
@@ -2261,7 +2261,7 @@
Results.push_back(Node->getOperand(i));
break;
case ISD::UNDEF: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
if (VT.isInteger())
Results.push_back(DAG.getConstant(0, VT));
else if (VT.isFloatingPoint())
@@ -2297,7 +2297,7 @@
case ISD::SIGN_EXTEND_INREG: {
// NOTE: we could fall back on load/store here too for targets without
// SAR. However, it is doubtful that any exist.
- MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
+ EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
ExtraVT.getSizeInBits();
SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
@@ -2314,7 +2314,7 @@
// NOTE: there is a choice here between constantly creating new stack
// slots and always reusing the same one. We currently always create
// new ones, as reuse may inhibit scheduling.
- MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
+ EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
Node->getValueType(0), dl);
Results.push_back(Tmp1);
@@ -2328,8 +2328,8 @@
break;
case ISD::FP_TO_UINT: {
SDValue True, False;
- MVT VT = Node->getOperand(0).getValueType();
- MVT NVT = Node->getValueType(0);
+ EVT VT = Node->getOperand(0).getValueType();
+ EVT NVT = Node->getValueType(0);
const uint64_t zero[] = {0, 0};
APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
APInt x = APInt::getSignBit(NVT.getSizeInBits());
@@ -2350,14 +2350,14 @@
}
case ISD::VAARG: {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(TLI.getTargetData()->
- getTypeAllocSize(VT.getTypeForMVT()),
+ getTypeAllocSize(VT.getTypeForEVT()),
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
@@ -2405,8 +2405,8 @@
SmallVector<int, 8> Mask;
cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
- MVT VT = Node->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = Node->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
unsigned NumElems = VT.getVectorNumElements();
SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i != NumElems; ++i) {
@@ -2429,7 +2429,7 @@
break;
}
case ISD::EXTRACT_ELEMENT: {
- MVT OpTy = Node->getOperand(0).getValueType();
+ EVT OpTy = Node->getOperand(0).getValueType();
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
// 1 -> Hi
Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
@@ -2478,7 +2478,7 @@
break;
case ISD::FABS: {
// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Tmp1 = Node->getOperand(0);
Tmp2 = DAG.getConstantFP(0.0, VT);
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
@@ -2593,7 +2593,7 @@
break;
}
case ISD::SUB: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
"Don't know how to expand this subtraction!");
@@ -2605,7 +2605,7 @@
}
case ISD::UREM:
case ISD::SREM: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
bool isSigned = Node->getOpcode() == ISD::SREM;
unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
@@ -2633,7 +2633,7 @@
case ISD::SDIV: {
bool isSigned = Node->getOpcode() == ISD::SDIV;
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
@@ -2651,7 +2651,7 @@
case ISD::MULHS: {
unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
ISD::SMUL_LOHI;
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
"If this wasn't legal, it shouldn't have been created!");
@@ -2661,7 +2661,7 @@
break;
}
case ISD::MUL: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
// See if multiply or divide can be lowered using two-result operations.
// We just need the low half of the multiply; try both the signed
@@ -2700,7 +2700,7 @@
ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
LHS, RHS);
Results.push_back(Sum);
- MVT OType = Node->getValueType(1);
+ EVT OType = Node->getValueType(1);
SDValue Zero = DAG.getConstant(0, LHS.getValueType());
@@ -2741,7 +2741,7 @@
}
case ISD::UMULO:
case ISD::SMULO: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDValue LHS = Node->getOperand(0);
SDValue RHS = Node->getOperand(1);
SDValue BottomHalf;
@@ -2757,8 +2757,8 @@
BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
RHS);
TopHalf = BottomHalf.getValue(1);
- } else if (TLI.isTypeLegal(MVT::getIntegerVT(VT.getSizeInBits() * 2))) {
- MVT WideVT = MVT::getIntegerVT(VT.getSizeInBits() * 2);
+ } else if (TLI.isTypeLegal(EVT::getIntegerVT(VT.getSizeInBits() * 2))) {
+ EVT WideVT = EVT::getIntegerVT(VT.getSizeInBits() * 2);
LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
@@ -2787,7 +2787,7 @@
break;
}
case ISD::BUILD_PAIR: {
- MVT PairTy = Node->getValueType(0);
+ EVT PairTy = Node->getValueType(0);
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
@@ -2816,14 +2816,14 @@
SDValue Table = Node->getOperand(1);
SDValue Index = Node->getOperand(2);
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
MachineFunction &MF = DAG.getMachineFunction();
unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
Index= DAG.getNode(ISD::MUL, dl, PTy,
Index, DAG.getConstant(EntrySize, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
- MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
+ EVT MemVT = EVT::getIntegerVT(EntrySize * 8);
SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
PseudoSourceValue::getJumpTable(), 0, MemVT);
Addr = LD;
@@ -2834,7 +2834,7 @@
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
TLI.getPICJumpTableRelocBase(Table, DAG));
}
- Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
+ Tmp1 = DAG.getNode(ISD::BRIND, dl, EVT::Other, LD.getValue(1), Addr);
Results.push_back(Tmp1);
break;
}
@@ -2844,12 +2844,12 @@
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
if (Tmp2.getOpcode() == ISD::SETCC) {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other,
Tmp1, Tmp2.getOperand(2),
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node->getOperand(2));
} else {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
Node->getOperand(2));
@@ -2870,7 +2870,7 @@
// Otherwise, SETCC for the given comparison type must be completely
// illegal; expand it into a SELECT_CC.
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
Results.push_back(Tmp1);
@@ -2929,13 +2929,13 @@
}
void SelectionDAGLegalize::PromoteNode(SDNode *Node,
SmallVectorImpl<SDValue> &Results) {
- MVT OVT = Node->getValueType(0);
+ EVT OVT = Node->getValueType(0);
if (Node->getOpcode() == ISD::UINT_TO_FP ||
Node->getOpcode() == ISD::SINT_TO_FP ||
Node->getOpcode() == ISD::SETCC) {
OVT = Node->getOperand(0).getValueType();
}
- MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+ EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
DebugLoc dl = Node->getDebugLoc();
SDValue Tmp1, Tmp2, Tmp3;
switch (Node->getOpcode()) {
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Mon Aug 10 17:56:29 2009
@@ -25,16 +25,16 @@
using namespace llvm;
/// GetFPLibCall - Return the right libcall for the given floating point type.
-static RTLIB::Libcall GetFPLibCall(MVT VT,
+static RTLIB::Libcall GetFPLibCall(EVT VT,
RTLIB::Libcall Call_F32,
RTLIB::Libcall Call_F64,
RTLIB::Libcall Call_F80,
RTLIB::Libcall Call_PPCF128) {
return
- VT == MVT::f32 ? Call_F32 :
- VT == MVT::f64 ? Call_F64 :
- VT == MVT::f80 ? Call_F80 :
- VT == MVT::ppcf128 ? Call_PPCF128 :
+ VT == EVT::f32 ? Call_F32 :
+ VT == EVT::f64 ? Call_F64 :
+ VT == EVT::f80 ? Call_F80 :
+ VT == EVT::ppcf128 ? Call_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
}
@@ -126,7 +126,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned Size = NVT.getSizeInBits();
// Mask = ~(1 << (Size-1))
@@ -137,7 +137,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -149,7 +149,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::CEIL_F32,
@@ -164,8 +164,8 @@
SDValue RHS = BitConvertToInteger(N->getOperand(1));
DebugLoc dl = N->getDebugLoc();
- MVT LVT = LHS.getValueType();
- MVT RVT = RHS.getValueType();
+ EVT LVT = LHS.getValueType();
+ EVT RVT = RHS.getValueType();
unsigned LSize = LVT.getSizeInBits();
unsigned RSize = RVT.getSizeInBits();
@@ -200,7 +200,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::COS_F32,
@@ -211,7 +211,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -223,7 +223,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::EXP_F32,
@@ -234,7 +234,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::EXP2_F32,
@@ -245,7 +245,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::FLOOR_F32,
@@ -256,7 +256,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::LOG_F32,
@@ -267,7 +267,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::LOG2_F32,
@@ -278,7 +278,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::LOG10_F32,
@@ -289,7 +289,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -301,7 +301,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::NEARBYINT_F32,
@@ -312,7 +312,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
// Expand Y = FNEG(X) -> Y = SUB -0.0, X
SDValue Ops[2] = { DAG.getConstantFP(-0.0, N->getValueType(0)),
GetSoftenedFloat(N->getOperand(0)) };
@@ -325,7 +325,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
@@ -333,7 +333,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
@@ -341,7 +341,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -353,9 +353,9 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
- assert(N->getOperand(1).getValueType() == MVT::i32 &&
+ assert(N->getOperand(1).getValueType() == EVT::i32 &&
"Unsupported power type!");
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::POWI_F32,
@@ -366,7 +366,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -378,7 +378,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::RINT_F32,
@@ -389,7 +389,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SIN_F32,
@@ -400,7 +400,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SQRT_F32,
@@ -411,7 +411,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -423,7 +423,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::TRUNC_F32,
@@ -435,8 +435,8 @@
SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
LoadSDNode *L = cast<LoadSDNode>(N);
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
SDValue NewL;
@@ -486,8 +486,8 @@
SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
SDValue Chain = N->getOperand(0); // Get the chain.
SDValue Ptr = N->getOperand(1); // Get the pointer.
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
SDValue NewVAARG;
@@ -501,18 +501,18 @@
SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
- MVT SVT = N->getOperand(0).getValueType();
- MVT RVT = N->getValueType(0);
- MVT NVT = MVT();
+ EVT SVT = N->getOperand(0).getValueType();
+ EVT RVT = N->getValueType(0);
+ EVT NVT = EVT();
DebugLoc dl = N->getDebugLoc();
// If the input is not legal, eg: i1 -> fp, then it needs to be promoted to
// a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
// match. Look for an appropriate libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
- t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
- NVT = (MVT::SimpleValueType)t;
+ for (unsigned t = EVT::FIRST_INTEGER_VALUETYPE;
+ t <= EVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
+ NVT = (EVT::SimpleValueType)t;
// The source needs to big enough to hold the operand.
if (NVT.bitsGE(SVT))
LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
@@ -574,70 +574,70 @@
ISD::CondCode &CCCode, DebugLoc dl) {
SDValue LHSInt = GetSoftenedFloat(NewLHS);
SDValue RHSInt = GetSoftenedFloat(NewRHS);
- MVT VT = NewLHS.getValueType();
+ EVT VT = NewLHS.getValueType();
- assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
+ assert((VT == EVT::f32 || VT == EVT::f64) && "Unsupported setcc type!");
// Expand into one or more soft-fp libcall(s).
RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
switch (CCCode) {
case ISD::SETEQ:
case ISD::SETOEQ:
- LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
case ISD::SETNE:
case ISD::SETUNE:
- LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
break;
case ISD::SETGE:
case ISD::SETOGE:
- LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETLT:
case ISD::SETOLT:
- LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETLE:
case ISD::SETOLE:
- LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETGT:
case ISD::SETOGT:
- LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUO:
- LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
break;
case ISD::SETO:
- LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
break;
default:
- LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
switch (CCCode) {
case ISD::SETONE:
// SETONE = SETOLT | SETOGT
- LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
// Fallthrough
case ISD::SETUGT:
- LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUGE:
- LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETULT:
- LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETULE:
- LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETUEQ:
- LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
default: assert(false && "Do not know how to soften this setcc!");
}
}
- MVT RetVT = MVT::i32; // FIXME: is this the correct return type?
+ EVT RetVT = EVT::i32; // FIXME: is this the correct return type?
SDValue Ops[2] = { LHSInt, RHSInt };
NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
NewRHS = DAG.getConstant(0, RetVT);
@@ -659,8 +659,8 @@
}
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
- MVT SVT = N->getOperand(0).getValueType();
- MVT RVT = N->getValueType(0);
+ EVT SVT = N->getOperand(0).getValueType();
+ EVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
@@ -688,7 +688,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
SDValue Op = GetSoftenedFloat(N->getOperand(0));
@@ -696,7 +696,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
SDValue Op = GetSoftenedFloat(N->getOperand(0));
@@ -829,7 +829,7 @@
void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(NVT.getSizeInBits() == integerPartWidth &&
"Do not know how to expand this float constant!");
APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
@@ -841,7 +841,7 @@
void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == MVT::ppcf128 &&
+ assert(N->getValueType(0) == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
DebugLoc dl = N->getDebugLoc();
SDValue Tmp;
@@ -981,7 +981,7 @@
void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
Hi = DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), NVT, N->getOperand(0));
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
}
@@ -1066,7 +1066,7 @@
SDValue Ptr = LD->getBasePtr();
DebugLoc dl = N->getDebugLoc();
- MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
assert(NVT.isByteSized() && "Expanded type not byte sized!");
assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
@@ -1088,31 +1088,31 @@
void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ assert(N->getValueType(0) == EVT::ppcf128 && "Unsupported XINT_TO_FP!");
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Src = N->getOperand(0);
- MVT SrcVT = Src.getValueType();
+ EVT SrcVT = Src.getValueType();
bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
DebugLoc dl = N->getDebugLoc();
// First do an SINT_TO_FP, whether the original was signed or unsigned.
// When promoting partial word types to i32 we must honor the signedness,
// though.
- if (SrcVT.bitsLE(MVT::i32)) {
+ if (SrcVT.bitsLE(EVT::i32)) {
// The integer can be represented exactly in an f64.
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- MVT::i32, Src);
+ EVT::i32, Src);
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
} else {
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (SrcVT.bitsLE(MVT::i64)) {
+ if (SrcVT.bitsLE(EVT::i64)) {
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- MVT::i64, Src);
+ EVT::i64, Src);
LC = RTLIB::SINTTOFP_I64_PPCF128;
- } else if (SrcVT.bitsLE(MVT::i128)) {
- Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
+ } else if (SrcVT.bitsLE(EVT::i128)) {
+ Src = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i128, Src);
LC = RTLIB::SINTTOFP_I128_PPCF128;
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
@@ -1137,20 +1137,20 @@
switch (SrcVT.getSimpleVT()) {
default:
assert(false && "Unsupported UINT_TO_FP!");
- case MVT::i32:
+ case EVT::i32:
Parts = TwoE32;
break;
- case MVT::i64:
+ case EVT::i64:
Parts = TwoE64;
break;
- case MVT::i128:
+ case EVT::i128:
Parts = TwoE128;
break;
}
Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
- MVT::ppcf128));
+ EVT::ppcf128));
Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
Lo, Hi, DAG.getCondCode(ISD::SETLT));
GetPairElements(Lo, Lo, Hi);
@@ -1222,8 +1222,8 @@
GetExpandedFloat(NewLHS, LHSLo, LHSHi);
GetExpandedFloat(NewRHS, RHSLo, RHSHi);
- MVT VT = NewLHS.getValueType();
- assert(VT == MVT::ppcf128 && "Unsupported setcc type!");
+ EVT VT = NewLHS.getValueType();
+ assert(VT == EVT::ppcf128 && "Unsupported setcc type!");
// FIXME: This generated code sucks. We want to generate
// FCMPU crN, hi1, hi2
@@ -1264,7 +1264,7 @@
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
- assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
+ assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
SDValue Lo, Hi;
GetExpandedFloat(N->getOperand(0), Lo, Hi);
@@ -1274,19 +1274,19 @@
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == MVT::i32) {
- assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
+ if (RVT == EVT::i32) {
+ assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
- SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
- N->getOperand(0), DAG.getValueType(MVT::f64));
- Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
+ SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, EVT::ppcf128,
+ N->getOperand(0), DAG.getValueType(EVT::f64));
+ Res = DAG.getNode(ISD::FP_ROUND, dl, EVT::f64, Res,
DAG.getIntPtrConstant(1));
- return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
+ return DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Res);
}
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
@@ -1295,29 +1295,29 @@
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == MVT::i32) {
- assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
+ if (RVT == EVT::i32) {
+ assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
APFloat APF = APFloat(APInt(128, 2, TwoE31));
- SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
+ SDValue Tmp = DAG.getConstantFP(APF, EVT::ppcf128);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks.
- return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp,
- DAG.getNode(ISD::ADD, dl, MVT::i32,
- DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
+ return DAG.getNode(ISD::SELECT_CC, dl, EVT::i32, N->getOperand(0), Tmp,
+ DAG.getNode(ISD::ADD, dl, EVT::i32,
+ DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32,
DAG.getNode(ISD::FSUB, dl,
- MVT::ppcf128,
+ EVT::ppcf128,
N->getOperand(0),
Tmp)),
- DAG.getConstant(0x80000000, MVT::i32)),
+ DAG.getConstant(0x80000000, EVT::i32)),
DAG.getNode(ISD::FP_TO_SINT, dl,
- MVT::i32, N->getOperand(0)),
+ EVT::i32, N->getOperand(0)),
DAG.getCondCode(ISD::SETGE));
}
@@ -1372,7 +1372,7 @@
SDValue Chain = ST->getChain();
SDValue Ptr = ST->getBasePtr();
- MVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType());
+ EVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType());
assert(NVT.isByteSized() && "Expanded type not byte sized!");
assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Aug 10 17:56:29 2009
@@ -162,10 +162,10 @@
SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
- MVT NInVT = TLI.getTypeToTransformTo(InVT);
- MVT OutVT = N->getValueType(0);
- MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
+ EVT InVT = InOp.getValueType();
+ EVT NInVT = TLI.getTypeToTransformTo(InVT);
+ EVT OutVT = N->getValueType(0);
+ EVT NOutVT = TLI.getTypeToTransformTo(OutVT);
DebugLoc dl = N->getDebugLoc();
switch (getTypeAction(InVT)) {
@@ -202,7 +202,7 @@
std::swap(Lo, Hi);
InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
- MVT::getIntegerVT(NOutVT.getSizeInBits()),
+ EVT::getIntegerVT(NOutVT.getSizeInBits()),
JoinIntegers(Lo, Hi));
return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
}
@@ -218,8 +218,8 @@
SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
SDValue Op = GetPromotedInteger(N->getOperand(0));
- MVT OVT = N->getValueType(0);
- MVT NVT = Op.getValueType();
+ EVT OVT = N->getValueType(0);
+ EVT NVT = Op.getValueType();
DebugLoc dl = N->getDebugLoc();
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
@@ -236,7 +236,7 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// FIXME there is no actual debug info here
DebugLoc dl = N->getDebugLoc();
// Zero extend things like i1, sign extend everything else. It shouldn't
@@ -254,7 +254,7 @@
CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
"can only promote integers");
- MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
N->getOperand(1), N->getOperand(2),
N->getOperand(3), N->getOperand(4), CvtCode);
@@ -264,8 +264,8 @@
// Zero extend to the promoted type and do the count there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
DebugLoc dl = N->getDebugLoc();
- MVT OVT = N->getValueType(0);
- MVT NVT = Op.getValueType();
+ EVT OVT = N->getValueType(0);
+ EVT NVT = Op.getValueType();
Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
// Subtract off the extra leading bits in the bigger type.
return DAG.getNode(ISD::SUB, dl, NVT, Op,
@@ -281,8 +281,8 @@
SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
SDValue Op = GetPromotedInteger(N->getOperand(0));
- MVT OVT = N->getValueType(0);
- MVT NVT = Op.getValueType();
+ EVT OVT = N->getValueType(0);
+ EVT NVT = Op.getValueType();
DebugLoc dl = N->getDebugLoc();
// The count is the same in the promoted type except if the original
// value was zero. This can be handled by setting the bit just off
@@ -295,13 +295,13 @@
SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
N->getOperand(1));
}
SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned NewOpc = N->getOpcode();
DebugLoc dl = N->getDebugLoc();
@@ -325,7 +325,7 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
@@ -352,7 +352,7 @@
SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
ISD::LoadExtType ExtType =
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
DebugLoc dl = N->getDebugLoc();
@@ -370,8 +370,8 @@
/// Promote the overflow flag of an overflowing arithmetic node.
SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
// Simply change the return type of the boolean result.
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
- MVT ValueVTs[] = { N->getValueType(0), NVT };
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
+ EVT ValueVTs[] = { N->getValueType(0), NVT };
SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
DAG.getVTList(ValueVTs, 2), Ops, 2);
@@ -391,8 +391,8 @@
// sign extension of its truncation to the original type.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
- MVT OVT = N->getOperand(0).getValueType();
- MVT NVT = LHS.getValueType();
+ EVT OVT = N->getOperand(0).getValueType();
+ EVT NVT = LHS.getValueType();
DebugLoc dl = N->getDebugLoc();
// Do the arithmetic in the larger type.
@@ -436,7 +436,7 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
- MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
+ EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
DebugLoc dl = N->getDebugLoc();
@@ -445,7 +445,7 @@
N->getOperand(1), N->getOperand(2));
// Convert to the expected type.
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
}
@@ -481,14 +481,14 @@
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
// The input value must be properly zero extended.
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Res = ZExtPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
}
SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Res;
switch (getTypeAction(N->getOperand(0).getValueType())) {
@@ -514,8 +514,8 @@
// zero extension of its truncation to the original type.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
- MVT OVT = N->getOperand(0).getValueType();
- MVT NVT = LHS.getValueType();
+ EVT OVT = N->getOperand(0).getValueType();
+ EVT NVT = LHS.getValueType();
DebugLoc dl = N->getDebugLoc();
// Do the arithmetic in the larger type.
@@ -549,10 +549,10 @@
SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
SDValue Chain = N->getOperand(0); // Get the chain.
SDValue Ptr = N->getOperand(1); // Get the pointer.
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
- MVT RegVT = TLI.getRegisterType(VT);
+ EVT RegVT = TLI.getRegisterType(VT);
unsigned NumRegs = TLI.getNumRegisters(VT);
// The argument is passed as NumRegs registers of type RegVT.
@@ -567,7 +567,7 @@
std::reverse(Parts.begin(), Parts.end());
// Assemble the parts in the promoted type.
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
for (unsigned i = 1; i < NumRegs; ++i) {
SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
@@ -718,7 +718,7 @@
assert(OpNo == 1 && "only know how to promote condition");
// Promote all the way up to the canonical SetCC type.
- MVT SVT = TLI.getSetCCResultType(MVT::Other);
+ EVT SVT = TLI.getSetCCResultType(EVT::Other);
SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
@@ -728,7 +728,7 @@
SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
// Since the result type is legal, the operands must promote to it.
- MVT OVT = N->getOperand(0).getValueType();
+ EVT OVT = N->getOperand(0).getValueType();
SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
SDValue Hi = GetPromotedInteger(N->getOperand(1));
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
@@ -743,7 +743,7 @@
// The vector type is legal but the element type is not. This implies
// that the vector is a power-of-two in length and that the element
// type does not have a strange size (eg: it is not i1).
- MVT VecVT = N->getValueType(0);
+ EVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
assert(!(NumElts & 1) && "Legal vector of one illegal element?");
@@ -802,7 +802,7 @@
NewOps[0] = N->getOperand(0);
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
SDValue Flag = GetPromotedInteger(N->getOperand(i));
- NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
+ NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, EVT::i1);
}
return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
array_lengthof(NewOps));
@@ -819,7 +819,7 @@
assert(OpNo == 0 && "Only know how to promote condition");
// Promote all the way up to the canonical SetCC type.
- MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
+ EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
@@ -990,10 +990,10 @@
SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH);
- MVT NVT = InL.getValueType();
+ EVT NVT = InL.getValueType();
unsigned VTBits = N->getValueType(0).getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
- MVT ShTy = N->getOperand(1).getValueType();
+ EVT ShTy = N->getOperand(1).getValueType();
if (N->getOpcode() == ISD::SHL) {
if (Amt > VTBits) {
@@ -1009,7 +1009,7 @@
TLI.isOperationLegalOrCustom(ISD::ADDC,
TLI.getTypeToExpandTo(NVT))) {
// Emit this X << 1 as X+X.
- SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
SDValue LoOps[2] = { InL, InL };
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
@@ -1077,8 +1077,8 @@
bool DAGTypeLegalizer::
ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue Amt = N->getOperand(1);
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- MVT ShTy = Amt.getValueType();
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT ShTy = Amt.getValueType();
unsigned ShBits = ShTy.getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
assert(isPowerOf2_32(NVTBits) &&
@@ -1155,8 +1155,8 @@
bool DAGTypeLegalizer::
ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue Amt = N->getOperand(1);
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- MVT ShTy = Amt.getValueType();
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT ShTy = Amt.getValueType();
unsigned NVTBits = NVT.getSizeInBits();
assert(isPowerOf2_32(NVTBits) &&
"Expanded integer type size not a power of two!");
@@ -1230,14 +1230,14 @@
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- MVT NVT = LHSL.getValueType();
+ EVT NVT = LHSL.getValueType();
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
// Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
// them. TODO: Teach operation legalization how to expand unsupported
// ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
- // a carry of type MVT::Flag, but there doesn't seem to be any way to
+ // a carry of type EVT::Flag, but there doesn't seem to be any way to
// generate a value of this type in the expanded code sequence.
bool hasCarry =
TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
@@ -1245,7 +1245,7 @@
TLI.getTypeToExpandTo(NVT));
if (hasCarry) {
- SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
@@ -1290,7 +1290,7 @@
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
@@ -1316,7 +1316,7 @@
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
SDValue HiOps[3] = { LHSH, RHSH };
@@ -1331,7 +1331,7 @@
void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
@@ -1355,14 +1355,14 @@
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT NVT = Lo.getValueType();
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
unsigned NVTBits = NVT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
if (NVTBits < EVTBits) {
Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
- DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
+ DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits)));
} else {
Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part replicates the sign bit of Lo, make it explicit.
@@ -1375,14 +1375,14 @@
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT NVT = Lo.getValueType();
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
unsigned NVTBits = NVT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
if (NVTBits < EVTBits) {
Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
- DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
+ DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits)));
} else {
Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part must be zero, make it explicit.
@@ -1400,7 +1400,7 @@
void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned NBitWidth = NVT.getSizeInBits();
const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
@@ -1412,7 +1412,7 @@
DebugLoc dl = N->getDebugLoc();
// ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
+ EVT NVT = Lo.getValueType();
SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
DAG.getConstant(0, NVT), ISD::SETNE);
@@ -1431,7 +1431,7 @@
DebugLoc dl = N->getDebugLoc();
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
+ EVT NVT = Lo.getValueType();
Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
Hi = DAG.getConstant(0, NVT);
@@ -1442,7 +1442,7 @@
DebugLoc dl = N->getDebugLoc();
// cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
+ EVT NVT = Lo.getValueType();
SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
DAG.getConstant(0, NVT), ISD::SETNE);
@@ -1459,7 +1459,7 @@
void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
@@ -1469,7 +1469,7 @@
void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
@@ -1485,8 +1485,8 @@
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
ISD::LoadExtType ExtType = N->getExtensionType();
@@ -1498,7 +1498,7 @@
assert(NVT.isByteSized() && "Expanded type not byte sized!");
if (N->getMemoryVT().bitsLE(NVT)) {
- MVT EVT = N->getMemoryVT();
+ EVT EVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
EVT, isVolatile, Alignment);
@@ -1527,7 +1527,7 @@
unsigned ExcessBits =
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
- MVT NEVT = MVT::getIntegerVT(ExcessBits);
+ EVT NEVT = EVT::getIntegerVT(ExcessBits);
// Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits()/8;
@@ -1539,19 +1539,19 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
} else {
// Big-endian - high bits are at low addresses. Favor aligned loads at
// the cost of some bit-fiddling.
- MVT EVT = N->getMemoryVT();
+ EVT EVT = N->getMemoryVT();
unsigned EBytes = EVT.getStoreSizeInBits()/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
// Load both the high bits and maybe some of the low bits.
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
- MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
+ EVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
isVolatile, Alignment);
// Increment the pointer to the other half.
@@ -1560,12 +1560,12 @@
// Load the rest of the low bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
SVOffset+IncrementSize,
- MVT::getIntegerVT(ExcessBits),
+ EVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
if (ExcessBits < NVT.getSizeInBits()) {
@@ -1599,8 +1599,8 @@
void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
@@ -1673,13 +1673,13 @@
// If nothing else, we can make a libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::MUL_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::MUL_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::MUL_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::MUL_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
@@ -1689,17 +1689,17 @@
void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SDIV_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SDIV_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SDIV_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
@@ -1709,7 +1709,7 @@
void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// If we can emit an efficient shift operation, do so now. Check to see if
@@ -1735,7 +1735,7 @@
// Next check to see if the target supports this SHL_PARTS operation or if it
// will custom expand it.
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
@@ -1744,7 +1744,7 @@
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
- MVT VT = LHSL.getValueType();
+ EVT VT = LHSL.getValueType();
Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
Hi = Lo.getValue(1);
return;
@@ -1755,34 +1755,34 @@
bool isSigned;
if (N->getOpcode() == ISD::SHL) {
isSigned = false; /*sign irrelevant*/
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SHL_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SHL_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SHL_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SHL_I128;
} else if (N->getOpcode() == ISD::SRL) {
isSigned = false;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SRL_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SRL_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SRL_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SRL_I128;
} else {
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
isSigned = true;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SRA_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SRA_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SRA_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SRA_I128;
}
@@ -1798,7 +1798,7 @@
void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
@@ -1821,7 +1821,7 @@
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
- DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
+ DAG.getValueType(EVT::getIntegerVT(ExcessBits)));
}
}
@@ -1829,7 +1829,7 @@
ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (EVT.bitsLE(Lo.getValueType())) {
// sext_inreg the low part if needed.
@@ -1847,23 +1847,23 @@
unsigned ExcessBits =
EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
- DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
+ DAG.getValueType(EVT::getIntegerVT(ExcessBits)));
}
}
void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SREM_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SREM_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SREM_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
@@ -1873,7 +1873,7 @@
void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
Hi = DAG.getNode(ISD::SRL, dl,
@@ -1884,17 +1884,17 @@
void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::UDIV_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::UDIV_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::UDIV_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::UDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
@@ -1904,17 +1904,17 @@
void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::UREM_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::UREM_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::UREM_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::UREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
@@ -1924,7 +1924,7 @@
void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
@@ -1943,7 +1943,7 @@
SplitInteger(Res, Lo, Hi);
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
- Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
+ Hi = DAG.getZeroExtendInReg(Hi, dl, EVT::getIntegerVT(ExcessBits));
}
}
@@ -2016,7 +2016,7 @@
GetExpandedInteger(NewLHS, LHSLo, LHSHi);
GetExpandedInteger(NewRHS, RHSLo, RHSHi);
- MVT VT = NewLHS.getValueType();
+ EVT VT = NewLHS.getValueType();
if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
if (RHSLo == RHSHi) {
@@ -2174,7 +2174,7 @@
SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
SDValue Op = N->getOperand(0);
- MVT DstVT = N->getValueType(0);
+ EVT DstVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this SINT_TO_FP!");
@@ -2188,8 +2188,8 @@
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
assert(OpNo == 1 && "Can only expand the stored value so far");
- MVT VT = N->getOperand(1).getValueType();
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getOperand(1).getValueType();
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
@@ -2213,7 +2213,7 @@
unsigned ExcessBits =
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
- MVT NEVT = MVT::getIntegerVT(ExcessBits);
+ EVT NEVT = EVT::getIntegerVT(ExcessBits);
// Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits()/8;
@@ -2222,17 +2222,17 @@
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
SVOffset+IncrementSize, NEVT,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
} else {
// Big-endian - high bits are at low addresses. Favor aligned stores at
// the cost of some bit-fiddling.
GetExpandedInteger(N->getValue(), Lo, Hi);
- MVT EVT = N->getMemoryVT();
- unsigned EBytes = EVT.getStoreSizeInBits()/8;
+ EVT ExtVT = N->getMemoryVT();
+ unsigned EBytes = ExtVT.getStoreSizeInBits()/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
- MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
+ EVT HiVT = EVT::getIntegerVT(ExtVT.getSizeInBits() - ExcessBits);
if (ExcessBits < NVT.getSizeInBits()) {
// Transfer high bits from the top of Lo to the bottom of Hi.
@@ -2255,9 +2255,9 @@
// Store the lowest ExcessBits bits in the second half.
Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
SVOffset+IncrementSize,
- MVT::getIntegerVT(ExcessBits),
+ EVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
}
@@ -2270,8 +2270,8 @@
SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
SDValue Op = N->getOperand(0);
- MVT SrcVT = Op.getValueType();
- MVT DstVT = N->getValueType(0);
+ EVT SrcVT = Op.getValueType();
+ EVT DstVT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
@@ -2288,11 +2288,11 @@
const uint64_t F32TwoE128 = 0x7F800000ULL;
APInt FF(32, 0);
- if (SrcVT == MVT::i32)
+ if (SrcVT == EVT::i32)
FF = APInt(32, F32TwoE32);
- else if (SrcVT == MVT::i64)
+ else if (SrcVT == EVT::i64)
FF = APInt(32, F32TwoE64);
- else if (SrcVT == MVT::i128)
+ else if (SrcVT == EVT::i128)
FF = APInt(32, F32TwoE128);
else
assert(false && "Unsupported UINT_TO_FP!");
@@ -2323,7 +2323,7 @@
// Load the value out, extending it from f32 to the destination float type.
// FIXME: Avoid the extend by constructing the right constant pool?
SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
- FudgePtr, NULL, 0, MVT::f32,
+ FudgePtr, NULL, 0, EVT::f32,
false, Alignment);
return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Mon Aug 10 17:56:29 2009
@@ -211,7 +211,7 @@
// Scan the values produced by the node, checking to see if any result
// types are illegal.
for (unsigned i = 0, NumResults = N->getNumValues(); i < NumResults; ++i) {
- MVT ResultVT = N->getValueType(i);
+ EVT ResultVT = N->getValueType(i);
switch (getTypeAction(ResultVT)) {
default:
assert(false && "Unknown action!");
@@ -264,7 +264,7 @@
if (IgnoreNodeResults(N->getOperand(i).getNode()))
continue;
- MVT OpVT = N->getOperand(i).getValueType();
+ EVT OpVT = N->getOperand(i).getValueType();
switch (getTypeAction(OpVT)) {
default:
assert(false && "Unknown action!");
@@ -861,7 +861,7 @@
SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
unsigned BitWidth = Op.getValueType().getSizeInBits();
return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
- MVT::getIntegerVT(BitWidth), Op);
+ EVT::getIntegerVT(BitWidth), Op);
}
/// BitConvertVectorToIntegerVector - Convert to a vector of integers of the
@@ -869,14 +869,14 @@
SDValue DAGTypeLegalizer::BitConvertVectorToIntegerVector(SDValue Op) {
assert(Op.getValueType().isVector() && "Only applies to vectors!");
unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits();
- MVT EltNVT = MVT::getIntegerVT(EltWidth);
+ EVT EltNVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = Op.getValueType().getVectorNumElements();
return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
- MVT::getVectorVT(EltNVT, NumElts), Op);
+ EVT::getVectorVT(EltNVT, NumElts), Op);
}
SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
- MVT DestVT) {
+ EVT DestVT) {
DebugLoc dl = Op.getDebugLoc();
// Create the stack frame object. Make sure it is aligned for both
// the source and destination types.
@@ -895,7 +895,7 @@
/// The last parameter being TRUE means we are dealing with a
/// node with illegal result types. The second parameter denotes the type of
/// illegal ResNo in that case.
-bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, MVT VT, bool LegalizeResult) {
+bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult) {
// See if the target wants to custom lower this node.
if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom)
return false;
@@ -920,14 +920,14 @@
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
/// which is split into two not necessarily identical pieces.
-void DAGTypeLegalizer::GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT) {
+void DAGTypeLegalizer::GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT) {
// Currently all types are split in half.
if (!InVT.isVector()) {
LoVT = HiVT = TLI.getTypeToTransformTo(InVT);
} else {
unsigned NumElements = InVT.getVectorNumElements();
assert(!(NumElements & 1) && "Splitting vector, but not in half!");
- LoVT = HiVT = MVT::getVectorVT(InVT.getVectorElementType(), NumElements/2);
+ LoVT = HiVT = EVT::getVectorVT(InVT.getVectorElementType(), NumElements/2);
}
}
@@ -936,14 +936,14 @@
void DAGTypeLegalizer::GetPairElements(SDValue Pair,
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = Pair.getDebugLoc();
- MVT NVT = TLI.getTypeToTransformTo(Pair.getValueType());
+ EVT NVT = TLI.getTypeToTransformTo(Pair.getValueType());
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
DAG.getIntPtrConstant(0));
Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
DAG.getIntPtrConstant(1));
}
-SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
+SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, EVT EltVT,
SDValue Index) {
DebugLoc dl = Index.getDebugLoc();
// Make sure the index type is big enough to compute in.
@@ -965,9 +965,9 @@
// Arbitrarily use dlHi for result DebugLoc
DebugLoc dlHi = Hi.getDebugLoc();
DebugLoc dlLo = Lo.getDebugLoc();
- MVT LVT = Lo.getValueType();
- MVT HVT = Hi.getValueType();
- MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
+ EVT LVT = Lo.getValueType();
+ EVT HVT = Hi.getValueType();
+ EVT NVT = EVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
@@ -999,7 +999,7 @@
/// MakeLibCall - Generate a libcall taking the given operands as arguments and
/// returning a result of type RetVT.
-SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
+SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, EVT RetVT,
const SDValue *Ops, unsigned NumOps,
bool isSigned, DebugLoc dl) {
TargetLowering::ArgListTy Args;
@@ -1008,7 +1008,7 @@
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0; i != NumOps; ++i) {
Entry.Node = Ops[i];
- Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
+ Entry.Ty = Entry.Node.getValueType().getTypeForEVT();
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
@@ -1016,7 +1016,7 @@
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
TLI.getPointerTy());
- const Type *RetTy = RetVT.getTypeForMVT();
+ const Type *RetTy = RetVT.getTypeForEVT();
std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
false, 0, CallingConv::C, false,
@@ -1028,7 +1028,7 @@
/// PromoteTargetBoolean - Promote the given target boolean to a target boolean
/// of the given type. A target boolean is an integer value, not necessarily of
/// type i1, the bits of which conform to getBooleanContents.
-SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) {
+SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, EVT VT) {
DebugLoc dl = Bool.getDebugLoc();
ISD::NodeType ExtendCode;
switch (TLI.getBooleanContents()) {
@@ -1054,7 +1054,7 @@
/// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT
/// bits in Hi.
void DAGTypeLegalizer::SplitInteger(SDValue Op,
- MVT LoVT, MVT HiVT,
+ EVT LoVT, EVT HiVT,
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = Op.getDebugLoc();
assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
@@ -1069,7 +1069,7 @@
/// type half the size of Op's.
void DAGTypeLegalizer::SplitInteger(SDValue Op,
SDValue &Lo, SDValue &Hi) {
- MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
+ EVT HalfVT = EVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Aug 10 17:56:29 2009
@@ -74,7 +74,7 @@
TargetLowering::ValueTypeActionImpl ValueTypeActions;
/// getTypeAction - Return how we should legalize values of this type.
- LegalizeAction getTypeAction(MVT VT) const {
+ LegalizeAction getTypeAction(EVT VT) const {
switch (ValueTypeActions.getTypeAction(VT)) {
default:
assert(false && "Unknown legalize action!");
@@ -109,7 +109,7 @@
}
/// isTypeLegal - Return true if this type is legal on this target.
- bool isTypeLegal(MVT VT) const {
+ bool isTypeLegal(EVT VT) const {
return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal;
}
@@ -159,7 +159,7 @@
explicit DAGTypeLegalizer(SelectionDAG &dag)
: TLI(dag.getTargetLoweringInfo()), DAG(dag),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
+ assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
@@ -185,19 +185,19 @@
// Common routines.
SDValue BitConvertToInteger(SDValue Op);
SDValue BitConvertVectorToIntegerVector(SDValue Op);
- SDValue CreateStackStoreLoad(SDValue Op, MVT DestVT);
- bool CustomLowerNode(SDNode *N, MVT VT, bool LegalizeResult);
- SDValue GetVectorElementPointer(SDValue VecPtr, MVT EltVT, SDValue Index);
+ SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
+ bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
+ SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index);
SDValue JoinIntegers(SDValue Lo, SDValue Hi);
SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
- SDValue MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
+ SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT,
const SDValue *Ops, unsigned NumOps, bool isSigned,
DebugLoc dl);
- SDValue PromoteTargetBoolean(SDValue Bool, MVT VT);
+ SDValue PromoteTargetBoolean(SDValue Bool, EVT VT);
void ReplaceValueWith(SDValue From, SDValue To);
void ReplaceValueWithHelper(SDValue From, SDValue To);
void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
- void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT,
+ void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
SDValue &Lo, SDValue &Hi);
//===--------------------------------------------------------------------===//
@@ -224,7 +224,7 @@
/// SExtPromotedInteger - Get a promoted operand and sign extend it to the
/// final size.
SDValue SExtPromotedInteger(SDValue Op) {
- MVT OldVT = Op.getValueType();
+ EVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
@@ -234,7 +234,7 @@
/// ZExtPromotedInteger - Get a promoted operand and zero extend it to the
/// final size.
SDValue ZExtPromotedInteger(SDValue Op) {
- MVT OldVT = Op.getValueType();
+ EVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
return DAG.getZeroExtendInReg(Op, dl, OldVT);
@@ -641,7 +641,7 @@
SDValue BasePtr, const Value *SV,
int SVOffset, unsigned Alignment,
bool isVolatile, unsigned LdWidth,
- MVT ResType, DebugLoc dl);
+ EVT ResType, DebugLoc dl);
/// Helper genWidenVectorStores - Helper function to generate a set of
/// stores to store a widen vector into non widen memory
@@ -664,7 +664,7 @@
/// Modifies a vector input (widen or narrows) to a vector of NVT. The
/// input vector must have the same element type as NVT.
- SDValue ModifyToType(SDValue InOp, MVT WidenVT);
+ SDValue ModifyToType(SDValue InOp, EVT WidenVT);
//===--------------------------------------------------------------------===//
@@ -686,7 +686,7 @@
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
/// which is split (or expanded) into two not necessarily identical pieces.
- void GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT);
+ void GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT);
/// GetPairElements - Use ISD::EXTRACT_ELEMENT nodes to extract the low and
/// high parts of the given value.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Mon Aug 10 17:56:29 2009
@@ -34,10 +34,10 @@
void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT OutVT = N->getValueType(0);
- MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
+ EVT OutVT = N->getValueType(0);
+ EVT NOutVT = TLI.getTypeToTransformTo(OutVT);
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
DebugLoc dl = N->getDebugLoc();
// Handle some special cases efficiently.
@@ -76,7 +76,7 @@
case WidenVector: {
assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BIT_CONVERT");
InOp = GetWidenedVector(InOp);
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
InVT.getVectorNumElements()/2);
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -93,7 +93,7 @@
if (InVT.isVector() && OutVT.isInteger()) {
// Handle cases like i64 = BIT_CONVERT v1i64 on x86, where the operand
// is legal but the result is not.
- MVT NVT = MVT::getVectorVT(NOutVT, 2);
+ EVT NVT = EVT::getVectorVT(NOutVT, 2);
if (isTypeLegal(NVT)) {
SDValue CastInOp = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, InOp);
@@ -115,7 +115,7 @@
// Create the stack frame object. Make sure it is aligned for both
// the source and expanded destination types.
unsigned Alignment =
- TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForMVT());
+ TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForEVT());
SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
@@ -167,11 +167,11 @@
// Convert to a vector of the expanded element type, for example
// <3 x i64> -> <6 x i32>.
- MVT OldVT = N->getValueType(0);
- MVT NewVT = TLI.getTypeToTransformTo(OldVT);
+ EVT OldVT = N->getValueType(0);
+ EVT NewVT = TLI.getTypeToTransformTo(OldVT);
SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::getVectorVT(NewVT, 2*OldElts),
+ EVT::getVectorVT(NewVT, 2*OldElts),
OldVec);
// Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
@@ -198,7 +198,7 @@
DebugLoc dl = N->getDebugLoc();
LoadSDNode *LD = cast<LoadSDNode>(N);
- MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
int SVOffset = LD->getSrcValueOffset();
@@ -220,7 +220,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Handle endianness of the load.
@@ -233,7 +233,7 @@
}
void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Chain = N->getOperand(0);
SDValue Ptr = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
@@ -263,8 +263,8 @@
// instead, but only if the new vector type is legal (otherwise there
// is no point, and it might create expansion loops). For example, on
// x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32.
- MVT OVT = N->getOperand(0).getValueType();
- MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
+ EVT OVT = N->getOperand(0).getValueType();
+ EVT NVT = EVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
if (isTypeLegal(NVT)) {
SDValue Parts[2];
@@ -284,10 +284,10 @@
SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
// The vector type is legal but the element type needs expansion.
- MVT VecVT = N->getValueType(0);
+ EVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
- MVT OldVT = N->getOperand(0).getValueType();
- MVT NewVT = TLI.getTypeToTransformTo(OldVT);
+ EVT OldVT = N->getOperand(0).getValueType();
+ EVT NewVT = TLI.getTypeToTransformTo(OldVT);
DebugLoc dl = N->getDebugLoc();
assert(OldVT == VecVT.getVectorElementType() &&
@@ -308,7 +308,7 @@
}
SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
- MVT::getVectorVT(NewVT, NewElts.size()),
+ EVT::getVectorVT(NewVT, NewElts.size()),
&NewElts[0], NewElts.size());
// Convert the new vector to the old vector type.
@@ -323,20 +323,20 @@
SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
// The vector type is legal but the element type needs expansion.
- MVT VecVT = N->getValueType(0);
+ EVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
DebugLoc dl = N->getDebugLoc();
SDValue Val = N->getOperand(1);
- MVT OldEVT = Val.getValueType();
- MVT NewEVT = TLI.getTypeToTransformTo(OldEVT);
+ EVT OldEVT = Val.getValueType();
+ EVT NewEVT = TLI.getTypeToTransformTo(OldEVT);
assert(OldEVT == VecVT.getVectorElementType() &&
"Inserted element type doesn't match vector element type!");
// Bitconvert to a vector of twice the length with elements of the expanded
// type, insert the expanded vector elements, and then convert back.
- MVT NewVecVT = MVT::getVectorVT(NewEVT, NumElts*2);
+ EVT NewVecVT = EVT::getVectorVT(NewEVT, NumElts*2);
SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
NewVecVT, N->getOperand(0));
@@ -358,7 +358,7 @@
SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
"SCALAR_TO_VECTOR operand type doesn't match vector element type!");
unsigned NumElts = VT.getVectorNumElements();
@@ -376,7 +376,7 @@
DebugLoc dl = N->getDebugLoc();
StoreSDNode *St = cast<StoreSDNode>(N);
- MVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType());
+ EVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType());
SDValue Chain = St->getChain();
SDValue Ptr = St->getBasePtr();
int SVOffset = St->getSrcValueOffset();
@@ -402,7 +402,7 @@
SVOffset + IncrementSize,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
@@ -462,7 +462,7 @@
}
void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getUNDEF(LoVT);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Mon Aug 10 17:56:29 2009
@@ -129,7 +129,7 @@
if (!HasVectorValue)
return TranslateLegalizeResults(Op, Result);
- MVT QueryType;
+ EVT QueryType;
switch (Op.getOpcode()) {
default:
return TranslateLegalizeResults(Op, Result);
@@ -231,10 +231,10 @@
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't promote a vector with multiple results!");
- MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
+ EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
@@ -260,11 +260,11 @@
}
SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
unsigned NumElems = VT.getVectorNumElements();
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
- MVT TmpEltVT = LHS.getValueType().getVectorElementType();
+ EVT TmpEltVT = LHS.getValueType().getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 8> Ops(NumElems);
for (unsigned i = 0; i < NumElems; ++i) {
@@ -287,11 +287,11 @@
/// the operation be expanded. "Unroll" the vector, splitting out the scalars
/// and operating on each element individually.
SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't unroll a vector with multiple results!");
unsigned NE = VT.getVectorNumElements();
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 8> Scalars;
@@ -299,14 +299,14 @@
for (unsigned i = 0; i != NE; ++i) {
for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
SDValue Operand = Op.getOperand(j);
- MVT OperandVT = Operand.getValueType();
+ EVT OperandVT = Operand.getValueType();
if (OperandVT.isVector()) {
// A vector operand; extract a single element.
- MVT OperandEltVT = OperandVT.getVectorElementType();
+ EVT OperandEltVT = OperandVT.getVectorElementType();
Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
OperandEltVT,
Operand,
- DAG.getConstant(i, MVT::i32));
+ DAG.getConstant(i, EVT::i32));
} else {
// A scalar operand; just use it as is.
Operands[j] = Operand;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Aug 10 17:56:29 2009
@@ -118,13 +118,13 @@
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
- MVT NewVT = N->getValueType(0).getVectorElementType();
+ EVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
NewVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
- MVT NewVT = N->getValueType(0).getVectorElementType();
+ EVT NewVT = N->getValueType(0).getVectorElementType();
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
Op0, DAG.getValueType(NewVT),
@@ -150,7 +150,7 @@
// The value to insert may have a wider type than the vector element type,
// so be sure to truncate it to the element type if necessary.
SDValue Op = N->getOperand(1);
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
if (Op.getValueType() != EltVT)
// FIXME: Can this happen for floating point types?
Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
@@ -177,7 +177,7 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
// Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
- MVT DestVT = N->getValueType(0).getVectorElementType();
+ EVT DestVT = N->getValueType(0).getVectorElementType();
SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
}
@@ -185,7 +185,7 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
// If the operand is wider than the vector element type then it is implicitly
// truncated. Make that explicit here.
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
SDValue InOp = N->getOperand(0);
if (InOp.getValueType() != EltVT)
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
@@ -213,7 +213,7 @@
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
- return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
+ return DAG.getNode(ISD::SETCC, DL, EVT::i1, LHS, RHS, N->getOperand(2));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
@@ -232,8 +232,8 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue RHS = GetScalarizedVector(N->getOperand(1));
- MVT NVT = N->getValueType(0).getVectorElementType();
- MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
+ EVT NVT = N->getValueType(0).getVectorElementType();
+ EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
@@ -247,16 +247,16 @@
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
- DAG.getValueType(MVT::i1));
+ DAG.getValueType(EVT::i1));
// Truncate to the final type.
return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
}
// The SETCC result type is smaller than the vector element type.
- // If the SetCC result is not sign-extended, chop it down to MVT::i1.
+ // If the SetCC result is not sign-extended, chop it down to EVT::i1.
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
- Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
+ Res = DAG.getNode(ISD::TRUNCATE, DL, EVT::i1, Res);
// Sign extend to the final type.
return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
}
@@ -472,12 +472,12 @@
SDValue &Hi) {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
DebugLoc dl = N->getDebugLoc();
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
switch (getTypeAction(InVT)) {
@@ -512,8 +512,8 @@
}
// In the general case, convert the input to an integer and split it by hand.
- MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
- MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
+ EVT LoIntVT = EVT::getIntegerVT(LoVT.getSizeInBits());
+ EVT HiIntVT = EVT::getIntegerVT(HiVT.getSizeInBits());
if (TLI.isBigEndian())
std::swap(LoIntVT, HiIntVT);
@@ -527,7 +527,7 @@
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
unsigned LoNumElts = LoVT.getVectorNumElements();
@@ -549,7 +549,7 @@
return;
}
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
@@ -561,7 +561,7 @@
void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
@@ -574,11 +574,11 @@
// Split the input.
SDValue VLo, VHi;
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: llvm_unreachable("Unexpected type action!");
case Legal: {
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -594,7 +594,7 @@
// the two types must have different lengths. Use the widened result
// and extract from it to do the split.
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -617,10 +617,10 @@
SDValue &Hi) {
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
- MVT IdxVT = Idx.getValueType();
+ EVT IdxVT = Idx.getValueType();
DebugLoc dl = N->getDebugLoc();
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
@@ -658,8 +658,8 @@
}
// Spill the vector to the stack.
- MVT VecVT = Vec.getValueType();
- MVT EltVT = VecVT.getVectorElementType();
+ EVT VecVT = Vec.getValueType();
+ EVT EltVT = VecVT.getVectorElementType();
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
@@ -667,7 +667,7 @@
// so use a truncating store.
SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
unsigned Alignment =
- TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
+ TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT());
Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
// Load the Lo part from the stack slot.
@@ -685,7 +685,7 @@
void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
@@ -695,7 +695,7 @@
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
SDValue &Hi) {
assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = LD->getDebugLoc();
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
@@ -705,11 +705,11 @@
SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
- MVT MemoryVT = LD->getMemoryVT();
+ EVT MemoryVT = LD->getMemoryVT();
unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile();
- MVT LoMemVT, HiMemVT;
+ EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
@@ -725,7 +725,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Legalized the chain result - switch anything that used the old chain to
@@ -734,14 +734,14 @@
}
void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc DL = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// Split the input.
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
SDValue LL, LH, RL, RH;
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -760,16 +760,16 @@
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// Get the dest types - they may not match the input types, e.g. int_to_fp.
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// Split the input.
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: llvm_unreachable("Unexpected type action!");
case Legal: {
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -785,7 +785,7 @@
// the two types must have different lengths. Use the widened result
// and extract from it to do the split.
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -806,7 +806,7 @@
DebugLoc dl = N->getDebugLoc();
GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
- MVT NewVT = Inputs[0].getValueType();
+ EVT NewVT = Inputs[0].getValueType();
unsigned NewElts = NewVT.getVectorNumElements();
// If Lo or Hi uses elements from at most two of the four input vectors, then
@@ -864,7 +864,7 @@
}
if (useBuildVector) {
- MVT EltVT = NewVT.getVectorElementType();
+ EVT EltVT = NewVT.getVectorElementType();
SmallVector<SDValue, 16> SVOps;
// Extract the input elements by hand.
@@ -969,13 +969,13 @@
SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
// The result has a legal vector type, but the input needs splitting.
- MVT ResVT = N->getValueType(0);
+ EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
DebugLoc dl = N->getDebugLoc();
GetSplitVector(N->getOperand(0), Lo, Hi);
- MVT InVT = Lo.getValueType();
+ EVT InVT = Lo.getValueType();
- MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
+ EVT OutVT = EVT::getVectorVT(ResVT.getVectorElementType(),
InVT.getVectorNumElements());
Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
@@ -1003,7 +1003,7 @@
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
// We know that the extracted result type is legal. For now, assume the index
// is a constant.
- MVT SubVT = N->getValueType(0);
+ EVT SubVT = N->getValueType(0);
SDValue Idx = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
SDValue Lo, Hi;
@@ -1025,7 +1025,7 @@
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
- MVT VecVT = Vec.getValueType();
+ EVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
@@ -1044,7 +1044,7 @@
}
// Store the vector to the stack.
- MVT EltVT = VecVT.getVectorElementType();
+ EVT EltVT = VecVT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
@@ -1066,13 +1066,13 @@
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
- MVT MemoryVT = N->getMemoryVT();
+ EVT MemoryVT = N->getMemoryVT();
unsigned Alignment = N->getAlignment();
bool isVol = N->isVolatile();
SDValue Lo, Hi;
GetSplitVector(N->getOperand(1), Lo, Hi);
- MVT LoMemVT, HiMemVT;
+ EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
@@ -1097,7 +1097,7 @@
Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVol, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
@@ -1197,7 +1197,7 @@
SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
// Binary op widening.
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp1 = GetWidenedVector(N->getOperand(0));
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
@@ -1207,12 +1207,12 @@
SDValue InOp = N->getOperand(0);
DebugLoc dl = N->getDebugLoc();
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
- MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
+ EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
unsigned Opcode = N->getOpcode();
unsigned InVTNumElts = InVT.getVectorNumElements();
@@ -1254,7 +1254,7 @@
// Otherwise unroll into some nasty scalar code and rebuild the vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
unsigned i;
for (i=0; i < MinElts; ++i)
@@ -1270,16 +1270,16 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp = GetWidenedVector(N->getOperand(0));
SDValue ShOp = N->getOperand(1);
- MVT ShVT = ShOp.getValueType();
+ EVT ShVT = ShOp.getValueType();
if (getTypeAction(ShVT) == WidenVector) {
ShOp = GetWidenedVector(ShOp);
ShVT = ShOp.getValueType();
}
- MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
+ EVT ShWidenVT = EVT::getVectorVT(ShVT.getVectorElementType(),
WidenVT.getVectorNumElements());
if (ShVT != ShWidenVT)
ShOp = ModifyToType(ShOp, ShWidenVT);
@@ -1289,16 +1289,16 @@
SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
// Unary op widening.
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp = GetWidenedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
}
SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
- MVT VT = N->getValueType(0);
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT InVT = InOp.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
switch (getTypeAction(InVT)) {
@@ -1338,13 +1338,13 @@
// Determine new input vector type. The new input vector type will use
// the same element type (if its a vector) or use the input type as a
// vector. It is the same size as the type to widen to.
- MVT NewInVT;
+ EVT NewInVT;
unsigned NewNumElts = WidenSize / InSize;
if (InVT.isVector()) {
- MVT InEltVT = InVT.getVectorElementType();
- NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
+ EVT InEltVT = InVT.getVectorElementType();
+ NewInVT= EVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
} else {
- NewInVT = MVT::getVectorVT(InVT, NewNumElts);
+ NewInVT = EVT::getVectorVT(InVT, NewNumElts);
}
if (TLI.isTypeLegal(NewInVT)) {
@@ -1376,11 +1376,11 @@
SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
// Build a vector with undefined for the new nodes.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
unsigned NumElts = VT.getVectorNumElements();
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
@@ -1392,8 +1392,8 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
- MVT InVT = N->getOperand(0).getValueType();
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT InVT = N->getOperand(0).getValueType();
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
unsigned WidenNumElts = WidenVT.getVectorNumElements();
unsigned NumOperands = N->getNumOperands();
@@ -1442,7 +1442,7 @@
}
// Fall back to use extracts and build vector.
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
unsigned NumInElts = InVT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(WidenNumElts);
unsigned Idx = 0;
@@ -1466,12 +1466,12 @@
SDValue RndOp = N->getOperand(3);
SDValue SatOp = N->getOperand(4);
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
- MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
+ EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
SDValue DTyOp = DAG.getValueType(WidenVT);
SDValue STyOp = DAG.getValueType(InWidenVT);
@@ -1518,7 +1518,7 @@
// Otherwise unroll into some nasty scalar code and rebuild the vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
DTyOp = DAG.getValueType(EltVT);
STyOp = DAG.getValueType(InEltVT);
@@ -1539,8 +1539,8 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
- MVT VT = N->getValueType(0);
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
SDValue Idx = N->getOperand(1);
@@ -1549,7 +1549,7 @@
if (getTypeAction(InOp.getValueType()) == WidenVector)
InOp = GetWidenedVector(InOp);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
if (CIdx) {
@@ -1567,8 +1567,8 @@
// We could try widening the input to the right length but for now, extract
// the original elements, fill the rest with undefs and build a vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = VT.getVectorElementType();
- MVT IdxVT = Idx.getValueType();
+ EVT EltVT = VT.getVectorElementType();
+ EVT IdxVT = Idx.getValueType();
unsigned NumElts = VT.getVectorNumElements();
unsigned i;
if (CIdx) {
@@ -1600,8 +1600,8 @@
SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
- MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
- MVT LdVT = LD->getMemoryVT();
+ EVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
+ EVT LdVT = LD->getMemoryVT();
DebugLoc dl = N->getDebugLoc();
assert(LdVT.isVector() && WidenVT.isVector());
@@ -1620,8 +1620,8 @@
// For extension loads, we can not play the tricks of chopping legal
// vector types and bit cast it to the right type. Instead, we unroll
// the load and build a vector.
- MVT EltVT = WidenVT.getVectorElementType();
- MVT LdEltVT = LdVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
+ EVT LdEltVT = LdVT.getVectorElementType();
unsigned NumElts = LdVT.getVectorNumElements();
// Load each element and widen
@@ -1660,7 +1660,7 @@
if (LdChain.size() == 1)
NewChain = LdChain[0];
else
- NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LdChain[0],
LdChain.size());
// Modified the chain - switch anything that used the old chain to use
@@ -1671,20 +1671,20 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
WidenVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue Cond1 = N->getOperand(0);
- MVT CondVT = Cond1.getValueType();
+ EVT CondVT = Cond1.getValueType();
if (CondVT.isVector()) {
- MVT CondEltVT = CondVT.getVectorElementType();
- MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
+ EVT CondEltVT = CondVT.getVectorElementType();
+ EVT CondWidenVT = EVT::getVectorVT(CondEltVT, WidenNumElts);
if (getTypeAction(CondVT) == WidenVector)
Cond1 = GetWidenedVector(Cond1);
@@ -1708,15 +1708,15 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getUNDEF(WidenVT);
}
SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned NumElts = VT.getVectorNumElements();
unsigned WidenNumElts = WidenVT.getVectorNumElements();
@@ -1738,13 +1738,13 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue InOp1 = N->getOperand(0);
- MVT InVT = InOp1.getValueType();
+ EVT InVT = InOp1.getValueType();
assert(InVT.isVector() && "can not widen non vector type");
- MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
+ EVT WidenInVT = EVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
InOp1 = GetWidenedVector(InOp1);
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
@@ -1812,15 +1812,15 @@
// Since the result is legal and the input is illegal, it is unlikely
// that we can fix the input to a legal type so unroll the convert
// into some scalar code and create a nasty build vector.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
unsigned NumElts = VT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
if (getTypeAction(InOp.getValueType()) == WidenVector)
InOp = GetWidenedVector(InOp);
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
unsigned Opcode = N->getOpcode();
SmallVector<SDValue, 16> Ops(NumElts);
@@ -1833,9 +1833,9 @@
}
SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InWidenVT = InOp.getValueType();
+ EVT InWidenVT = InOp.getValueType();
DebugLoc dl = N->getDebugLoc();
// Check if we can convert between two legal vector types and extract.
@@ -1843,7 +1843,7 @@
unsigned Size = VT.getSizeInBits();
if (InWidenSize % Size == 0 && !VT.isVector()) {
unsigned NewNumElts = InWidenSize / Size;
- MVT NewVT = MVT::getVectorVT(VT, NewNumElts);
+ EVT NewVT = EVT::getVectorVT(VT, NewNumElts);
if (TLI.isTypeLegal(NewVT)) {
SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
@@ -1858,13 +1858,13 @@
// If the input vector is not legal, it is likely that we will not find a
// legal vector of the same size. Replace the concatenate vector with a
// nasty build vector.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
unsigned NumElts = VT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(NumElts);
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
unsigned NumInElts = InVT.getVectorNumElements();
unsigned Idx = 0;
@@ -1899,8 +1899,8 @@
SDValue ValOp = GetWidenedVector(ST->getValue());
DebugLoc dl = N->getDebugLoc();
- MVT StVT = ST->getMemoryVT();
- MVT ValVT = ValOp.getValueType();
+ EVT StVT = ST->getMemoryVT();
+ EVT ValVT = ValOp.getValueType();
// It must be true that we the widen vector type is bigger than where
// we need to store.
assert(StVT.isVector() && ValOp.getValueType().isVector());
@@ -1911,8 +1911,8 @@
// For truncating stores, we can not play the tricks of chopping legal
// vector types and bit cast it to the right type. Instead, we unroll
// the store.
- MVT StEltVT = StVT.getVectorElementType();
- MVT ValEltVT = ValVT.getVectorElementType();
+ EVT StEltVT = StVT.getVectorElementType();
+ EVT ValEltVT = ValVT.getVectorElementType();
unsigned Increment = ValEltVT.getSizeInBits() / 8;
unsigned NumElts = StVT.getVectorNumElements();
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
@@ -1941,7 +1941,7 @@
return StChain[0];
else
return DAG.getNode(ISD::TokenFactor, dl,
- MVT::Other,&StChain[0],StChain.size());
+ EVT::Other,&StChain[0],StChain.size());
}
//===----------------------------------------------------------------------===//
@@ -1958,8 +1958,8 @@
// Returns NewVecVT and NewEltVT - the vector type and its associated
// element type.
static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
- MVT VecVT,
- MVT& NewEltVT, MVT& NewVecVT) {
+ EVT VecVT,
+ EVT& NewEltVT, EVT& NewVecVT) {
unsigned EltWidth = Width + 1;
if (TLI.isTypeLegal(VecVT)) {
// We start with the preferred with, making it a power of 2 and find a
@@ -1969,9 +1969,9 @@
do {
assert(EltWidth > 0);
EltWidth = 1 << Log2_32(EltWidth - 1);
- NewEltVT = MVT::getIntegerVT(EltWidth);
+ NewEltVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
- NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
+ NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
} while (!TLI.isTypeLegal(NewVecVT) ||
VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
} else {
@@ -1984,9 +1984,9 @@
do {
assert(EltWidth > 0);
EltWidth = 1 << Log2_32(EltWidth - 1);
- NewEltVT = MVT::getIntegerVT(EltWidth);
+ NewEltVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
- NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
+ NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
} while (!TLI.isTypeLegal(NewEltVT) ||
VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
}
@@ -2000,7 +2000,7 @@
unsigned Alignment,
bool isVolatile,
unsigned LdWidth,
- MVT ResType,
+ EVT ResType,
DebugLoc dl) {
// The strategy assumes that we can efficiently load powers of two widths.
// The routines chops the vector into the largest power of 2 load and
@@ -2011,7 +2011,7 @@
// the load is nonvolatile, we an use a wider load for the value.
// Find the vector type that can load from.
- MVT NewEltVT, NewVecVT;
+ EVT NewEltVT, NewVecVT;
unsigned NewEltVTWidth;
FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
NewEltVTWidth = NewEltVT.getSizeInBits();
@@ -2075,8 +2075,8 @@
// want to store. This avoids requiring a stack convert.
// Find a width of the element type we can store with
- MVT WidenVT = ValOp.getValueType();
- MVT NewEltVT, NewVecVT;
+ EVT WidenVT = ValOp.getValueType();
+ EVT NewEltVT, NewVecVT;
FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
@@ -2125,10 +2125,10 @@
/// Modifies a vector input (widen or narrows) to a vector of NVT. The
/// input vector must have the same element type as NVT.
-SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
+SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
// Note that InOp might have been widened so it might already have
// the right width or it might need be narrowed.
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match");
DebugLoc dl = InOp.getDebugLoc();
@@ -2156,7 +2156,7 @@
// Fall back to extract and build.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = NVT.getVectorElementType();
+ EVT EltVT = NVT.getVectorElementType();
unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
unsigned Idx;
for (Idx = 0; Idx < MinNumElts; ++Idx)
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Mon Aug 10 17:56:29 2009
@@ -215,16 +215,16 @@
SUnit *NewSU;
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT == MVT::Flag)
+ EVT VT = N->getValueType(i);
+ if (VT == EVT::Flag)
return NULL;
- else if (VT == MVT::Other)
+ else if (VT == EVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
- MVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == MVT::Flag)
+ EVT VT = Op.getNode()->getValueType(Op.getResNo());
+ if (VT == EVT::Flag)
return NULL;
}
@@ -420,7 +420,7 @@
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
/// definition of the specified node.
/// FIXME: Move to SelectionDAG?
-static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
+static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
@@ -534,7 +534,7 @@
assert(LRegs.size() == 1 && "Can't handle this yet!");
unsigned Reg = LRegs[0];
SUnit *LRDef = LiveRegDefs[Reg];
- MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
+ EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
const TargetRegisterClass *RC =
TRI->getPhysicalRegisterRegClass(Reg, VT);
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Aug 10 17:56:29 2009
@@ -352,16 +352,16 @@
SUnit *NewSU;
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT == MVT::Flag)
+ EVT VT = N->getValueType(i);
+ if (VT == EVT::Flag)
return NULL;
- else if (VT == MVT::Other)
+ else if (VT == EVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
- MVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == MVT::Flag)
+ EVT VT = Op.getNode()->getValueType(Op.getResNo());
+ if (VT == EVT::Flag)
return NULL;
}
@@ -571,7 +571,7 @@
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
/// definition of the specified node.
/// FIXME: Move to SelectionDAG?
-static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
+static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
@@ -630,7 +630,7 @@
if (Node->getOpcode() == ISD::INLINEASM) {
// Inline asm can clobber physical defs.
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
--NumOps; // Ignore the flag operand.
for (unsigned i = 2; i != NumOps;) {
@@ -754,7 +754,7 @@
assert(LRegs.size() == 1 && "Can't handle this yet!");
unsigned Reg = LRegs[0];
SUnit *LRDef = LiveRegDefs[Reg];
- MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
+ EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
const TargetRegisterClass *RC =
TRI->getPhysicalRegisterRegClass(Reg, VT);
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
@@ -1216,8 +1216,8 @@
if (!SUImpDefs)
return false;
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT == MVT::Flag || VT == MVT::Other)
+ EVT VT = N->getValueType(i);
+ if (VT == EVT::Flag || VT == EVT::Other)
continue;
if (!N->hasAnyUseOfValue(i))
continue;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon Aug 10 17:56:29 2009
@@ -111,7 +111,7 @@
// Scan up to find flagged preds.
SDNode *N = NI;
while (N->getNumOperands() &&
- N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
+ N->getOperand(N->getNumOperands()-1).getValueType() == EVT::Flag) {
N = N->getOperand(N->getNumOperands()-1).getNode();
assert(N->getNodeId() == -1 && "Node already inserted!");
N->setNodeId(NodeSUnit->NodeNum);
@@ -119,7 +119,7 @@
// Scan down to find any flagged succs.
N = NI;
- while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
+ while (N->getValueType(N->getNumValues()-1) == EVT::Flag) {
SDValue FlagVal(N, N->getNumValues()-1);
// There are either zero or one users of the Flag result.
@@ -189,9 +189,9 @@
assert(OpSU && "Node has no SUnit!");
if (OpSU == SU) continue; // In the same group.
- MVT OpVT = N->getOperand(i).getValueType();
- assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
- bool isChain = OpVT == MVT::Other;
+ EVT OpVT = N->getOperand(i).getValueType();
+ assert(OpVT != EVT::Flag && "Flagged nodes should be in same sunit!");
+ bool isChain = OpVT == EVT::Other;
unsigned PhysReg = 0;
int Cost = 1;
@@ -244,9 +244,9 @@
/// not go into the resulting MachineInstr).
unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
unsigned N = Node->getNumValues();
- while (N && Node->getValueType(N - 1) == MVT::Flag)
+ while (N && Node->getValueType(N - 1) == EVT::Flag)
--N;
- if (N && Node->getValueType(N - 1) == MVT::Other)
+ if (N && Node->getValueType(N - 1) == EVT::Other)
--N; // Skip over chain result.
return N;
}
@@ -266,9 +266,9 @@
/// operand
unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
unsigned N = Node->getNumOperands();
- while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
+ while (N && Node->getOperand(N - 1).getValueType() == EVT::Flag)
--N;
- if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
+ if (N && Node->getOperand(N - 1).getValueType() == EVT::Other)
--N; // Ignore chain if it exists.
return N;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Mon Aug 10 17:56:29 2009
@@ -69,8 +69,8 @@
SDValue Op = User->getOperand(i);
if (Op.getNode() != Node || Op.getResNo() != ResNo)
continue;
- MVT VT = Node->getValueType(Op.getResNo());
- if (VT == MVT::Other || VT == MVT::Flag)
+ EVT VT = Node->getValueType(Op.getResNo());
+ if (VT == EVT::Other || VT == EVT::Flag)
continue;
Match = false;
if (User->isMachineOpcode()) {
@@ -95,7 +95,7 @@
break;
}
- MVT VT = Node->getValueType(ResNo);
+ EVT VT = Node->getValueType(ResNo);
const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
@@ -238,8 +238,8 @@
unsigned IIOpNum,
const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap) {
- assert(Op.getValueType() != MVT::Other &&
- Op.getValueType() != MVT::Flag &&
+ assert(Op.getValueType() != EVT::Other &&
+ Op.getValueType() != EVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
@@ -322,8 +322,8 @@
MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
ES->getTargetFlags()));
} else {
- assert(Op.getValueType() != MVT::Other &&
- Op.getValueType() != MVT::Flag &&
+ assert(Op.getValueType() != EVT::Other &&
+ Op.getValueType() != EVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
}
@@ -334,7 +334,7 @@
/// type matches the specified type.
static const TargetRegisterClass*
getSuperRegisterRegClass(const TargetRegisterClass *TRC,
- unsigned SubIdx, MVT VT) {
+ unsigned SubIdx, EVT VT) {
// Pick the register class of the superegister for this type
for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
E = TRC->superregclasses_end(); I != E; ++I)
@@ -599,7 +599,7 @@
}
case ISD::INLINEASM: {
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
--NumOps; // Ignore the flag operand.
// Create the inline asm machine instruction.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Aug 10 17:56:29 2009
@@ -47,19 +47,19 @@
/// makeVTList - Return an instance of the SDVTList struct initialized with the
/// specified members.
-static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
+static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) {
SDVTList Res = {VTs, NumVTs};
return Res;
}
-static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
+static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
switch (VT.getSimpleVT()) {
default: llvm_unreachable("Unknown FP format");
- case MVT::f32: return &APFloat::IEEEsingle;
- case MVT::f64: return &APFloat::IEEEdouble;
- case MVT::f80: return &APFloat::x87DoubleExtended;
- case MVT::f128: return &APFloat::IEEEquad;
- case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
+ case EVT::f32: return &APFloat::IEEEsingle;
+ case EVT::f64: return &APFloat::IEEEdouble;
+ case EVT::f80: return &APFloat::x87DoubleExtended;
+ case EVT::f128: return &APFloat::IEEEquad;
+ case EVT::ppcf128: return &APFloat::PPCDoubleDouble;
}
}
@@ -77,19 +77,19 @@
return getValueAPF().bitwiseIsEqual(V);
}
-bool ConstantFPSDNode::isValueValidForType(MVT VT,
+bool ConstantFPSDNode::isValueValidForType(EVT VT,
const APFloat& Val) {
assert(VT.isFloatingPoint() && "Can only convert between FP types");
// PPC long double cannot be converted to any other type.
- if (VT == MVT::ppcf128 ||
+ if (VT == EVT::ppcf128 ||
&Val.getSemantics() == &APFloat::PPCDoubleDouble)
return false;
// convert modifies in place, so make a copy.
APFloat Val2 = APFloat(Val);
bool losesInfo;
- (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
+ (void) Val2.convert(*EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
&losesInfo);
return !losesInfo;
}
@@ -502,7 +502,7 @@
/// doNotCSE - Return true if CSE should not be performed for this node.
static bool doNotCSE(SDNode *N) {
- if (N->getValueType(0) == MVT::Flag)
+ if (N->getValueType(0) == EVT::Flag)
return true; // Never CSE anything that produces a flag.
switch (N->getOpcode()) {
@@ -517,7 +517,7 @@
// Check that remaining values produced are not flags.
for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
- if (N->getValueType(i) == MVT::Flag)
+ if (N->getValueType(i) == EVT::Flag)
return true; // Never CSE anything that produces a flag.
return false;
@@ -638,7 +638,7 @@
break;
}
case ISD::VALUETYPE: {
- MVT VT = cast<VTSDNode>(N)->getVT();
+ EVT VT = cast<VTSDNode>(N)->getVT();
if (VT.isExtended()) {
Erased = ExtendedValueTypeNodes.erase(VT);
} else {
@@ -656,7 +656,7 @@
// Verify that the node was actually in one of the CSE maps, unless it has a
// flag result (which cannot be CSE'd) or is one of the special cases that are
// not subject to CSE.
- if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
+ if (!Erased && N->getValueType(N->getNumValues()-1) != EVT::Flag &&
!N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this);
cerr << "\n";
@@ -754,7 +754,7 @@
default:
break;
case ISD::BUILD_PAIR: {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
assert(N->getNumValues() == 1 && "Too many results!");
assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &&
"Wrong return type!");
@@ -772,7 +772,7 @@
assert(N->getValueType(0).isVector() && "Wrong return type!");
assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
"Wrong number of operands!");
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
assert((I->getValueType() == EltVT ||
(EltVT.isInteger() && I->getValueType().isInteger() &&
@@ -783,13 +783,13 @@
}
}
-/// getMVTAlignment - Compute the default alignment value for the
+/// getEVTAlignment - Compute the default alignment value for the
/// given type.
///
-unsigned SelectionDAG::getMVTAlignment(MVT VT) const {
- const Type *Ty = VT == MVT::iPTR ?
+unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
+ const Type *Ty = VT == EVT::iPTR ?
PointerType::get(Type::Int8Ty, 0) :
- VT.getTypeForMVT();
+ VT.getTypeForEVT();
return TLI.getTargetData()->getABITypeAlignment(Ty);
}
@@ -798,7 +798,7 @@
SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
: TLI(tli), FLI(fli), DW(0),
EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
- getVTList(MVT::Other)), Root(getEntryNode()) {
+ getVTList(EVT::Other)), Root(getEntryNode()) {
AllNodes.push_back(&EntryNode);
}
@@ -839,7 +839,7 @@
Root = getEntryNode();
}
-SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
+SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT VT) {
if (Op.getValueType() == VT) return Op;
APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
VT.getSizeInBits());
@@ -849,29 +849,29 @@
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
///
-SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
- MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
+SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, EVT VT) {
+ EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
SDValue NegOne =
getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
return getNode(ISD::XOR, DL, VT, Val, NegOne);
}
-SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
- MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
+SDValue SelectionDAG::getConstant(uint64_t Val, EVT VT, bool isT) {
+ EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
assert((EltVT.getSizeInBits() >= 64 ||
(uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
"getConstant with a uint64_t value that doesn't fit in the type!");
return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
}
-SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
+SDValue SelectionDAG::getConstant(const APInt &Val, EVT VT, bool isT) {
return getConstant(*ConstantInt::get(*Context, Val), VT, isT);
}
-SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) {
+SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
assert(VT.isInteger() && "Cannot create FP integer constant!");
- MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
+ EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
"APInt size does not match type size!");
@@ -906,14 +906,14 @@
}
-SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
+SDValue SelectionDAG::getConstantFP(const APFloat& V, EVT VT, bool isTarget) {
return getConstantFP(*ConstantFP::get(*getContext(), V), VT, isTarget);
}
-SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){
+SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){
assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
- MVT EltVT =
+ EVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
// Do the map lookup using the actual bit pattern for the floating point
@@ -946,24 +946,24 @@
return Result;
}
-SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
- MVT EltVT =
+SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) {
+ EVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
- if (EltVT==MVT::f32)
+ if (EltVT==EVT::f32)
return getConstantFP(APFloat((float)Val), VT, isTarget);
else
return getConstantFP(APFloat(Val), VT, isTarget);
}
SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
- MVT VT, int64_t Offset,
+ EVT VT, int64_t Offset,
bool isTargetGA,
unsigned char TargetFlags) {
assert((TargetFlags == 0 || isTargetGA) &&
"Cannot set target flags on target-independent globals");
// Truncate (with sign-extension) the offset value to the pointer size.
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned BitWidth = PTy.getSizeInBits();
if (BitWidth < 64)
Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth));
@@ -996,7 +996,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
+SDValue SelectionDAG::getFrameIndex(int FI, EVT VT, bool isTarget) {
unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
@@ -1011,7 +1011,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget,
+SDValue SelectionDAG::getJumpTable(int JTI, EVT VT, bool isTarget,
unsigned char TargetFlags) {
assert((TargetFlags == 0 || isTarget) &&
"Cannot set target flags on target-independent jump tables");
@@ -1030,7 +1030,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT,
+SDValue SelectionDAG::getConstantPool(Constant *C, EVT VT,
unsigned Alignment, int Offset,
bool isTarget,
unsigned char TargetFlags) {
@@ -1056,7 +1056,7 @@
}
-SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
+SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT,
unsigned Alignment, int Offset,
bool isTarget,
unsigned char TargetFlags) {
@@ -1083,7 +1083,7 @@
SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::BasicBlock, getVTList(EVT::Other), 0, 0);
ID.AddPointer(MBB);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1095,7 +1095,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getValueType(MVT VT) {
+SDValue SelectionDAG::getValueType(EVT VT) {
if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
ValueTypeNodes.resize(VT.getSimpleVT()+1);
@@ -1109,7 +1109,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
+SDValue SelectionDAG::getExternalSymbol(const char *Sym, EVT VT) {
SDNode *&N = ExternalSymbols[Sym];
if (N) return SDValue(N, 0);
N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
@@ -1118,7 +1118,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT,
+SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, EVT VT,
unsigned char TargetFlags) {
SDNode *&N =
TargetExternalSymbols[std::pair<std::string,unsigned char>(Sym,
@@ -1157,7 +1157,7 @@
}
}
-SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1,
+SDValue SelectionDAG::getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1,
SDValue N2, const int *Mask) {
assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE");
assert(VT.isVector() && N1.getValueType().isVector() &&
@@ -1247,7 +1247,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl,
+SDValue SelectionDAG::getConvertRndSat(EVT VT, DebugLoc dl,
SDValue Val, SDValue DTy,
SDValue STy, SDValue Rnd, SDValue Sat,
ISD::CvtCode Code) {
@@ -1269,7 +1269,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
+SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
ID.AddInteger(RegNo);
@@ -1298,7 +1298,7 @@
unsigned LabelID) {
FoldingSetNodeID ID;
SDValue Ops[] = { Root };
- AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
+ AddNodeIDNode(ID, Opcode, getVTList(EVT::Other), &Ops[0], 1);
ID.AddInteger(LabelID);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1315,7 +1315,7 @@
"SrcValue is not a pointer?");
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(EVT::Other), 0, 0);
ID.AddPointer(V);
void *IP = 0;
@@ -1337,7 +1337,7 @@
#endif
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(EVT::Other), 0, 0);
MO.Profile(ID);
void *IP = 0;
@@ -1354,8 +1354,8 @@
/// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type.
SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
- MVT OpTy = Op.getValueType();
- MVT ShTy = TLI.getShiftAmountTy();
+ EVT OpTy = Op.getValueType();
+ EVT ShTy = TLI.getShiftAmountTy();
if (OpTy == ShTy || OpTy.isVector()) return Op;
ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
@@ -1364,10 +1364,10 @@
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
/// specified value type.
-SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
+SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
unsigned ByteSize = VT.getStoreSizeInBits()/8;
- const Type *Ty = VT.getTypeForMVT();
+ const Type *Ty = VT.getTypeForEVT();
unsigned StackAlign =
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
@@ -1377,11 +1377,11 @@
/// CreateStackTemporary - Create a stack temporary suitable for holding
/// either of the specified value types.
-SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) {
+SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) {
unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
VT2.getStoreSizeInBits())/8;
- const Type *Ty1 = VT1.getTypeForMVT();
- const Type *Ty2 = VT2.getTypeForMVT();
+ const Type *Ty1 = VT1.getTypeForEVT();
+ const Type *Ty2 = VT2.getTypeForEVT();
const TargetData *TD = TLI.getTargetData();
unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1),
TD->getPrefTypeAlignment(Ty2));
@@ -1391,7 +1391,7 @@
return getFrameIndex(FrameIdx, TLI.getPointerTy());
}
-SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
+SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
// These setcc operations always fold.
switch (Cond) {
@@ -1438,7 +1438,7 @@
if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
// No compile time operations on this type yet.
- if (N1C->getValueType(0) == MVT::ppcf128)
+ if (N1C->getValueType(0) == EVT::ppcf128)
return SDValue();
APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
@@ -1727,7 +1727,7 @@
}
return;
case ISD::SIGN_EXTEND_INREG: {
- MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
unsigned EBits = EVT.getSizeInBits();
// Sign extension. Compute the demanded bits in the result that are not
@@ -1772,14 +1772,14 @@
case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.getNode())) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
- MVT VT = LD->getMemoryVT();
+ EVT VT = LD->getMemoryVT();
unsigned MemBits = VT.getSizeInBits();
KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask;
}
return;
}
case ISD::ZERO_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
APInt InMask = Mask;
@@ -1793,7 +1793,7 @@
return;
}
case ISD::SIGN_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InSignBit = APInt::getSignBit(InBits);
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
@@ -1834,7 +1834,7 @@
return;
}
case ISD::ANY_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InMask = Mask;
InMask.trunc(InBits);
@@ -1846,7 +1846,7 @@
return;
}
case ISD::TRUNCATE: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InMask = Mask;
InMask.zext(InBits);
@@ -1859,7 +1859,7 @@
break;
}
case ISD::AssertZext: {
- MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
KnownOne, Depth+1);
@@ -1978,7 +1978,7 @@
/// information. For example, immediately after an "SRA X, 2", we know that
/// the top 3 bits are all equal to each other, so we return 3.
unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
assert(VT.isInteger() && "Invalid VT!");
unsigned VTBits = VT.getSizeInBits();
unsigned Tmp, Tmp2;
@@ -2213,7 +2213,7 @@
/// element of the result of the vector shuffle.
SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N,
unsigned i) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
if (N->getMaskElt(i) < 0)
return getUNDEF(VT.getVectorElementType());
@@ -2224,7 +2224,7 @@
if (V.getOpcode() == ISD::BIT_CONVERT) {
V = V.getOperand(0);
- MVT VVT = V.getValueType();
+ EVT VVT = V.getValueType();
if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems)
return SDValue();
}
@@ -2241,7 +2241,7 @@
/// getNode - Gets or creates the specified node.
///
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
void *IP = 0;
@@ -2259,7 +2259,7 @@
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
- MVT VT, SDValue Operand) {
+ EVT VT, SDValue Operand) {
// Constant fold unary operations with an integer constant operand.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) {
const APInt &Val = C->getAPIntValue();
@@ -2276,7 +2276,7 @@
case ISD::SINT_TO_FP: {
const uint64_t zero[] = {0, 0};
// No compile time operations on this type.
- if (VT==MVT::ppcf128)
+ if (VT==EVT::ppcf128)
break;
APFloat apf = APFloat(APInt(BitWidth, 2, zero));
(void)apf.convertFromAPInt(Val,
@@ -2285,9 +2285,9 @@
return getConstantFP(apf, VT);
}
case ISD::BIT_CONVERT:
- if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
+ if (VT == EVT::f32 && C->getValueType(0) == EVT::i32)
return getConstantFP(Val.bitsToFloat(), VT);
- else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
+ else if (VT == EVT::f64 && C->getValueType(0) == EVT::i64)
return getConstantFP(Val.bitsToDouble(), VT);
break;
case ISD::BSWAP:
@@ -2304,7 +2304,7 @@
// Constant fold unary operations with a floating point constant operand.
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
APFloat V = C->getValueAPF(); // make copy
- if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
+ if (VT != EVT::ppcf128 && Operand.getValueType() != EVT::ppcf128) {
switch (Opcode) {
case ISD::FNEG:
V.changeSign();
@@ -2317,7 +2317,7 @@
bool ignored;
// This can return overflow, underflow, or inexact; we don't care.
// FIXME need to be more flexible about rounding mode.
- (void)V.convert(*MVTToAPFloatSemantics(VT),
+ (void)V.convert(*EVTToAPFloatSemantics(VT),
APFloat::rmNearestTiesToEven, &ignored);
return getConstantFP(V, VT);
}
@@ -2336,9 +2336,9 @@
return getConstant(api, VT);
}
case ISD::BIT_CONVERT:
- if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
+ if (VT == EVT::i32 && C->getValueType(0) == EVT::f32)
return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
- else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
+ else if (VT == EVT::i64 && C->getValueType(0) == EVT::f64)
return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
break;
}
@@ -2449,7 +2449,7 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) { // Don't CSE flag producing nodes
+ if (VT != EVT::Flag) { // Don't CSE flag producing nodes
FoldingSetNodeID ID;
SDValue Ops[1] = { Operand };
AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
@@ -2472,7 +2472,7 @@
}
SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode,
- MVT VT,
+ EVT VT,
ConstantSDNode *Cst1,
ConstantSDNode *Cst2) {
const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue();
@@ -2507,15 +2507,15 @@
return SDValue();
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2) {
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
switch (Opcode) {
default: break;
case ISD::TokenFactor:
- assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
- N2.getValueType() == MVT::Other && "Invalid token factor!");
+ assert(VT == EVT::Other && N1.getValueType() == EVT::Other &&
+ N2.getValueType() == EVT::Other && "Invalid token factor!");
// Fold trivial token factors.
if (N1.getOpcode() == ISD::EntryToken) return N2;
if (N2.getOpcode() == ISD::EntryToken) return N1;
@@ -2605,11 +2605,11 @@
// Always fold shifts of i1 values so the code generator doesn't need to
// handle them. Since we know the size of the shift has to be less than the
// size of the value, the shift/rotate count is guaranteed to be zero.
- if (VT == MVT::i1)
+ if (VT == EVT::i1)
return N1;
break;
case ISD::FP_ROUND_INREG: {
- MVT EVT = cast<VTSDNode>(N2)->getVT();
+ EVT EVT = cast<VTSDNode>(N2)->getVT();
assert(VT == N1.getValueType() && "Not an inreg round!");
assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
"Cannot FP_ROUND_INREG integer types");
@@ -2626,7 +2626,7 @@
break;
case ISD::AssertSext:
case ISD::AssertZext: {
- MVT EVT = cast<VTSDNode>(N2)->getVT();
+ EVT EVT = cast<VTSDNode>(N2)->getVT();
assert(VT == N1.getValueType() && "Not an inreg extend!");
assert(VT.isInteger() && EVT.isInteger() &&
"Cannot *_EXTEND_INREG FP types");
@@ -2635,7 +2635,7 @@
break;
}
case ISD::SIGN_EXTEND_INREG: {
- MVT EVT = cast<VTSDNode>(N2)->getVT();
+ EVT EVT = cast<VTSDNode>(N2)->getVT();
assert(VT == N1.getValueType() && "Not an inreg extend!");
assert(VT.isInteger() && EVT.isInteger() &&
"Cannot *_EXTEND_INREG FP types");
@@ -2673,7 +2673,7 @@
// expanding large vector constants.
if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
SDValue Elt = N1.getOperand(N2C->getZExtValue());
- MVT VEltTy = N1.getValueType().getVectorElementType();
+ EVT VEltTy = N1.getValueType().getVectorElementType();
if (Elt.getValueType() != VEltTy) {
// If the vector element type is not legal, the BUILD_VECTOR operands
// are promoted and implicitly truncated. Make that explicit here.
@@ -2746,7 +2746,7 @@
// Cannonicalize constant to RHS if commutative
std::swap(N1CFP, N2CFP);
std::swap(N1, N2);
- } else if (N2CFP && VT != MVT::ppcf128) {
+ } else if (N2CFP && VT != EVT::ppcf128) {
APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
APFloat::opStatus s;
switch (Opcode) {
@@ -2861,7 +2861,7 @@
// Memoize this node if possible.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) {
+ if (VT != EVT::Flag) {
SDValue Ops[] = { N1, N2 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
@@ -2883,7 +2883,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3) {
// Perform various simplifications.
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
@@ -2920,7 +2920,7 @@
case ISD::BRCOND:
if (N2C) {
if (N2C->getZExtValue()) // Unconditional branch
- return getNode(ISD::BR, DL, MVT::Other, N1, N3);
+ return getNode(ISD::BR, DL, EVT::Other, N1, N3);
else
return N1; // Never-taken branch
}
@@ -2938,7 +2938,7 @@
// Memoize node if it doesn't produce a flag.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) {
+ if (VT != EVT::Flag) {
SDValue Ops[] = { N1, N2, N3 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
@@ -2959,14 +2959,14 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4) {
SDValue Ops[] = { N1, N2, N3, N4 };
return getNode(Opcode, DL, VT, Ops, 4);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4, SDValue N5) {
SDValue Ops[] = { N1, N2, N3, N4, N5 };
@@ -2992,13 +2992,13 @@
ArgChains.push_back(SDValue(L, 1));
// Build a tokenfactor for all the chains.
- return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
+ return getNode(ISD::TokenFactor, Chain.getDebugLoc(), EVT::Other,
&ArgChains[0], ArgChains.size());
}
/// getMemsetValue - Vectorized representation of the memset value
/// operand.
-static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG,
+static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
DebugLoc dl) {
unsigned NumBits = VT.isVector() ?
VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
@@ -3032,7 +3032,7 @@
/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
/// used when a memcpy is turned into a memset when the source is a constant
/// string ptr.
-static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG,
+static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG,
const TargetLowering &TLI,
std::string &Str, unsigned Offset) {
// Handle vector with all elements zero.
@@ -3040,9 +3040,9 @@
if (VT.isInteger())
return DAG.getConstant(0, VT);
unsigned NumElts = VT.getVectorNumElements();
- MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
+ EVT EltVT = (VT.getVectorElementType() == EVT::f32) ? EVT::i32 : EVT::i64;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts)));
+ DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts)));
}
assert(!VT.isVector() && "Can't handle vector type here!");
@@ -3062,7 +3062,7 @@
///
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
SelectionDAG &DAG) {
- MVT VT = Base.getValueType();
+ EVT VT = Base.getValueType();
return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
VT, Base, DAG.getConstant(Offset, VT));
}
@@ -3094,7 +3094,7 @@
/// to replace the memset / memcpy is below the threshold. It also returns the
/// types of the sequence of memory ops to perform memset / memcpy.
static
-bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
+bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps,
SDValue Dst, SDValue Src,
unsigned Limit, uint64_t Size, unsigned &Align,
std::string &Str, bool &isSrcStr,
@@ -3103,23 +3103,23 @@
isSrcStr = isMemSrcFromString(Src, Str);
bool isSrcConst = isa<ConstantSDNode>(Src);
bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
- MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
- if (VT != MVT::iAny) {
+ EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
+ if (VT != EVT::iAny) {
unsigned NewAlign = (unsigned)
- TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
+ TLI.getTargetData()->getABITypeAlignment(VT.getTypeForEVT());
// If source is a string constant, this will require an unaligned load.
if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
if (Dst.getOpcode() != ISD::FrameIndex) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = MVT::iAny;
+ VT = EVT::iAny;
} else {
int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
if (MFI->isFixedObjectIndex(FI)) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = MVT::iAny;
+ VT = EVT::iAny;
} else {
// Give the stack frame object a larger alignment if needed.
if (MFI->getObjectAlignment(FI) < NewAlign)
@@ -3130,21 +3130,21 @@
}
}
- if (VT == MVT::iAny) {
+ if (VT == EVT::iAny) {
if (AllowUnalign) {
- VT = MVT::i64;
+ VT = EVT::i64;
} else {
switch (Align & 7) {
- case 0: VT = MVT::i64; break;
- case 4: VT = MVT::i32; break;
- case 2: VT = MVT::i16; break;
- default: VT = MVT::i8; break;
+ case 0: VT = EVT::i64; break;
+ case 4: VT = EVT::i32; break;
+ case 2: VT = EVT::i16; break;
+ default: VT = EVT::i8; break;
}
}
- MVT LVT = MVT::i64;
+ EVT LVT = EVT::i64;
while (!TLI.isTypeLegal(LVT))
- LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1);
+ LVT = (EVT::SimpleValueType)(LVT.getSimpleVT() - 1);
assert(LVT.isInteger());
if (VT.bitsGT(LVT))
@@ -3157,14 +3157,14 @@
while (VTSize > Size) {
// For now, only use non-vector load / store's for the left-over pieces.
if (VT.isVector()) {
- VT = MVT::i64;
+ VT = EVT::i64;
while (!TLI.isTypeLegal(VT))
- VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
VTSize = VT.getSizeInBits() / 8;
} else {
// This can result in a type that is not legal on the target, e.g.
// 1 or 2 bytes on PPC.
- VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
VTSize >>= 1;
}
}
@@ -3188,7 +3188,7 @@
// Expand memcpy to a series of load and store ops if the size operand falls
// below a certain threshold.
- std::vector<MVT> MemOps;
+ std::vector<EVT> MemOps;
uint64_t Limit = -1ULL;
if (!AlwaysInline)
Limit = TLI.getMaxStoresPerMemcpy();
@@ -3205,7 +3205,7 @@
unsigned NumMemOps = MemOps.size();
uint64_t SrcOff = 0, DstOff = 0;
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
@@ -3225,7 +3225,7 @@
// thing to do is generate a LoadExt/StoreTrunc pair. These simplify
// to Load/Store if NVT==VT.
// FIXME does the case above also need this?
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
assert(NVT.bitsGE(VT));
Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
@@ -3239,7 +3239,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3253,7 +3253,7 @@
// Expand memmove to a series of load and store ops if the size operand falls
// below a certain threshold.
- std::vector<MVT> MemOps;
+ std::vector<EVT> MemOps;
uint64_t Limit = -1ULL;
if (!AlwaysInline)
Limit = TLI.getMaxStoresPerMemmove();
@@ -3271,7 +3271,7 @@
SmallVector<SDValue, 8> OutChains;
unsigned NumMemOps = MemOps.size();
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
@@ -3282,11 +3282,11 @@
LoadChains.push_back(Value.getValue(1));
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&LoadChains[0], LoadChains.size());
OutChains.clear();
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
@@ -3297,7 +3297,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3310,7 +3310,7 @@
// Expand memset to a series of load/store ops if the size operand
// falls below a certain threshold.
- std::vector<MVT> MemOps;
+ std::vector<EVT> MemOps;
std::string Str;
bool CopyFromStr;
if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(),
@@ -3322,7 +3322,7 @@
unsigned NumMemOps = MemOps.size();
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value = getMemsetValue(Src, VT, DAG, dl);
SDValue Store = DAG.getStore(Chain, dl, Value,
@@ -3332,7 +3332,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3477,10 +3477,10 @@
Entry.Node = Dst; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend or truncate the argument to be an i32 value for the call.
- if (Src.getValueType().bitsGT(MVT::i32))
- Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
+ if (Src.getValueType().bitsGT(EVT::i32))
+ Src = getNode(ISD::TRUNCATE, dl, EVT::i32, Src);
else
- Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
+ Src = getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Src);
Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
Args.push_back(Entry);
Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
@@ -3496,7 +3496,7 @@
return CallResult.second;
}
-SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
SDValue Chain,
SDValue Ptr, SDValue Cmp,
SDValue Swp, const Value* PtrVal,
@@ -3504,12 +3504,12 @@
assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
- MVT VT = Cmp.getValueType();
+ EVT VT = Cmp.getValueType();
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(MemVT);
+ Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, MVT::Other);
+ SDVTList VTs = getVTList(VT, EVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
@@ -3525,7 +3525,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
SDValue Chain,
SDValue Ptr, SDValue Val,
const Value* PtrVal,
@@ -3543,12 +3543,12 @@
Opcode == ISD::ATOMIC_SWAP) &&
"Invalid Atomic Op");
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(MemVT);
+ Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, MVT::Other);
+ SDVTList VTs = getVTList(VT, EVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Val};
@@ -3571,7 +3571,7 @@
if (NumOps == 1)
return Ops[0];
- SmallVector<MVT, 4> VTs;
+ SmallVector<EVT, 4> VTs;
VTs.reserve(NumOps);
for (unsigned i = 0; i < NumOps; ++i)
VTs.push_back(Ops[i].getValueType());
@@ -3581,9 +3581,9 @@
SDValue
SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
- const MVT *VTs, unsigned NumVTs,
+ const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
+ EVT MemVT, const Value *srcValue, int SVOff,
unsigned Align, bool Vol,
bool ReadMem, bool WriteMem) {
return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
@@ -3594,12 +3594,12 @@
SDValue
SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
+ EVT MemVT, const Value *srcValue, int SVOff,
unsigned Align, bool Vol,
bool ReadMem, bool WriteMem) {
// Memoize the node unless it returns a flag.
MemIntrinsicSDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -3621,12 +3621,12 @@
SDValue
SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
- ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
+ ISD::LoadExtType ExtType, EVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
- const Value *SV, int SVOffset, MVT EVT,
+ const Value *SV, int SVOffset, EVT EVT,
bool isVolatile, unsigned Alignment) {
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
+ Alignment = getEVTAlignment(VT);
if (VT == EVT) {
ExtType = ISD::NON_EXTLOAD;
@@ -3651,7 +3651,7 @@
"Unindexed load with an offset!");
SDVTList VTs = Indexed ?
- getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
+ getVTList(VT, Ptr.getValueType(), EVT::Other) : getVTList(VT, EVT::Other);
SDValue Ops[] = { Chain, Ptr, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
@@ -3668,7 +3668,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
+SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset,
bool isVolatile, unsigned Alignment) {
@@ -3677,10 +3677,10 @@
SV, SVOffset, VT, isVolatile, Alignment);
}
-SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
+SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
SDValue Chain, SDValue Ptr,
const Value *SV,
- int SVOffset, MVT EVT,
+ int SVOffset, EVT EVT,
bool isVolatile, unsigned Alignment) {
SDValue Undef = getUNDEF(Ptr.getValueType());
return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
@@ -3702,12 +3702,12 @@
SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV, int SVOffset,
bool isVolatile, unsigned Alignment) {
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
+ Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(MVT::Other);
+ SDVTList VTs = getVTList(EVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
@@ -3728,9 +3728,9 @@
SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV,
- int SVOffset, MVT SVT,
+ int SVOffset, EVT SVT,
bool isVolatile, unsigned Alignment) {
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
if (VT == SVT)
return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
@@ -3740,9 +3740,9 @@
"Can't do FP-INT conversion!");
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
+ Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(MVT::Other);
+ SDVTList VTs = getVTList(EVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
@@ -3767,7 +3767,7 @@
StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
"Store is already a indexed store!");
- SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
+ SDVTList VTs = getVTList(Base.getValueType(), EVT::Other);
SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3786,14 +3786,14 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl,
+SDValue SelectionDAG::getVAArg(EVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
SDValue SV) {
SDValue Ops[] = { Chain, Ptr, SV };
- return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
+ return getNode(ISD::VAARG, dl, getVTList(VT, EVT::Other), Ops, 3);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
const SDUse *Ops, unsigned NumOps) {
switch (NumOps) {
case 0: return getNode(Opcode, DL, VT);
@@ -3809,7 +3809,7 @@
return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
const SDValue *Ops, unsigned NumOps) {
switch (NumOps) {
case 0: return getNode(Opcode, DL, VT);
@@ -3843,7 +3843,7 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) {
+ if (VT != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
void *IP = 0;
@@ -3867,14 +3867,14 @@
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
- const std::vector<MVT> &ResultTys,
+ const std::vector<EVT> &ResultTys,
const SDValue *Ops, unsigned NumOps) {
return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()),
Ops, NumOps);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
- const MVT *VTs, unsigned NumVTs,
+ const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps) {
if (NumVTs == 1)
return getNode(Opcode, DL, VTs[0], Ops, NumOps);
@@ -3895,7 +3895,7 @@
case ISD::SRL_PARTS:
case ISD::SHL_PARTS:
if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
+ cast<VTSDNode>(N3.getOperand(1))->getVT() != EVT::i1)
return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
else if (N3.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
@@ -3911,7 +3911,7 @@
// Memoize the node unless it returns a flag.
SDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -3989,17 +3989,17 @@
return getNode(Opcode, DL, VTList, Ops, 5);
}
-SDVTList SelectionDAG::getVTList(MVT VT) {
+SDVTList SelectionDAG::getVTList(EVT VT) {
return makeVTList(SDNode::getValueTypeList(VT), 1);
}
-SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) {
+SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) {
for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
E = VTList.rend(); I != E; ++I)
if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
return *I;
- MVT *Array = Allocator.Allocate<MVT>(2);
+ EVT *Array = Allocator.Allocate<EVT>(2);
Array[0] = VT1;
Array[1] = VT2;
SDVTList Result = makeVTList(Array, 2);
@@ -4007,14 +4007,14 @@
return Result;
}
-SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) {
+SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) {
for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
E = VTList.rend(); I != E; ++I)
if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
I->VTs[2] == VT3)
return *I;
- MVT *Array = Allocator.Allocate<MVT>(3);
+ EVT *Array = Allocator.Allocate<EVT>(3);
Array[0] = VT1;
Array[1] = VT2;
Array[2] = VT3;
@@ -4023,14 +4023,14 @@
return Result;
}
-SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) {
+SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) {
for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
E = VTList.rend(); I != E; ++I)
if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
I->VTs[2] == VT3 && I->VTs[3] == VT4)
return *I;
- MVT *Array = Allocator.Allocate<MVT>(3);
+ EVT *Array = Allocator.Allocate<EVT>(3);
Array[0] = VT1;
Array[1] = VT2;
Array[2] = VT3;
@@ -4040,7 +4040,7 @@
return Result;
}
-SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
+SDVTList SelectionDAG::getVTList(const EVT *VTs, unsigned NumVTs) {
switch (NumVTs) {
case 0: llvm_unreachable("Cannot have nodes without results!");
case 1: return getVTList(VTs[0]);
@@ -4064,7 +4064,7 @@
return *I;
}
- MVT *Array = Allocator.Allocate<MVT>(NumVTs);
+ EVT *Array = Allocator.Allocate<EVT>(NumVTs);
std::copy(VTs, VTs+NumVTs, Array);
SDVTList Result = makeVTList(Array, NumVTs);
VTList.push_back(Result);
@@ -4206,20 +4206,20 @@
/// machine opcode.
///
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT) {
+ EVT VT) {
SDVTList VTs = getVTList(VT);
return SelectNodeTo(N, MachineOpc, VTs, 0, 0);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDValue Op1) {
+ EVT VT, SDValue Op1) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2 };
@@ -4227,7 +4227,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4235,41 +4235,41 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, const SDValue *Ops,
+ EVT VT, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, const SDValue *Ops,
+ EVT VT1, EVT VT2, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2) {
+ EVT VT1, EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, MVT VT3, MVT VT4,
+ EVT VT1, EVT VT2, EVT VT3, EVT VT4,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1 };
@@ -4277,7 +4277,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2 };
@@ -4285,7 +4285,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4294,7 +4294,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
@@ -4309,20 +4309,20 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT) {
+ EVT VT) {
SDVTList VTs = getVTList(VT);
return MorphNodeTo(N, Opc, VTs, 0, 0);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDValue Op1) {
+ EVT VT, SDValue Op1) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1 };
return MorphNodeTo(N, Opc, VTs, Ops, 1);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2 };
@@ -4330,7 +4330,7 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4338,34 +4338,34 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, const SDValue *Ops,
+ EVT VT, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2, const SDValue *Ops,
+ EVT VT1, EVT VT2, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2) {
+ EVT VT1, EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1 };
@@ -4373,7 +4373,7 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2 };
@@ -4381,7 +4381,7 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4406,7 +4406,7 @@
unsigned NumOps) {
// If an identical node already exists, use it.
void *IP = 0;
- if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
+ if (VTs.VTs[VTs.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -4478,54 +4478,54 @@
/// Note that getTargetNode returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT) {
return getNode(~Opcode, dl, VT).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
SDValue Op1) {
return getNode(~Opcode, dl, VT, Op1).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
SDValue Op1, SDValue Op2) {
return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
SDValue Op1, SDValue Op2,
SDValue Op3) {
return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
const SDValue *Ops, unsigned NumOps) {
return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2) {
+ EVT VT1, EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Op;
return getNode(~Opcode, dl, VTs, &Op, 0).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1) {
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
return getNode(~Opcode, dl, VTs, &Op1, 1).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1,
SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2 };
return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1,
SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4533,14 +4533,14 @@
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
SDValue Ops[] = { Op1, Op2 };
@@ -4548,7 +4548,7 @@
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
@@ -4557,21 +4557,21 @@
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, MVT VT3, MVT VT4,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, EVT VT3, EVT VT4,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- const std::vector<MVT> &ResultTys,
+ const std::vector<EVT> &ResultTys,
const SDValue *Ops, unsigned NumOps) {
return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode();
}
@@ -4580,7 +4580,7 @@
/// else return NULL.
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
const SDValue *Ops, unsigned NumOps) {
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -4928,13 +4928,13 @@
}
GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA,
- MVT VT, int64_t o, unsigned char TF)
+ EVT VT, int64_t o, unsigned char TF)
: SDNode(Opc, DebugLoc::getUnknownLoc(), getSDVTList(VT)),
Offset(o), TargetFlags(TF) {
TheGlobal = const_cast<GlobalValue*>(GA);
}
-MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt,
+MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT memvt,
const Value *srcValue, int SVO,
unsigned alignment, bool vol)
: SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
@@ -4946,7 +4946,7 @@
MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
const SDValue *Ops,
- unsigned NumOps, MVT memvt, const Value *srcValue,
+ unsigned NumOps, EVT memvt, const Value *srcValue,
int SVO, unsigned alignment, bool vol)
: SDNode(Opc, dl, VTs, Ops, NumOps),
MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
@@ -4994,13 +4994,13 @@
AddNodeIDNode(ID, this);
}
-static ManagedStatic<std::set<MVT, MVT::compareRawBits> > EVTs;
-static MVT VTs[MVT::LAST_VALUETYPE];
+static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs;
+static EVT VTs[EVT::LAST_VALUETYPE];
static ManagedStatic<sys::SmartMutex<true> > VTMutex;
/// getValueTypeList - Return a pointer to the specified value type.
///
-const MVT *SDNode::getValueTypeList(MVT VT) {
+const EVT *SDNode::getValueTypeList(EVT VT) {
sys::SmartScopedLock<true> Lock(*VTMutex);
if (VT.isExtended()) {
return &(*EVTs->insert(VT).first);
@@ -5447,10 +5447,10 @@
for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
if (i) OS << ",";
- if (getValueType(i) == MVT::Other)
+ if (getValueType(i) == EVT::Other)
OS << "ch";
else
- OS << getValueType(i).getMVTString();
+ OS << getValueType(i).getEVTString();
}
OS << " = " << getOperationName(G);
}
@@ -5541,7 +5541,7 @@
else
OS << "<null:" << M->MO.getOffset() << ">";
} else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
- OS << ":" << N->getVT().getMVTString();
+ OS << ":" << N->getVT().getEVTString();
}
else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
const Value *SrcValue = LD->getSrcValue();
@@ -5561,7 +5561,7 @@
case ISD::ZEXTLOAD: OS << " <zext "; break;
}
if (doExt)
- OS << LD->getMemoryVT().getMVTString() << ">";
+ OS << LD->getMemoryVT().getEVTString() << ">";
const char *AM = getIndexedModeName(LD->getAddressingMode());
if (*AM)
@@ -5580,7 +5580,7 @@
OS << ":" << SrcOffset << ">";
if (ST->isTruncatingStore())
- OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">";
+ OS << " <trunc " << ST->getMemoryVT().getEVTString() << ">";
const char *AM = getIndexedModeName(ST->getAddressingMode());
if (*AM)
@@ -5702,7 +5702,7 @@
unsigned &SplatBitSize,
bool &HasAnyUndefs,
unsigned MinSplatBits) {
- MVT VT = getValueType(0);
+ EVT VT = getValueType(0);
assert(VT.isVector() && "Expected a vector type");
unsigned sz = VT.getSizeInBits();
if (MinSplatBits > sz)
@@ -5760,7 +5760,7 @@
return true;
}
-bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
+bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) {
// Find the first non-undef value in the shuffle mask.
unsigned i, e;
for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Aug 10 17:56:29 2009
@@ -106,14 +106,14 @@
}
/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
-/// MVTs that represent all the individual underlying
+/// EVTs that represent all the individual underlying
/// non-aggregate types that comprise it.
///
/// If Offsets is non-null, it points to a vector to be filled in
/// with the in-memory offsets of each of the individual values.
///
static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
- SmallVectorImpl<MVT> &ValueVTs,
+ SmallVectorImpl<EVT> &ValueVTs,
SmallVectorImpl<uint64_t> *Offsets = 0,
uint64_t StartingOffset = 0) {
// Given a struct type, recursively traverse the elements.
@@ -139,7 +139,7 @@
// Interpret void as zero return values.
if (Ty == Type::VoidTy)
return;
- // Base case: we can get an MVT for this LLVM IR type.
+ // Base case: we can get an EVT for this LLVM IR type.
ValueVTs.push_back(TLI.getValueType(Ty));
if (Offsets)
Offsets->push_back(StartingOffset);
@@ -163,7 +163,7 @@
/// ValueVTs - The value types of the values, which may not be legal, and
/// may need be promoted or synthesized from one or more registers.
///
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
/// RegVTs - The value types of the registers. This is the same size as
/// ValueVTs and it records, for each value, what the type of the assigned
@@ -174,7 +174,7 @@
/// getRegisterType member function, however when with physical registers
/// it is necessary to have a separate record of the types.
///
- SmallVector<MVT, 4> RegVTs;
+ SmallVector<EVT, 4> RegVTs;
/// Regs - This list holds the registers assigned to the values.
/// Each legal or promoted value requires one register, and each
@@ -186,21 +186,21 @@
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> ®s,
- MVT regvt, MVT valuevt)
+ EVT regvt, EVT valuevt)
: TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> ®s,
- const SmallVector<MVT, 4> ®vts,
- const SmallVector<MVT, 4> &valuevts)
+ const SmallVector<EVT, 4> ®vts,
+ const SmallVector<EVT, 4> &valuevts)
: TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
unsigned Reg, const Type *Ty) : TLI(&tli) {
ComputeValueVTs(tli, Ty, ValueVTs);
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = TLI->getRegisterType(ValueVT);
+ EVT RegisterVT = TLI->getRegisterType(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i)
Regs.push_back(Reg + i);
RegVTs.push_back(RegisterVT);
@@ -354,10 +354,10 @@
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
- MVT VT = ValueVTs[vti];
+ EVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(VT);
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
for (unsigned i = 0; i != NumRegisters; ++i)
@@ -368,7 +368,7 @@
}
}
-unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
+unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
@@ -380,13 +380,13 @@
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, V->getType(), ValueVTs);
unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
- MVT RegisterVT = TLI.getRegisterType(ValueVT);
+ EVT ValueVT = ValueVTs[Value];
+ EVT RegisterVT = TLI.getRegisterType(ValueVT);
unsigned NumRegs = TLI.getNumRegisters(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
@@ -404,7 +404,7 @@
/// (ISD::AssertSext).
static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
const SDValue *Parts,
- unsigned NumParts, MVT PartVT, MVT ValueVT,
+ unsigned NumParts, EVT PartVT, EVT ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -420,11 +420,11 @@
unsigned RoundParts = NumParts & (NumParts - 1) ?
1 << Log2_32(NumParts) : NumParts;
unsigned RoundBits = PartBits * RoundParts;
- MVT RoundVT = RoundBits == ValueBits ?
- ValueVT : MVT::getIntegerVT(RoundBits);
+ EVT RoundVT = RoundBits == ValueBits ?
+ ValueVT : EVT::getIntegerVT(RoundBits);
SDValue Lo, Hi;
- MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
+ EVT HalfVT = EVT::getIntegerVT(RoundBits/2);
if (RoundParts > 2) {
Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
@@ -441,7 +441,7 @@
if (RoundParts < NumParts) {
// Assemble the trailing non-power-of-2 part.
unsigned OddParts = NumParts - RoundParts;
- MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
+ EVT OddVT = EVT::getIntegerVT(OddParts * PartBits);
Hi = getCopyFromParts(DAG, dl,
Parts+RoundParts, OddParts, PartVT, OddVT);
@@ -449,7 +449,7 @@
Lo = Val;
if (TLI.isBigEndian())
std::swap(Lo, Hi);
- MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
+ EVT TotalVT = EVT::getIntegerVT(NumParts * PartBits);
Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
DAG.getConstant(Lo.getValueType().getSizeInBits(),
@@ -459,7 +459,7 @@
}
} else if (ValueVT.isVector()) {
// Handle a multi-element vector.
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs =
TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
@@ -496,11 +496,11 @@
ValueVT, &Ops[0], NumIntermediates);
} else if (PartVT.isFloatingPoint()) {
// FP split into multiple FP parts (for ppcf128)
- assert(ValueVT == MVT(MVT::ppcf128) && PartVT == MVT(MVT::f64) &&
+ assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) &&
"Unexpected split");
SDValue Lo, Hi;
- Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[0]);
- Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[1]);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]);
+ Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
@@ -508,7 +508,7 @@
// FP split into integer parts (soft fp)
assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split");
- MVT IntVT = MVT::getIntegerVT(ValueVT.getSizeInBits());
+ EVT IntVT = EVT::getIntegerVT(ValueVT.getSizeInBits());
Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
}
}
@@ -565,11 +565,11 @@
/// split into legal parts. If the parts contain more bits than Val, then, for
/// integers, ExtendKind can be used to specify how to generate the extra bits.
static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
- SDValue *Parts, unsigned NumParts, MVT PartVT,
+ SDValue *Parts, unsigned NumParts, EVT PartVT,
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- MVT PtrVT = TLI.getPointerTy();
- MVT ValueVT = Val.getValueType();
+ EVT PtrVT = TLI.getPointerTy();
+ EVT ValueVT = Val.getValueType();
unsigned PartBits = PartVT.getSizeInBits();
unsigned OrigNumParts = NumParts;
assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
@@ -590,7 +590,7 @@
assert(NumParts == 1 && "Do not know what to promote to!");
Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
} else if (PartVT.isInteger() && ValueVT.isInteger()) {
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
} else {
llvm_unreachable("Unknown mismatch!");
@@ -602,7 +602,7 @@
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
// If the parts cover less bits than value has, truncate the value.
if (PartVT.isInteger() && ValueVT.isInteger()) {
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
} else {
llvm_unreachable("Unknown mismatch!");
@@ -636,19 +636,19 @@
// The odd parts were reversed by getCopyToParts - unreverse them.
std::reverse(Parts + RoundParts, Parts + NumParts);
NumParts = RoundParts;
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
}
// The number of parts is a power of 2. Repeatedly bisect the value using
// EXTRACT_ELEMENT.
Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::getIntegerVT(ValueVT.getSizeInBits()),
+ EVT::getIntegerVT(ValueVT.getSizeInBits()),
Val);
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
for (unsigned i = 0; i < NumParts; i += StepSize) {
unsigned ThisBits = StepSize * PartBits / 2;
- MVT ThisVT = MVT::getIntegerVT (ThisBits);
+ EVT ThisVT = EVT::getIntegerVT (ThisBits);
SDValue &Part0 = Parts[i];
SDValue &Part1 = Parts[i+StepSize/2];
@@ -694,7 +694,7 @@
}
// Handle a multi-element vector.
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs = TLI
.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
@@ -774,7 +774,7 @@
}
// Otherwise, we have to make a token factor node.
- SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
@@ -804,7 +804,7 @@
PendingExports.push_back(Root);
}
- Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&PendingExports[0],
PendingExports.size());
PendingExports.clear();
@@ -833,7 +833,7 @@
if (N.getNode()) return N;
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
- MVT VT = TLI.getValueType(V->getType(), true);
+ EVT VT = TLI.getValueType(V->getType(), true);
if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
return N = DAG.getConstant(*CI, VT);
@@ -873,14 +873,14 @@
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
"Unknown struct or array constant!");
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, C->getType(), ValueVTs);
unsigned NumElts = ValueVTs.size();
if (NumElts == 0)
return SDValue(); // empty struct
SmallVector<SDValue, 4> Constants(NumElts);
for (unsigned i = 0; i != NumElts; ++i) {
- MVT EltVT = ValueVTs[i];
+ EVT EltVT = ValueVTs[i];
if (isa<UndefValue>(C))
Constants[i] = DAG.getUNDEF(EltVT);
else if (EltVT.isFloatingPoint())
@@ -902,7 +902,7 @@
Ops.push_back(getValue(CP->getOperand(i)));
} else {
assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
- MVT EltVT = TLI.getValueType(VecTy->getElementType());
+ EVT EltVT = TLI.getValueType(VecTy->getElementType());
SDValue Op;
if (EltVT.isFloatingPoint())
@@ -939,14 +939,14 @@
SDValue Chain = getControlRoot();
SmallVector<ISD::OutputArg, 8> Outs;
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues == 0) continue;
SDValue RetOp = getValue(I.getOperand(i));
for (unsigned j = 0, f = NumValues; j != f; ++j) {
- MVT VT = ValueVTs[j];
+ EVT VT = ValueVTs[j];
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@@ -961,13 +961,13 @@
// conventions. The frontend should mark functions whose return values
// require promoting with signext or zeroext attributes.
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
- MVT MinVT = TLI.getRegisterType(MVT::i32);
+ EVT MinVT = TLI.getRegisterType(EVT::i32);
if (VT.bitsLT(MinVT))
VT = MinVT;
}
unsigned NumParts = TLI.getNumRegisters(VT);
- MVT PartVT = TLI.getRegisterType(VT);
+ EVT PartVT = TLI.getRegisterType(VT);
SmallVector<SDValue, 4> Parts(NumParts);
getCopyToParts(DAG, getCurDebugLoc(),
SDValue(RetOp.getNode(), RetOp.getResNo() + j),
@@ -995,7 +995,7 @@
Outs, getCurDebugLoc(), DAG);
// Verify that the target's LowerReturn behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
"LowerReturn didn't return a valid chain!");
// Update the DAG with the new chain value resulting from return lowering.
@@ -1250,7 +1250,7 @@
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
return;
}
@@ -1334,7 +1334,7 @@
SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
} else
- Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+ Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
} else {
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
@@ -1342,15 +1342,15 @@
const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
SDValue CmpOp = getValue(CB.CmpMHS);
- MVT VT = CmpOp.getValueType();
+ EVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
- Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
+ Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT),
ISD::SETLE);
} else {
SDValue SUB = DAG.getNode(ISD::SUB, dl,
VT, CmpOp, DAG.getConstant(Low, VT));
- Cond = DAG.getSetCC(dl, MVT::i1, SUB,
+ Cond = DAG.getSetCC(dl, EVT::i1, SUB,
DAG.getConstant(High-Low, VT), ISD::SETULE);
}
}
@@ -1374,7 +1374,7 @@
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
}
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
- MVT::Other, getControlRoot(), Cond,
+ EVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB));
// If the branch was constant folded, fix up the CFG.
@@ -1389,7 +1389,7 @@
if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond,
DAG.getBasicBlock(CB.FalseBB)));
}
}
@@ -1398,12 +1398,12 @@
void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
// Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!");
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
- MVT::Other, Index.getValue(1),
+ EVT::Other, Index.getValue(1),
Table, Index));
}
@@ -1415,7 +1415,7 @@
// conditional branch to default mbb if the result is greater than the
// difference between smallest and largest cases.
SDValue SwitchOp = getValue(JTH.SValue);
- MVT VT = SwitchOp.getValueType();
+ EVT VT = SwitchOp.getValueType();
SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
DAG.getConstant(JTH.First, VT));
@@ -1452,13 +1452,13 @@
NextBlock = BBI;
SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, CopyTo, CMP,
+ EVT::Other, CopyTo, CMP,
DAG.getBasicBlock(JT.Default));
if (JT.MBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond,
DAG.getBasicBlock(JT.MBB)));
}
@@ -1467,7 +1467,7 @@
void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
// Subtract the minimum value
SDValue SwitchOp = getValue(B.SValue);
- MVT VT = SwitchOp.getValueType();
+ EVT VT = SwitchOp.getValueType();
SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
DAG.getConstant(B.First, VT));
@@ -1502,13 +1502,13 @@
CurMBB->addSuccessor(MBB);
SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, CopyTo, RangeCmp,
+ EVT::Other, CopyTo, RangeCmp,
DAG.getBasicBlock(B.Default));
if (MBB == NextBlock)
DAG.setRoot(BrRange);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo,
DAG.getBasicBlock(MBB)));
}
@@ -1537,7 +1537,7 @@
CurMBB->addSuccessor(NextMBB);
SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
AndCmp, DAG.getBasicBlock(B.TargetBB));
// Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1550,7 +1550,7 @@
if (NextMBB == NextBlock)
DAG.setRoot(BrAnd);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd,
DAG.getBasicBlock(NextMBB)));
}
@@ -1575,7 +1575,7 @@
// Drop into normal successor.
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
@@ -1669,8 +1669,8 @@
static inline bool areJTsAllowed(const TargetLowering &TLI) {
return !DisableJumpTables &&
- (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
- TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
+ (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) ||
+ TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other));
}
static APInt ComputeRange(const APInt &First, const APInt &Last) {
@@ -1911,7 +1911,7 @@
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default){
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned IntPtrBits = PTy.getSizeInBits();
Case& FrontCase = *CR.Range.first;
@@ -2096,7 +2096,7 @@
CurMBB->addSuccessor(Default);
if (Default != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Default)));
return;
}
@@ -2188,8 +2188,8 @@
if (!isa<VectorType>(I.getType()) &&
Op2.getValueType() != TLI.getShiftAmountTy()) {
// If the operand is smaller than the shift count type, promote it.
- MVT PTy = TLI.getPointerTy();
- MVT STy = TLI.getShiftAmountTy();
+ EVT PTy = TLI.getPointerTy();
+ EVT STy = TLI.getShiftAmountTy();
if (STy.bitsGT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
TLI.getShiftAmountTy(), Op2);
@@ -2226,7 +2226,7 @@
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = getICmpCondCode(predicate);
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
}
@@ -2239,12 +2239,12 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Condition = getFCmpCondCode(predicate);
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
}
void SelectionDAGLowering::visitSelect(User &I) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues != 0) {
@@ -2269,7 +2269,7 @@
void SelectionDAGLowering::visitTrunc(User &I) {
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
}
@@ -2277,7 +2277,7 @@
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
}
@@ -2285,14 +2285,14 @@
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// SExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPTrunc(User &I) {
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
DestVT, N, DAG.getIntPtrConstant(0)));
}
@@ -2300,35 +2300,35 @@
void SelectionDAGLowering::visitFPExt(User &I){
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPToUI(User &I) {
// FPToUI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPToSI(User &I) {
// FPToSI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitUIToFP(User &I) {
// UIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitSIToFP(User &I){
// SIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
}
@@ -2336,8 +2336,8 @@
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
- MVT SrcVT = N.getValueType();
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT SrcVT = N.getValueType();
+ EVT DestVT = TLI.getValueType(I.getType());
SDValue Result;
if (DestVT.bitsLT(SrcVT))
Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
@@ -2351,8 +2351,8 @@
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
- MVT SrcVT = N.getValueType();
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT SrcVT = N.getValueType();
+ EVT DestVT = TLI.getValueType(I.getType());
if (DestVT.bitsLT(SrcVT))
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
else
@@ -2363,7 +2363,7 @@
void SelectionDAGLowering::visitBitCast(User &I) {
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
// BitCast assures us that source and destination are the same size so this
// is either a BIT_CONVERT or a no-op.
@@ -2424,8 +2424,8 @@
Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
}
- MVT VT = TLI.getValueType(I.getType());
- MVT SrcVT = Src1.getValueType();
+ EVT VT = TLI.getValueType(I.getType());
+ EVT SrcVT = Src1.getValueType();
unsigned SrcNumElts = SrcVT.getVectorNumElements();
if (SrcNumElts == MaskNumElts) {
@@ -2559,8 +2559,8 @@
// We can't use either concat vectors or extract subvectors so fall back to
// replacing the shuffle with extract and build vector.
// to insert and build vector.
- MVT EltVT = VT.getVectorElementType();
- MVT PtrVT = TLI.getPointerTy();
+ EVT EltVT = VT.getVectorElementType();
+ EVT PtrVT = TLI.getPointerTy();
SmallVector<SDValue,8> Ops;
for (unsigned i = 0; i != MaskNumElts; ++i) {
if (Mask[i] < 0) {
@@ -2591,9 +2591,9 @@
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
I.idx_begin(), I.idx_end());
- SmallVector<MVT, 4> AggValueVTs;
+ SmallVector<EVT, 4> AggValueVTs;
ComputeValueVTs(TLI, AggTy, AggValueVTs);
- SmallVector<MVT, 4> ValValueVTs;
+ SmallVector<EVT, 4> ValValueVTs;
ComputeValueVTs(TLI, ValTy, ValValueVTs);
unsigned NumAggValues = AggValueVTs.size();
@@ -2630,7 +2630,7 @@
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
I.idx_begin(), I.idx_end());
- SmallVector<MVT, 4> ValValueVTs;
+ SmallVector<EVT, 4> ValValueVTs;
ComputeValueVTs(TLI, ValTy, ValValueVTs);
unsigned NumValValues = ValValueVTs.size();
@@ -2675,12 +2675,12 @@
uint64_t Offs =
TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
SDValue OffsVal;
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned PtrBits = PTy.getSizeInBits();
if (PtrBits < 64) {
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(),
- DAG.getConstant(Offs, MVT::i64));
+ DAG.getConstant(Offs, EVT::i64));
} else
OffsVal = DAG.getIntPtrConstant(Offs);
N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
@@ -2743,7 +2743,7 @@
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
IntPtr, AllocSize);
@@ -2770,7 +2770,7 @@
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
- SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
+ SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other);
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
VTs, Ops, 3);
setValue(&I, DSA);
@@ -2789,7 +2789,7 @@
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
SmallVector<uint64_t, 4> Offsets;
ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
unsigned NumValues = ValueVTs.size();
@@ -2812,7 +2812,7 @@
SmallVector<SDValue, 4> Values(NumValues);
SmallVector<SDValue, 4> Chains(NumValues);
- MVT PtrVT = Ptr.getValueType();
+ EVT PtrVT = Ptr.getValueType();
for (unsigned i = 0; i != NumValues; ++i) {
SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
DAG.getNode(ISD::ADD, getCurDebugLoc(),
@@ -2826,7 +2826,7 @@
if (!ConstantMemory) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- MVT::Other,
+ EVT::Other,
&Chains[0], NumValues);
if (isVolatile)
DAG.setRoot(Chain);
@@ -2844,7 +2844,7 @@
Value *SrcV = I.getOperand(0);
Value *PtrV = I.getOperand(1);
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
SmallVector<uint64_t, 4> Offsets;
ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
unsigned NumValues = ValueVTs.size();
@@ -2859,7 +2859,7 @@
SDValue Root = getRoot();
SmallVector<SDValue, 4> Chains(NumValues);
- MVT PtrVT = Ptr.getValueType();
+ EVT PtrVT = Ptr.getValueType();
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
for (unsigned i = 0; i != NumValues; ++i)
@@ -2872,7 +2872,7 @@
isVolatile, Alignment);
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- MVT::Other, &Chains[0], NumValues));
+ EVT::Other, &Chains[0], NumValues));
}
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
@@ -2909,7 +2909,7 @@
Ops.push_back(Op);
}
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs);
#ifndef NDEBUG
for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
@@ -2918,7 +2918,7 @@
}
#endif // NDEBUG
if (HasChain)
- ValueVTs.push_back(MVT::Other);
+ ValueVTs.push_back(EVT::Other);
SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
@@ -2951,7 +2951,7 @@
}
if (I.getType() != Type::VoidTy) {
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
- MVT VT = TLI.getValueType(PTy);
+ EVT VT = TLI.getValueType(PTy);
Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
}
setValue(&I, Result);
@@ -3033,11 +3033,11 @@
/// where Op is the hexidecimal representation of floating point value.
static SDValue
GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
- SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
- DAG.getConstant(0x007fffff, MVT::i32));
- SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
- DAG.getConstant(0x3f800000, MVT::i32));
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
+ SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
+ DAG.getConstant(0x007fffff, EVT::i32));
+ SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1,
+ DAG.getConstant(0x3f800000, EVT::i32));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2);
}
/// GetExponent - Get the exponent:
@@ -3048,19 +3048,19 @@
static SDValue
GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
DebugLoc dl) {
- SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
- DAG.getConstant(0x7f800000, MVT::i32));
- SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
+ SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
+ DAG.getConstant(0x7f800000, EVT::i32));
+ SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0,
DAG.getConstant(23, TLI.getPointerTy()));
- SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
- DAG.getConstant(127, MVT::i32));
- return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
+ SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1,
+ DAG.getConstant(127, EVT::i32));
+ return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2);
}
/// getF32Constant - Get 32-bit floating point constant.
static SDValue
getF32Constant(SelectionDAG &DAG, unsigned Flt) {
- return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
+ return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32);
}
/// Inlined utility function to implement binary input atomic intrinsics for
@@ -3087,7 +3087,7 @@
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
- SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
+ SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1);
SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
setValue(&I, Result);
@@ -3101,7 +3101,7 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
@@ -3110,16 +3110,16 @@
//
// #define LOG2OFe 1.4426950f
// IntegerPartOfX = ((int32_t)(X * LOG2OFe));
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
getF32Constant(DAG, 0x3fb8aa3b));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
// FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3130,20 +3130,20 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5);
// Add the exponent into the result in integer domain.
- SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3153,23 +3153,23 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// 0.000107046256 error, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7);
// Add the exponent into the result in integer domain.
- SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3182,33 +3182,33 @@
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
//
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::i32, t13);
+ EVT::i32, t13);
// Add the exponent into the result in integer domain.
- SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14);
}
} else {
// No special expansion.
@@ -3227,14 +3227,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Scale the exponent by log(2) [0.69314718f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
getF32Constant(DAG, 0x3f317218));
// Get the significand and build it into a floating-point number with
@@ -3249,16 +3249,16 @@
// (1.4034025f - 0.23903021f * x) * x;
//
// error 0.0034276066, which is better than 8 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbe74c456));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3fb3a2b1));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f949a29));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3269,22 +3269,22 @@
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
//
// error 0.000061011436, which is 14 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbd67b6d6));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3ee4f4b8));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fbc278b));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40348e95));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3fdef31a));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3297,28 +3297,28 @@
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
//
// error 0.0000023660568, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbc91e5ac));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e4350aa));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f60d3e3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x4011cdf0));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x406cfd1c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x408797cb));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
getF32Constant(DAG, 0x4006dcab));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
}
} else {
// No special expansion.
@@ -3337,10 +3337,10 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Get the exponent.
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
@@ -3357,16 +3357,16 @@
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
//
// error 0.0049451742, which is more than 7 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbeb08fe0));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x40019463));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fd6633d));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3377,22 +3377,22 @@
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
//
// error 0.0000876136000, which is better than 13 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbda7262e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3f25280b));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x4007b923));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40823e2f));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x4020d29c));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3406,28 +3406,28 @@
// 0.25691327e-1f * x) * x) * x) * x) * x) * x;
//
// error 0.0000018516, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbcd2769e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e8ce0b9));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fa22ae7));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40525723));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x40aaf200));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x40c39dad));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
getF32Constant(DAG, 0x4042902c));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
}
} else {
// No special expansion.
@@ -3446,14 +3446,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Scale the exponent by log10(2) [0.30102999f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
getF32Constant(DAG, 0x3e9a209a));
// Get the significand and build it into a floating-point number with
@@ -3468,16 +3468,16 @@
// (0.60948995f - 0.10380950f * x) * x;
//
// error 0.0014886165, which is 6 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbdd49a13));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3f1c0789));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f011300));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3487,19 +3487,19 @@
// (-0.31664806f + 0.47637168e-1f * x) * x) * x;
//
// error 0.00019228036, which is better than 12 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3d431f31));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3ea21fb2));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f6ae232));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f25f7c3));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3511,25 +3511,25 @@
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
//
// error 0.0000037995730, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3c5d51ce));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e00685a));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3efb6798));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f88d192));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3fc4316c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3f57ce70));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
}
} else {
// No special expansion.
@@ -3548,18 +3548,18 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3570,19 +3570,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3592,22 +3592,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3619,31 +3619,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3664,8 +3664,8 @@
DebugLoc dl = getCurDebugLoc();
bool IsExp10 = false;
- if (getValue(Val).getValueType() == MVT::f32 &&
- getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
+ if (getValue(Val).getValueType() == EVT::f32 &&
+ getValue(I.getOperand(2)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
@@ -3683,16 +3683,16 @@
//
// #define LOG2OF10 3.3219281f
// IntegerPartOfX = (int32_t)(x * LOG2OF10);
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
getF32Constant(DAG, 0x40549a78));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3703,19 +3703,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3725,22 +3725,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3752,31 +3752,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3973,14 +3973,14 @@
return 0;
Value *Variable = DI.getVariable();
- DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
+ DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(),
getValue(DI.getAddress()), getValue(Variable)));
return 0;
}
case Intrinsic::eh_exception: {
// Insert the EXCEPTIONADDR instruction.
assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
- SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other);
SDValue Ops[1];
Ops[0] = DAG.getRoot();
SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
@@ -3992,8 +3992,8 @@
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
if (CurMBB->isLandingPad())
@@ -4008,7 +4008,7 @@
}
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(VT, MVT::Other);
+ SDVTList VTs = DAG.getVTList(VT, EVT::Other);
SDValue Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
@@ -4025,8 +4025,8 @@
case Intrinsic::eh_typeid_for_i32:
case Intrinsic::eh_typeid_for_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
// Find the type id for the given typeinfo.
@@ -4047,7 +4047,7 @@
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
MMI->setCallsEHReturn(true);
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
- MVT::Other,
+ EVT::Other,
getControlRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
@@ -4064,7 +4064,7 @@
return 0;
case Intrinsic::eh_dwarf_cfa: {
- MVT VT = getValue(I.getOperand(1)).getValueType();
+ EVT VT = getValue(I.getOperand(1)).getValueType();
SDValue CfaArg;
if (VT.bitsGT(TLI.getPointerTy()))
CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
@@ -4109,7 +4109,7 @@
case Intrinsic::convertus: Code = ISD::CVT_US; break;
case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
}
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
Value* Op1 = I.getOperand(1);
setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
DAG.getValueType(DestVT),
@@ -4161,13 +4161,13 @@
return 0;
case Intrinsic::pcmarker: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
- DAG.getVTList(MVT::i64, MVT::Other),
+ DAG.getVTList(EVT::i64, EVT::Other),
&Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
@@ -4180,21 +4180,21 @@
return 0;
case Intrinsic::cttz: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctlz: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctpop: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
setValue(&I, result);
return 0;
@@ -4202,21 +4202,21 @@
case Intrinsic::stacksave: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
- DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
+ DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
}
case Intrinsic::stackrestore: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::stackprotector: {
// Emit code into the DAG to store the stack guard onto the stack.
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
- MVT PtrTy = TLI.getPointerTy();
+ EVT PtrTy = TLI.getPointerTy();
SDValue Src = getValue(I.getOperand(1)); // The guard's value.
AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
@@ -4250,7 +4250,7 @@
Ops[5] = DAG.getSrcValue(F);
SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
- DAG.getVTList(TLI.getPointerTy(), MVT::Other),
+ DAG.getVTList(TLI.getPointerTy(), EVT::Other),
Ops, 6);
setValue(&I, Tmp);
@@ -4274,12 +4274,12 @@
return 0;
case Intrinsic::flt_rounds: {
- setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
+ setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32));
return 0;
}
case Intrinsic::trap: {
- DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
+ DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot()));
return 0;
}
@@ -4302,7 +4302,7 @@
Ops[1] = getValue(I.getOperand(1));
Ops[2] = getValue(I.getOperand(2));
Ops[3] = getValue(I.getOperand(3));
- DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
+ DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4));
return 0;
}
@@ -4312,7 +4312,7 @@
for (int x = 1; x < 6; ++x)
Ops[x] = getValue(I.getOperand(x));
- DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
+ DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6));
return 0;
}
case Intrinsic::atomic_cmp_swap: {
@@ -4599,9 +4599,9 @@
SmallVector<SDValue, 8> Parts;
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
// Copy the legal parts from the registers.
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
Parts.resize(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i) {
@@ -4630,25 +4630,25 @@
// FIXME: We capture more information than the dag can represent. For
// now, just use the tightest assertzext/assertsext possible.
bool isSExt = true;
- MVT FromVT(MVT::Other);
+ EVT FromVT(EVT::Other);
if (NumSignBits == RegSize)
- isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
+ isSExt = true, FromVT = EVT::i1; // ASSERT SEXT 1
else if (NumZeroBits >= RegSize-1)
- isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
+ isSExt = false, FromVT = EVT::i1; // ASSERT ZEXT 1
else if (NumSignBits > RegSize-8)
- isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
+ isSExt = true, FromVT = EVT::i8; // ASSERT SEXT 8
else if (NumZeroBits >= RegSize-8)
- isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
+ isSExt = false, FromVT = EVT::i8; // ASSERT ZEXT 8
else if (NumSignBits > RegSize-16)
- isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
+ isSExt = true, FromVT = EVT::i16; // ASSERT SEXT 16
else if (NumZeroBits >= RegSize-16)
- isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
+ isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16
else if (NumSignBits > RegSize-32)
- isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
+ isSExt = true, FromVT = EVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-32)
- isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
+ isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32
- if (FromVT != MVT::Other) {
+ if (FromVT != EVT::Other) {
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
RegisterVT, P, DAG.getValueType(FromVT));
@@ -4680,9 +4680,9 @@
unsigned NumRegs = Regs.size();
SmallVector<SDValue, 8> Parts(NumRegs);
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumParts = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
&Parts[Part], NumParts, RegisterVT);
@@ -4715,7 +4715,7 @@
// = op c3, ..., f2
Chain = Chains[NumRegs-1];
else
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs);
}
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
@@ -4725,7 +4725,7 @@
bool HasMatching,unsigned MatchingIdx,
SelectionDAG &DAG,
std::vector<SDValue> &Ops) const {
- MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
unsigned Flag = Code | (Regs.size() << 3);
if (HasMatching)
@@ -4733,7 +4733,7 @@
Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
for (unsigned i = 0; i != NumRegs; ++i) {
assert(Reg < Regs.size() && "Mismatch in # registers expected");
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
@@ -4748,11 +4748,11 @@
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI,
const TargetRegisterInfo *TRI) {
- MVT FoundVT = MVT::Other;
+ EVT FoundVT = EVT::Other;
const TargetRegisterClass *FoundRC = 0;
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
E = TRI->regclass_end(); RCI != E; ++RCI) {
- MVT ThisVT = MVT::Other;
+ EVT ThisVT = EVT::Other;
const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we
@@ -4763,14 +4763,14 @@
// If we have already found this register in a different register class,
// choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
- if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
+ if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) {
ThisVT = *I;
break;
}
}
}
- if (ThisVT == MVT::Other) continue;
+ if (ThisVT == EVT::Other) continue;
// NOTE: This isn't ideal. In particular, this might allocate the
// frame pointer in functions that need it (due to them not being taken
@@ -4825,12 +4825,12 @@
}
}
- /// getCallOperandValMVT - Return the MVT of the Value* that this operand
+ /// getCallOperandValEVT - Return the EVT of the Value* that this operand
/// corresponds to. If there is no Value* for this operand, it returns
- /// MVT::Other.
- MVT getCallOperandValMVT(const TargetLowering &TLI,
+ /// EVT::Other.
+ EVT getCallOperandValEVT(const TargetLowering &TLI,
const TargetData *TD) const {
- if (CallOperandVal == 0) return MVT::Other;
+ if (CallOperandVal == 0) return EVT::Other;
if (isa<BasicBlock>(CallOperandVal))
return TLI.getPointerTy();
@@ -4923,16 +4923,16 @@
OpInfo.ConstraintVT);
unsigned NumRegs = 1;
- if (OpInfo.ConstraintVT != MVT::Other) {
+ if (OpInfo.ConstraintVT != EVT::Other) {
// If this is a FP input in an integer register (or visa versa) insert a bit
// cast of the input value. More generally, handle any case where the input
// value disagrees with the register class we plan to stick this in.
if (OpInfo.Type == InlineAsm::isInput &&
PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
- // Try to convert to the first MVT that the reg class contains. If the
+ // Try to convert to the first EVT that the reg class contains. If the
// types are identical size, use a bitcast to convert (e.g. two differing
// vector types).
- MVT RegVT = *PhysReg.second->vt_begin();
+ EVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
RegVT, OpInfo.CallOperand);
@@ -4942,7 +4942,7 @@
// bitcast to the corresponding integer type. This turns an f64 value
// into i64, which can be passed with two i32 values on a 32-bit
// machine.
- RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
+ RegVT = EVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT;
@@ -4952,14 +4952,14 @@
NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
}
- MVT RegVT;
- MVT ValueVT = OpInfo.ConstraintVT;
+ EVT RegVT;
+ EVT ValueVT = OpInfo.ConstraintVT;
// If this is a constraint for a specific physical register, like {r17},
// assign it now.
if (unsigned AssignedReg = PhysReg.first) {
const TargetRegisterClass *RC = PhysReg.second;
- if (OpInfo.ConstraintVT == MVT::Other)
+ if (OpInfo.ConstraintVT == EVT::Other)
ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user
@@ -4993,7 +4993,7 @@
// for this reference.
if (const TargetRegisterClass *RC = PhysReg.second) {
RegVT = *RC->vt_begin();
- if (OpInfo.ConstraintVT == MVT::Other)
+ if (OpInfo.ConstraintVT == EVT::Other)
ValueVT = RegVT;
// Create the appropriate number of virtual registers.
@@ -5107,7 +5107,7 @@
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
- MVT OpVT = MVT::Other;
+ EVT OpVT = EVT::Other;
// Compute the value type for each operand.
switch (OpInfo.Type) {
@@ -5149,7 +5149,7 @@
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
}
- OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
+ OpVT = OpInfo.getCallOperandValEVT(TLI, TD);
}
OpInfo.ConstraintVT = OpVT;
@@ -5243,7 +5243,7 @@
std::vector<SDValue> AsmNodeOperands;
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
AsmNodeOperands.push_back(
- DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
+ DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other));
// Loop over all of the inputs, copying the operand values into the
@@ -5336,7 +5336,7 @@
RegsForValue MatchedRegs;
MatchedRegs.TLI = &TLI;
MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
- MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
+ EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
MatchedRegs.RegVTs.push_back(RegVT);
MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
@@ -5431,7 +5431,7 @@
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
- DAG.getVTList(MVT::Other, MVT::Flag),
+ DAG.getVTList(EVT::Other, EVT::Flag),
&AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
@@ -5443,7 +5443,7 @@
// FIXME: Why don't we do this for inline asms with MRVs?
if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
- MVT ResultType = TLI.getValueType(CS.getType());
+ EVT ResultType = TLI.getValueType(CS.getType());
// If any of the results of the inline asm is a vector, it may have the
// wrong width/num elts. This can happen for register classes that can
@@ -5492,7 +5492,7 @@
getValue(StoresToEmit[i].second),
StoresToEmit[i].second, 0));
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
@@ -5509,13 +5509,13 @@
uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
if (ElementSize != 1) {
// Src is always 32-bits, make sure the constant fits.
- assert(Src.getValueType() == MVT::i32);
+ assert(Src.getValueType() == EVT::i32);
ElementSize = (uint32_t)ElementSize;
Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
Src, DAG.getConstant(ElementSize, Src.getValueType()));
}
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(Src.getValueType()))
Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
@@ -5548,7 +5548,7 @@
Entry.Node = getValue(I.getOperand(0));
Entry.Ty = TLI.getTargetData()->getIntPtrType();
Args.push_back(Entry);
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
bool isTailCall = PerformTailCallOpt &&
isInTailCallPosition(&I, Attribute::None, TLI);
std::pair<SDValue,SDValue> Result =
@@ -5563,7 +5563,7 @@
void SelectionDAGLowering::visitVAStart(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
@@ -5578,14 +5578,14 @@
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
void SelectionDAGLowering::visitVACopy(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2)),
DAG.getSrcValue(I.getOperand(1)),
@@ -5611,12 +5611,12 @@
// Handle all of the outgoing arguments.
SmallVector<ISD::OutputArg, 32> Outs;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- const Type *ArgTy = VT.getTypeForMVT();
+ EVT VT = ValueVTs[Value];
+ const Type *ArgTy = VT.getTypeForEVT();
SDValue Op = SDValue(Args[i].Node.getNode(),
Args[i].Node.getResNo() + Value);
ISD::ArgFlagsTy Flags;
@@ -5648,7 +5648,7 @@
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
- MVT PartVT = getRegisterType(VT);
+ EVT PartVT = getRegisterType(VT);
unsigned NumParts = getNumRegisters(VT);
SmallVector<SDValue, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@@ -5675,11 +5675,11 @@
// Handle the incoming return values from the call.
SmallVector<ISD::InputArg, 32> Ins;
- SmallVector<MVT, 4> RetTys;
+ SmallVector<EVT, 4> RetTys;
ComputeValueVTs(*this, RetTy, RetTys);
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
- MVT VT = RetTys[I];
- MVT RegisterVT = getRegisterType(VT);
+ EVT VT = RetTys[I];
+ EVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags;
@@ -5706,7 +5706,7 @@
Outs, Ins, dl, DAG, InVals);
// Verify that the target's LowerCall behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
"LowerCall didn't return a valid chain!");
assert((!isTailCall || InVals.empty()) &&
"LowerCall emitted a return value for a tail call!");
@@ -5738,8 +5738,8 @@
SmallVector<SDValue, 4> ReturnValues;
unsigned CurReg = 0;
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
- MVT VT = RetTys[I];
- MVT RegisterVT = getRegisterType(VT);
+ EVT VT = RetTys[I];
+ EVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
SDValue ReturnValue =
@@ -5805,13 +5805,13 @@
unsigned Idx = 1;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++Idx) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I->getType(), ValueVTs);
bool isArgValueUsed = !I->use_empty();
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- const Type *ArgTy = VT.getTypeForMVT();
+ EVT VT = ValueVTs[Value];
+ const Type *ArgTy = VT.getTypeForEVT();
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
TD->getABITypeAlignment(ArgTy);
@@ -5841,7 +5841,7 @@
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
- MVT RegisterVT = TLI.getRegisterType(VT);
+ EVT RegisterVT = TLI.getRegisterType(VT);
unsigned NumRegs = TLI.getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
@@ -5862,7 +5862,7 @@
dl, DAG, InVals);
// Verify that the target's LowerFormalArguments behaved as expected.
- assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
+ assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other &&
"LowerFormalArguments didn't return a valid chain!");
assert(InVals.size() == Ins.size() &&
"LowerFormalArguments didn't emit the correct number of values!");
@@ -5882,12 +5882,12 @@
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
++I, ++Idx) {
SmallVector<SDValue, 4> ArgValues;
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
for (unsigned Value = 0; Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- MVT PartVT = TLI.getRegisterType(VT);
+ EVT VT = ValueVTs[Value];
+ EVT PartVT = TLI.getRegisterType(VT);
unsigned NumParts = TLI.getNumRegisters(VT);
if (!I->use_empty()) {
@@ -5975,10 +5975,10 @@
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
- MVT VT = ValueVTs[vti];
+ EVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(VT);
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
@@ -6029,10 +6029,10 @@
// own moves. Second, this check is necessary becuase FastISel doesn't
// use CreateRegForValue to create registers, so it always creates
// exactly one register for each non-void instruction.
- MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
- if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
- // Promote MVT::i1.
- if (VT == MVT::i1)
+ EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
+ if (VT == EVT::Other || !TLI.isTypeLegal(VT)) {
+ // Promote EVT::i1.
+ if (VT == EVT::i1)
VT = TLI.getTypeToTransformTo(VT);
else {
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h Mon Aug 10 17:56:29 2009
@@ -117,7 +117,7 @@
SmallSet<Instruction*, 8> CatchInfoFound;
#endif
- unsigned MakeReg(MVT VT);
+ unsigned MakeReg(EVT VT);
/// isExportedInst - Return true if the specified value is an instruction
/// exported from its block.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Aug 10 17:56:29 2009
@@ -283,7 +283,7 @@
delete FuncInfo;
}
-unsigned SelectionDAGISel::MakeReg(MVT VT) {
+unsigned SelectionDAGISel::MakeReg(EVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
@@ -421,7 +421,7 @@
// Otherwise, add all chain operands to the worklist.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- if (N->getOperand(i).getValueType() == MVT::Other)
+ if (N->getOperand(i).getValueType() == EVT::Other)
Worklist.push_back(N->getOperand(i).getNode());
// If this is a CopyToReg with a vreg dest, process it.
@@ -434,7 +434,7 @@
// Ignore non-scalar or non-integer values.
SDValue Src = N->getOperand(2);
- MVT SrcVT = Src.getValueType();
+ EVT SrcVT = Src.getValueType();
if (!SrcVT.isInteger() || SrcVT.isVector())
continue;
@@ -1098,7 +1098,7 @@
Ops.push_back(InOps[1]); // input asm string.
unsigned i = 2, e = InOps.size();
- if (InOps[e-1].getValueType() == MVT::Flag)
+ if (InOps[e-1].getValueType() == EVT::Flag)
--e; // Don't process a flag operand if it is here.
while (i != e) {
@@ -1119,7 +1119,7 @@
}
// Add this to the output node.
- MVT IntPtrTy = TLI.getPointerTy();
+ EVT IntPtrTy = TLI.getPointerTy();
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
IntPtrTy));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
@@ -1132,7 +1132,7 @@
Ops.push_back(InOps.back());
}
-/// findFlagUse - Return use of MVT::Flag value produced by the specified
+/// findFlagUse - Return use of EVT::Flag value produced by the specified
/// SDNode.
///
static SDNode *findFlagUse(SDNode *N) {
@@ -1235,8 +1235,8 @@
// Fold. But since Fold and FU are flagged together, this will create
// a cycle in the scheduling graph.
- MVT VT = Root->getValueType(Root->getNumValues()-1);
- while (VT == MVT::Flag) {
+ EVT VT = Root->getValueType(Root->getNumValues()-1);
+ while (VT == EVT::Flag) {
SDNode *FU = findFlagUse(Root);
if (FU == NULL)
break;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Mon Aug 10 17:56:29 2009
@@ -44,7 +44,7 @@
}
static std::string getEdgeDestLabel(const void *Node, unsigned i) {
- return ((const SDNode *) Node)->getValueType(i).getMVTString();
+ return ((const SDNode *) Node)->getValueType(i).getEVTString();
}
/// edgeTargetsEdgeSource - This method returns true if this outgoing edge
@@ -84,10 +84,10 @@
template<typename EdgeIter>
static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
SDValue Op = EI.getNode()->getOperand(EI.getOperand());
- MVT VT = Op.getValueType();
- if (VT == MVT::Flag)
+ EVT VT = Op.getValueType();
+ if (VT == EVT::Flag)
return "color=red,style=bold";
- else if (VT == MVT::Other)
+ else if (VT == EVT::Other)
return "color=blue,style=dashed";
return "";
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Aug 10 17:56:29 2009
@@ -249,9 +249,9 @@
/// getFPEXT - Return the FPEXT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::f32) {
- if (RetVT == MVT::f64)
+RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::f32) {
+ if (RetVT == EVT::f64)
return FPEXT_F32_F64;
}
return UNKNOWN_LIBCALL;
@@ -259,18 +259,18 @@
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) {
- if (RetVT == MVT::f32) {
- if (OpVT == MVT::f64)
+RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
+ if (RetVT == EVT::f32) {
+ if (OpVT == EVT::f64)
return FPROUND_F64_F32;
- if (OpVT == MVT::f80)
+ if (OpVT == EVT::f80)
return FPROUND_F80_F32;
- if (OpVT == MVT::ppcf128)
+ if (OpVT == EVT::ppcf128)
return FPROUND_PPCF128_F32;
- } else if (RetVT == MVT::f64) {
- if (OpVT == MVT::f80)
+ } else if (RetVT == EVT::f64) {
+ if (OpVT == EVT::f80)
return FPROUND_F80_F64;
- if (OpVT == MVT::ppcf128)
+ if (OpVT == EVT::ppcf128)
return FPROUND_PPCF128_F64;
}
return UNKNOWN_LIBCALL;
@@ -278,38 +278,38 @@
/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::f32) {
- if (RetVT == MVT::i8)
+RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::f32) {
+ if (RetVT == EVT::i8)
return FPTOSINT_F32_I8;
- if (RetVT == MVT::i16)
+ if (RetVT == EVT::i16)
return FPTOSINT_F32_I16;
- if (RetVT == MVT::i32)
+ if (RetVT == EVT::i32)
return FPTOSINT_F32_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_F32_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_F32_I128;
- } else if (OpVT == MVT::f64) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f64) {
+ if (RetVT == EVT::i32)
return FPTOSINT_F64_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_F64_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_F64_I128;
- } else if (OpVT == MVT::f80) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f80) {
+ if (RetVT == EVT::i32)
return FPTOSINT_F80_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_F80_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_F80_I128;
- } else if (OpVT == MVT::ppcf128) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::ppcf128) {
+ if (RetVT == EVT::i32)
return FPTOSINT_PPCF128_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_PPCF128_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
@@ -317,38 +317,38 @@
/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::f32) {
- if (RetVT == MVT::i8)
+RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::f32) {
+ if (RetVT == EVT::i8)
return FPTOUINT_F32_I8;
- if (RetVT == MVT::i16)
+ if (RetVT == EVT::i16)
return FPTOUINT_F32_I16;
- if (RetVT == MVT::i32)
+ if (RetVT == EVT::i32)
return FPTOUINT_F32_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_F32_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_F32_I128;
- } else if (OpVT == MVT::f64) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f64) {
+ if (RetVT == EVT::i32)
return FPTOUINT_F64_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_F64_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_F64_I128;
- } else if (OpVT == MVT::f80) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f80) {
+ if (RetVT == EVT::i32)
return FPTOUINT_F80_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_F80_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_F80_I128;
- } else if (OpVT == MVT::ppcf128) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::ppcf128) {
+ if (RetVT == EVT::i32)
return FPTOUINT_PPCF128_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_PPCF128_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
@@ -356,33 +356,33 @@
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::i32) {
- if (RetVT == MVT::f32)
+RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::i32) {
+ if (RetVT == EVT::f32)
return SINTTOFP_I32_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return SINTTOFP_I32_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return SINTTOFP_I32_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return SINTTOFP_I32_PPCF128;
- } else if (OpVT == MVT::i64) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i64) {
+ if (RetVT == EVT::f32)
return SINTTOFP_I64_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return SINTTOFP_I64_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return SINTTOFP_I64_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return SINTTOFP_I64_PPCF128;
- } else if (OpVT == MVT::i128) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i128) {
+ if (RetVT == EVT::f32)
return SINTTOFP_I128_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return SINTTOFP_I128_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return SINTTOFP_I128_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return SINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
@@ -390,33 +390,33 @@
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::i32) {
- if (RetVT == MVT::f32)
+RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::i32) {
+ if (RetVT == EVT::f32)
return UINTTOFP_I32_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return UINTTOFP_I32_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return UINTTOFP_I32_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return UINTTOFP_I32_PPCF128;
- } else if (OpVT == MVT::i64) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i64) {
+ if (RetVT == EVT::f32)
return UINTTOFP_I64_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return UINTTOFP_I64_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return UINTTOFP_I64_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return UINTTOFP_I64_PPCF128;
- } else if (OpVT == MVT::i128) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i128) {
+ if (RetVT == EVT::f32)
return UINTTOFP_I128_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return UINTTOFP_I128_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return UINTTOFP_I128_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return UINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
@@ -456,48 +456,48 @@
memset(CondCodeActions, 0, sizeof(CondCodeActions));
// Set default actions for various operations.
- for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
+ for (unsigned VT = 0; VT != (unsigned)EVT::LAST_VALUETYPE; ++VT) {
// Default all indexed load / store to expand.
for (unsigned IM = (unsigned)ISD::PRE_INC;
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
- setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
- setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
+ setIndexedLoadAction(IM, (EVT::SimpleValueType)VT, Expand);
+ setIndexedStoreAction(IM, (EVT::SimpleValueType)VT, Expand);
}
// These operations default to expand.
- setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FGETSIGN, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CONCAT_VECTORS, (EVT::SimpleValueType)VT, Expand);
}
// Most targets ignore the @llvm.prefetch intrinsic.
- setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
+ setOperationAction(ISD::PREFETCH, EVT::Other, Expand);
// ConstantFP nodes default to expand. Targets can either change this to
// Legal, in which case all fp constants are legal, or use addLegalFPImmediate
// to optimize expansions for certain constants.
- setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
- setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
- setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
+ setOperationAction(ISD::ConstantFP, EVT::f32, Expand);
+ setOperationAction(ISD::ConstantFP, EVT::f64, Expand);
+ setOperationAction(ISD::ConstantFP, EVT::f80, Expand);
// These library functions default to expand.
- setOperationAction(ISD::FLOG , MVT::f64, Expand);
- setOperationAction(ISD::FLOG2, MVT::f64, Expand);
- setOperationAction(ISD::FLOG10,MVT::f64, Expand);
- setOperationAction(ISD::FEXP , MVT::f64, Expand);
- setOperationAction(ISD::FEXP2, MVT::f64, Expand);
- setOperationAction(ISD::FLOG , MVT::f32, Expand);
- setOperationAction(ISD::FLOG2, MVT::f32, Expand);
- setOperationAction(ISD::FLOG10,MVT::f32, Expand);
- setOperationAction(ISD::FEXP , MVT::f32, Expand);
- setOperationAction(ISD::FEXP2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG , EVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, EVT::f64, Expand);
+ setOperationAction(ISD::FLOG10,EVT::f64, Expand);
+ setOperationAction(ISD::FEXP , EVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, EVT::f64, Expand);
+ setOperationAction(ISD::FLOG , EVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, EVT::f32, Expand);
+ setOperationAction(ISD::FLOG10,EVT::f32, Expand);
+ setOperationAction(ISD::FEXP , EVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, EVT::f32, Expand);
// Default ISD::TRAP to expand (which turns it into abort).
- setOperationAction(ISD::TRAP, MVT::Other, Expand);
+ setOperationAction(ISD::TRAP, EVT::Other, Expand);
IsLittleEndian = TD->isLittleEndian();
UsesGlobalOffsetTable = false;
ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()).getSimpleVT();
- memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
+ memset(RegClassForVT, 0,EVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
allowUnalignedMemoryAccesses = false;
@@ -524,7 +524,7 @@
// Tell Legalize whether the assembler supports DEBUG_LOC.
const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
if (!TASM || !TASM->hasDotLocAndDotFile())
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
}
TargetLowering::~TargetLowering() {
@@ -534,31 +534,31 @@
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLowering::computeRegisterProperties() {
- assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
+ assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
// Everything defaults to needing one register.
- for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
+ for (unsigned i = 0; i != EVT::LAST_VALUETYPE; ++i) {
NumRegistersForVT[i] = 1;
- RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
+ RegisterTypeForVT[i] = TransformToType[i] = (EVT::SimpleValueType)i;
}
// ...except isVoid, which doesn't need any registers.
- NumRegistersForVT[MVT::isVoid] = 0;
+ NumRegistersForVT[EVT::isVoid] = 0;
// Find the largest integer register class.
- unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
+ unsigned LargestIntReg = EVT::LAST_INTEGER_VALUETYPE;
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
- assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
+ assert(LargestIntReg != EVT::i1 && "No integer registers defined!");
// Every integer value type larger than this largest register takes twice as
// many registers to represent as the previous ValueType.
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
- MVT EVT = (MVT::SimpleValueType)ExpandedReg;
+ EVT EVT = (EVT::SimpleValueType)ExpandedReg;
if (!EVT.isInteger())
break;
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
- RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
- TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
+ RegisterTypeForVT[ExpandedReg] = (EVT::SimpleValueType)LargestIntReg;
+ TransformToType[ExpandedReg] = (EVT::SimpleValueType)(ExpandedReg - 1);
ValueTypeActions.setTypeAction(EVT, Expand);
}
@@ -566,56 +566,56 @@
// register to see which ones need promotion.
unsigned LegalIntReg = LargestIntReg;
for (unsigned IntReg = LargestIntReg - 1;
- IntReg >= (unsigned)MVT::i1; --IntReg) {
- MVT IVT = (MVT::SimpleValueType)IntReg;
+ IntReg >= (unsigned)EVT::i1; --IntReg) {
+ EVT IVT = (EVT::SimpleValueType)IntReg;
if (isTypeLegal(IVT)) {
LegalIntReg = IntReg;
} else {
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
- (MVT::SimpleValueType)LegalIntReg;
+ (EVT::SimpleValueType)LegalIntReg;
ValueTypeActions.setTypeAction(IVT, Promote);
}
}
// ppcf128 type is really two f64's.
- if (!isTypeLegal(MVT::ppcf128)) {
- NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
- RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
- TransformToType[MVT::ppcf128] = MVT::f64;
- ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
+ if (!isTypeLegal(EVT::ppcf128)) {
+ NumRegistersForVT[EVT::ppcf128] = 2*NumRegistersForVT[EVT::f64];
+ RegisterTypeForVT[EVT::ppcf128] = EVT::f64;
+ TransformToType[EVT::ppcf128] = EVT::f64;
+ ValueTypeActions.setTypeAction(EVT::ppcf128, Expand);
}
// Decide how to handle f64. If the target does not have native f64 support,
// expand it to i64 and we will be generating soft float library calls.
- if (!isTypeLegal(MVT::f64)) {
- NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
- RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
- TransformToType[MVT::f64] = MVT::i64;
- ValueTypeActions.setTypeAction(MVT::f64, Expand);
+ if (!isTypeLegal(EVT::f64)) {
+ NumRegistersForVT[EVT::f64] = NumRegistersForVT[EVT::i64];
+ RegisterTypeForVT[EVT::f64] = RegisterTypeForVT[EVT::i64];
+ TransformToType[EVT::f64] = EVT::i64;
+ ValueTypeActions.setTypeAction(EVT::f64, Expand);
}
// Decide how to handle f32. If the target does not have native support for
// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
- if (!isTypeLegal(MVT::f32)) {
- if (isTypeLegal(MVT::f64)) {
- NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
- RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
- TransformToType[MVT::f32] = MVT::f64;
- ValueTypeActions.setTypeAction(MVT::f32, Promote);
+ if (!isTypeLegal(EVT::f32)) {
+ if (isTypeLegal(EVT::f64)) {
+ NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::f64];
+ RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::f64];
+ TransformToType[EVT::f32] = EVT::f64;
+ ValueTypeActions.setTypeAction(EVT::f32, Promote);
} else {
- NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
- RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
- TransformToType[MVT::f32] = MVT::i32;
- ValueTypeActions.setTypeAction(MVT::f32, Expand);
+ NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::i32];
+ RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::i32];
+ TransformToType[EVT::f32] = EVT::i32;
+ ValueTypeActions.setTypeAction(EVT::f32, Expand);
}
}
// Loop over all of the vector value types to see which need transformations.
- for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
- MVT VT = (MVT::SimpleValueType)i;
+ for (unsigned i = EVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
+ EVT VT = (EVT::SimpleValueType)i;
if (!isTypeLegal(VT)) {
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
NumRegistersForVT[i] =
getVectorTypeBreakdown(VT,
@@ -625,10 +625,10 @@
// Determine if there is a legal wider type.
bool IsLegalWiderType = false;
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
- for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
- MVT SVT = (MVT::SimpleValueType)nVT;
+ for (unsigned nVT = i+1; nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) {
+ EVT SVT = (EVT::SimpleValueType)nVT;
if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts) {
TransformToType[i] = SVT;
@@ -638,10 +638,10 @@
}
}
if (!IsLegalWiderType) {
- MVT NVT = VT.getPow2VectorType();
+ EVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
- TransformToType[i] = MVT::Other;
+ TransformToType[i] = EVT::Other;
ValueTypeActions.setTypeAction(VT, Expand);
} else {
TransformToType[i] = NVT;
@@ -657,27 +657,27 @@
}
-MVT::SimpleValueType TargetLowering::getSetCCResultType(MVT VT) const {
+EVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
return getValueType(TD->getIntPtrType()).getSimpleVT();
}
/// getVectorTypeBreakdown - Vector types are broken down into some number of
-/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
-/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
-/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
+/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
+/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
+/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
///
/// This method returns the number of registers needed, and the VT for each
/// register. It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
///
-unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
- MVT &IntermediateVT,
+unsigned TargetLowering::getVectorTypeBreakdown(EVT VT,
+ EVT &IntermediateVT,
unsigned &NumIntermediates,
- MVT &RegisterVT) const {
+ EVT &RegisterVT) const {
// Figure out the right, legal destination reg to copy into.
unsigned NumElts = VT.getVectorNumElements();
- MVT EltTy = VT.getVectorElementType();
+ EVT EltTy = VT.getVectorElementType();
unsigned NumVectorRegs = 1;
@@ -690,19 +690,19 @@
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
- while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
+ while (NumElts > 1 && !isTypeLegal(EVT::getVectorVT(EltTy, NumElts))) {
NumElts >>= 1;
NumVectorRegs <<= 1;
}
NumIntermediates = NumVectorRegs;
- MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
+ EVT NewVT = EVT::getVectorVT(EltTy, NumElts);
if (!isTypeLegal(NewVT))
NewVT = EltTy;
IntermediateVT = NewVT;
- MVT DestVT = getRegisterType(NewVT);
+ EVT DestVT = getRegisterType(NewVT);
RegisterVT = DestVT;
if (DestVT.bitsLT(NewVT)) {
// Value is expanded, e.g. i64 -> i16.
@@ -718,16 +718,16 @@
/// getWidenVectorType: given a vector type, returns the type to widen to
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
-/// If there is no vector type that we want to widen to, returns MVT::Other
+/// If there is no vector type that we want to widen to, returns EVT::Other
/// When and where to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
-MVT TargetLowering::getWidenVectorType(MVT VT) const {
+EVT TargetLowering::getWidenVectorType(EVT VT) const {
assert(VT.isVector());
if (isTypeLegal(VT))
return VT;
// Default is not to widen until moved to LegalizeTypes
- return MVT::Other;
+ return EVT::Other;
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
@@ -788,7 +788,7 @@
// if we can expand it to have all bits set, do it
if (C->getAPIntValue().intersects(~Demanded)) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
DAG.getConstant(Demanded &
C->getAPIntValue(),
@@ -829,7 +829,7 @@
if (!isPowerOf2_32(SmallVTBits))
SmallVTBits = NextPowerOf2(SmallVTBits);
for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
- MVT SmallVT = MVT::getIntegerVT(SmallVTBits);
+ EVT SmallVT = EVT::getIntegerVT(SmallVTBits);
if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
TLI.isZExtFree(SmallVT, Op.getValueType())) {
// We found a type with free casts.
@@ -1015,7 +1015,7 @@
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
if ((KnownOne & KnownOne2) == KnownOne) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Op.getOperand(0), ANDC));
@@ -1030,7 +1030,7 @@
// if we can expand it to have all bits set, do it
if (Expanded.isAllOnesValue()) {
if (Expanded != C->getAPIntValue()) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
TLO.DAG.getConstant(Expanded, VT));
return TLO.CombineTo(Op, New);
@@ -1106,7 +1106,7 @@
SDValue NewSA =
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
InOp.getOperand(0), NewSA));
}
@@ -1123,7 +1123,7 @@
break;
case ISD::SRL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
unsigned ShAmt = SA->getZExtValue();
unsigned VTSize = VT.getSizeInBits();
SDValue InOp = Op.getOperand(0);
@@ -1175,7 +1175,7 @@
Op.getOperand(0), Op.getOperand(1)));
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
unsigned ShAmt = SA->getZExtValue();
// If the shift count is an invalid immediate, don't do anything.
@@ -1212,7 +1212,7 @@
}
break;
case ISD::SIGN_EXTEND_INREG: {
- MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
// Sign extension. Compute the demanded bits in the result that are not
// present in the input.
@@ -1279,7 +1279,7 @@
break;
}
case ISD::SIGN_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
@@ -1378,7 +1378,7 @@
break;
}
case ISD::AssertZext: {
- MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
@@ -1392,9 +1392,9 @@
#if 0
// If this is an FP->Int bitcast and if the sign bit is the only thing that
// is demanded, turn this into a FGETSIGN.
- if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) &&
- MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
- !MVT::isVector(Op.getOperand(0).getValueType())) {
+ if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
+ EVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
+ !EVT::isVector(Op.getOperand(0).getValueType())) {
// Only do this xform if FGETSIGN is valid or if before legalize.
if (!TLO.AfterLegalize ||
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
@@ -1499,7 +1499,7 @@
// to handle some common cases.
// Fall back to ComputeMaskedBits to catch other known cases.
- MVT OpVT = Val.getValueType();
+ EVT OpVT = Val.getValueType();
unsigned BitWidth = OpVT.getSizeInBits();
APInt Mask = APInt::getAllOnesValue(BitWidth);
APInt KnownZero, KnownOne;
@@ -1511,7 +1511,7 @@
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
/// and cc. If it is unable to simplify it, return a null SDValue.
SDValue
-TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
+TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI, DebugLoc dl) const {
SelectionDAG &DAG = DCI.DAG;
@@ -1597,9 +1597,9 @@
}
}
if (bestWidth) {
- MVT newVT = MVT::getIntegerVT(bestWidth);
+ EVT newVT = EVT::getIntegerVT(bestWidth);
if (newVT.isRound()) {
- MVT PtrType = Lod->getOperand(1).getValueType();
+ EVT PtrType = Lod->getOperand(1).getValueType();
SDValue Ptr = Lod->getBasePtr();
if (bestOffset != 0)
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
@@ -1653,7 +1653,7 @@
case ISD::SETUGE:
case ISD::SETULT:
case ISD::SETULE: {
- MVT newVT = N0.getOperand(0).getValueType();
+ EVT newVT = N0.getOperand(0).getValueType();
if (DCI.isBeforeLegalizeOps() ||
(isOperationLegal(ISD::SETCC, newVT) &&
getCondCodeAction(Cond, newVT)==Legal))
@@ -1667,9 +1667,9 @@
}
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
- MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
+ EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
- MVT ExtDstTy = N0.getValueType();
+ EVT ExtDstTy = N0.getValueType();
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
// If the extended part has any inconsistent bits, it cannot ever
@@ -1681,7 +1681,7 @@
return DAG.getConstant(Cond == ISD::SETNE, VT);
SDValue ZextOp;
- MVT Op0Ty = N0.getOperand(0).getValueType();
+ EVT Op0Ty = N0.getOperand(0).getValueType();
if (Op0Ty == ExtSrcTy) {
ZextOp = N0.getOperand(0);
} else {
@@ -1822,7 +1822,7 @@
VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS =
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
- MVT ShiftTy = DCI.isBeforeLegalize() ?
+ EVT ShiftTy = DCI.isBeforeLegalize() ?
getPointerTy() : getShiftAmountTy();
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
@@ -2010,46 +2010,46 @@
// Fold away ALL boolean setcc's.
SDValue Temp;
- if (N0.getValueType() == MVT::i1 && foldBooleans) {
+ if (N0.getValueType() == EVT::i1 && foldBooleans) {
switch (Cond) {
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
- Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
- N0 = DAG.getNOT(dl, Temp, MVT::i1);
+ Temp = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
+ N0 = DAG.getNOT(dl, Temp, EVT::i1);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETNE: // X != Y --> (X^Y)
- N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
+ N0 = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
break;
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
- Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, EVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
- Temp = DAG.getNOT(dl, N1, MVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, EVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
- Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, EVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
- Temp = DAG.getNOT(dl, N1, MVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, EVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N0, Temp);
break;
}
- if (VT != MVT::i1) {
+ if (VT != EVT::i1) {
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(N0.getNode());
// FIXME: If running after legalize, we probably can't do this.
@@ -2102,7 +2102,7 @@
const MachineFrameInfo *MFI) const {
if (LD->getChain() != Base->getChain())
return false;
- MVT VT = LD->getValueType(0);
+ EVT VT = LD->getValueType(0);
if (VT.getSizeInBits() / 8 != Bytes)
return false;
@@ -2183,7 +2183,7 @@
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand.
-const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
+const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
if (ConstraintVT.isInteger())
return "r";
if (ConstraintVT.isFloatingPoint())
@@ -2245,7 +2245,7 @@
// now; without this it would get ZExt'd later in
// ScheduleDAGSDNodes::EmitNode, which is very generic.
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
- MVT::i64));
+ EVT::i64));
return;
}
}
@@ -2256,14 +2256,14 @@
std::vector<unsigned> TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
return std::vector<unsigned>();
}
std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
if (Constraint[0] != '{')
return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
@@ -2479,7 +2479,7 @@
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl= N->getDebugLoc();
// Check to see if we can do this.
@@ -2536,7 +2536,7 @@
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// Check to see if we can do this.
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Aug 10 17:56:29 2009
@@ -63,7 +63,7 @@
/// getI32Imm - Return a target constant with the specified value, of type i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i32);
+ return CurDAG->getTargetConstant(Imm, EVT::i32);
}
SDNode *Select(SDValue Op);
@@ -156,13 +156,13 @@
BaseReg = N.getOperand(0);
unsigned ShImmVal = 0;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- ShReg = CurDAG->getRegister(0, MVT::i32);
+ ShReg = CurDAG->getRegister(0, EVT::i32);
ShImmVal = RHS->getZExtValue() & 31;
} else {
ShReg = N.getOperand(1);
}
Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
- MVT::i32);
+ EVT::i32);
return true;
}
@@ -185,7 +185,7 @@
Base = Offset = N.getOperand(0);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
ARM_AM::lsl),
- MVT::i32);
+ EVT::i32);
return true;
}
}
@@ -200,10 +200,10 @@
} else if (N.getOpcode() == ARMISD::Wrapper) {
Base = N.getOperand(0);
}
- Offset = CurDAG->getRegister(0, MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
ARM_AM::no_shift),
- MVT::i32);
+ EVT::i32);
return true;
}
@@ -218,7 +218,7 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
ARM_AM::AddrOpc AddSub = ARM_AM::add;
if (RHSC < 0) {
@@ -227,7 +227,7 @@
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
ARM_AM::no_shift),
- MVT::i32);
+ EVT::i32);
return true;
}
}
@@ -270,7 +270,7 @@
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
- MVT::i32);
+ EVT::i32);
return true;
}
@@ -285,10 +285,10 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 0x1000) { // 12 bits.
- Offset = CurDAG->getRegister(0, MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
ARM_AM::no_shift),
- MVT::i32);
+ EVT::i32);
return true;
}
}
@@ -308,7 +308,7 @@
}
Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
- MVT::i32);
+ EVT::i32);
return true;
}
@@ -320,7 +320,7 @@
// X - C is canonicalize to X + -C, no need to handle it here.
Base = N.getOperand(0);
Offset = N.getOperand(1);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),EVT::i32);
return true;
}
@@ -330,8 +330,8 @@
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, MVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),EVT::i32);
return true;
}
@@ -345,21 +345,21 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- Offset = CurDAG->getRegister(0, MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
ARM_AM::AddrOpc AddSub = ARM_AM::add;
if (RHSC < 0) {
AddSub = ARM_AM::sub;
RHSC = - RHSC;
}
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),EVT::i32);
return true;
}
}
Base = N.getOperand(0);
Offset = N.getOperand(1);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), EVT::i32);
return true;
}
@@ -374,21 +374,21 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
int Val = (int)C->getZExtValue();
if (Val >= 0 && Val < 256) {
- Offset = CurDAG->getRegister(0, MVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), EVT::i32);
return true;
}
}
Offset = N;
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), EVT::i32);
return true;
}
bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
SDValue &Addr, SDValue &Mode) {
Addr = N;
- Mode = CurDAG->getTargetConstant(0, MVT::i32);
+ Mode = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -403,7 +403,7 @@
Base = N.getOperand(0);
}
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
- MVT::i32);
+ EVT::i32);
return true;
}
@@ -426,7 +426,7 @@
RHSC = - RHSC;
}
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
- MVT::i32);
+ EVT::i32);
return true;
}
}
@@ -434,7 +434,7 @@
Base = N;
Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
- MVT::i32);
+ EVT::i32);
return true;
}
@@ -443,8 +443,8 @@
SDValue &Opc) {
Addr = N;
// The optional writeback is handled in ARMLoadStoreOpt.
- Update = CurDAG->getRegister(0, MVT::i32);
- Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
+ Update = CurDAG->getRegister(0, EVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), EVT::i32);
return true;
}
@@ -454,7 +454,7 @@
Offset = N.getOperand(0);
SDValue N1 = N.getOperand(1);
Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
- MVT::i32);
+ EVT::i32);
return true;
}
return false;
@@ -493,8 +493,8 @@
if (N.getOpcode() != ISD::ADD) {
Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
- Offset = CurDAG->getRegister(0, MVT::i32);
- OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -504,8 +504,8 @@
if ((LHSR && LHSR->getReg() == ARM::SP) ||
(RHSR && RHSR->getReg() == ARM::SP)) {
Base = N;
- Offset = CurDAG->getRegister(0, MVT::i32);
- OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -516,8 +516,8 @@
RHSC /= Scale;
if (RHSC >= 0 && RHSC < 32) {
Base = N.getOperand(0);
- Offset = CurDAG->getRegister(0, MVT::i32);
- OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
+ Offset = CurDAG->getRegister(0, EVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
return true;
}
}
@@ -525,7 +525,7 @@
Base = N.getOperand(0);
Offset = N.getOperand(1);
- OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -552,7 +552,7 @@
if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -573,7 +573,7 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
return true;
}
}
@@ -612,7 +612,7 @@
if (N.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- OffImm = CurDAG->getTargetConstant(0, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
return false;
@@ -629,7 +629,7 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
return true;
}
}
@@ -652,7 +652,7 @@
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
}
- OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
return true;
}
}
@@ -671,8 +671,8 @@
int RHSC = (int)RHS->getZExtValue();
if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
- ? CurDAG->getTargetConstant(RHSC, MVT::i32)
- : CurDAG->getTargetConstant(-RHSC, MVT::i32);
+ ? CurDAG->getTargetConstant(RHSC, EVT::i32)
+ : CurDAG->getTargetConstant(-RHSC, EVT::i32);
return true;
}
}
@@ -688,7 +688,7 @@
if (((RHSC & 0x3) == 0) &&
((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
Base = N.getOperand(0);
- OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32);
return true;
}
}
@@ -697,7 +697,7 @@
int RHSC = (int)RHS->getZExtValue();
if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
Base = N.getOperand(0);
- OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
+ OffImm = CurDAG->getTargetConstant(-RHSC, EVT::i32);
return true;
}
}
@@ -719,8 +719,8 @@
if (Base.getOpcode() == ISD::TargetConstantPool)
return false; // We want to select t2LDRpci instead.
}
- OffReg = CurDAG->getRegister(0, MVT::i32);
- ShImm = CurDAG->getTargetConstant(0, MVT::i32);
+ OffReg = CurDAG->getRegister(0, EVT::i32);
+ ShImm = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -736,8 +736,8 @@
// Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
if (N.getOpcode() == ISD::SUB) {
Base = N;
- OffReg = CurDAG->getRegister(0, MVT::i32);
- ShImm = CurDAG->getTargetConstant(0, MVT::i32);
+ OffReg = CurDAG->getRegister(0, EVT::i32);
+ ShImm = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -771,7 +771,7 @@
}
}
- ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
+ ShImm = CurDAG->getTargetConstant(ShAmt, EVT::i32);
return true;
}
@@ -780,7 +780,7 @@
/// getAL - Returns a ARMCC::AL immediate node.
static inline SDValue getAL(SelectionDAG *CurDAG) {
- return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
+ return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, EVT::i32);
}
SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
@@ -789,22 +789,22 @@
if (AM == ISD::UNINDEXED)
return NULL;
- MVT LoadedVT = LD->getMemoryVT();
+ EVT LoadedVT = LD->getMemoryVT();
SDValue Offset, AMOpc;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
bool Match = false;
- if (LoadedVT == MVT::i32 &&
+ if (LoadedVT == EVT::i32 &&
SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
Match = true;
- } else if (LoadedVT == MVT::i16 &&
+ } else if (LoadedVT == EVT::i16 &&
SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Match = true;
Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
: (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
- } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
+ } else if (LoadedVT == EVT::i8 || LoadedVT == EVT::i1) {
if (LD->getExtensionType() == ISD::SEXTLOAD) {
if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
Match = true;
@@ -822,9 +822,9 @@
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
- CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
- MVT::Other, Ops, 6);
+ CurDAG->getRegister(0, EVT::i32), Chain };
+ return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
+ EVT::Other, Ops, 6);
}
return NULL;
@@ -836,7 +836,7 @@
if (AM == ISD::UNINDEXED)
return NULL;
- MVT LoadedVT = LD->getMemoryVT();
+ EVT LoadedVT = LD->getMemoryVT();
bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
SDValue Offset;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
@@ -844,17 +844,17 @@
bool Match = false;
if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
switch (LoadedVT.getSimpleVT()) {
- case MVT::i32:
+ case EVT::i32:
Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
break;
- case MVT::i16:
+ case EVT::i16:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
else
Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
break;
- case MVT::i8:
- case MVT::i1:
+ case EVT::i8:
+ case EVT::i1:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
else
@@ -870,9 +870,9 @@
SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, getAL(CurDAG),
- CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
- MVT::Other, Ops, 5);
+ CurDAG->getRegister(0, EVT::i32), Chain };
+ return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32,
+ EVT::Other, Ops, 5);
}
return NULL;
@@ -881,11 +881,11 @@
SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
- SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
+ SDValue SP = CurDAG->getRegister(ARM::SP, EVT::i32);
int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
if (AlignVal < 0)
// We need to align the stack. Use Thumb1 tAND which is the only thumb
@@ -900,8 +900,8 @@
// tSUBspi - immediate is between 0 ... 508 inclusive.
if (C <= 508 && ((C & 3) == 0))
// FIXME: tSUBspi encode scale 4 implicitly.
- return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
- CurDAG->getTargetConstant(C/4, MVT::i32),
+ return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, EVT::Other, SP,
+ CurDAG->getTargetConstant(C/4, EVT::i32),
Chain);
if (Subtarget->isThumb1Only()) {
@@ -909,22 +909,22 @@
// should have negated the size operand already. FIXME: We can't insert
// new target independent node at this stage so we are forced to negate
// it earlier. Is there a better solution?
- return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
+ return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, EVT::Other, SP, Size,
Chain);
} else if (Subtarget->isThumb2()) {
if (isC && Predicate_t2_so_imm(Size.getNode())) {
// t2SUBrSPi
- SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
+ SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, EVT::Other, Ops, 3);
} else if (isC && Predicate_imm0_4095(Size.getNode())) {
// t2SUBrSPi12
- SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
+ SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain };
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, EVT::Other, Ops, 3);
} else {
// t2SUBrSPs
SDValue Ops[] = { SP, Size,
getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
- return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
+ return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, EVT::Other, Ops, 4);
}
}
@@ -964,21 +964,21 @@
SDNode *ResNode;
if (Subtarget->isThumb1Only()) {
- SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
+ SDValue Pred = CurDAG->getTargetConstant(0xEULL, EVT::i32);
+ SDValue PredReg = CurDAG->getRegister(0, EVT::i32);
SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
- ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
+ ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, EVT::i32, EVT::Other,
Ops, 4);
} else {
SDValue Ops[] = {
CPIdx,
- CurDAG->getRegister(0, MVT::i32),
- CurDAG->getTargetConstant(0, MVT::i32),
+ CurDAG->getRegister(0, EVT::i32),
+ CurDAG->getTargetConstant(0, EVT::i32),
getAL(CurDAG),
- CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, EVT::i32),
CurDAG->getEntryNode()
};
- ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
+ ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, EVT::i32, EVT::Other,
Ops, 6);
}
ReplaceUses(Op, SDValue(ResNode, 0));
@@ -990,19 +990,19 @@
}
case ISD::ConstantFP: {
ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(N);
- MVT VT = CFP->getValueType(0);
+ EVT VT = CFP->getValueType(0);
ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
SDValue CPIdx = CurDAG->getTargetConstantPool(LLVMC, TLI.getPointerTy());
SDNode *ResNode;
SDValue Ops[] = {
CPIdx,
- CurDAG->getTargetConstant(0, MVT::i32),
+ CurDAG->getTargetConstant(0, EVT::i32),
getAL(CurDAG),
- CurDAG->getRegister(0, MVT::i32),
+ CurDAG->getRegister(0, EVT::i32),
CurDAG->getEntryNode()
};
- unsigned Opc = (VT == MVT::f32) ? ARM::FLDS : ARM::FLDD;
- ResNode=CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Ops, 5);
+ unsigned Opc = (VT == EVT::f32) ? ARM::FLDS : ARM::FLDD;
+ ResNode=CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Ops, 5);
ReplaceUses(Op, SDValue(ResNode, 0));
return NULL;
}
@@ -1011,15 +1011,15 @@
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
if (Subtarget->isThumb1Only()) {
- return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
- CurDAG->getTargetConstant(0, MVT::i32));
+ return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, EVT::i32, TFI,
+ CurDAG->getTargetConstant(0, EVT::i32));
} else {
unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
ARM::t2ADDri : ARM::ADDri);
- SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
- getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
- CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
+ SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, EVT::i32),
+ getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
+ CurDAG->getRegister(0, EVT::i32) };
+ return CurDAG->SelectNodeTo(N, Opc, EVT::i32, Ops, 5);
}
}
case ARMISD::DYN_ALLOC:
@@ -1036,14 +1036,14 @@
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
- SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
- SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
+ SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
+ SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
+ return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, EVT::i32, Ops, 6);
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
+ return CurDAG->SelectNodeTo(N, ARM::ADDrs, EVT::i32, Ops, 7);
}
}
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
@@ -1052,35 +1052,35 @@
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
- SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
- SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
+ SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32);
+ SDValue Reg0 = CurDAG->getRegister(0, EVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
+ return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, EVT::i32, Ops, 5);
} else {
SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
- return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
+ return CurDAG->SelectNodeTo(N, ARM::RSBrs, EVT::i32, Ops, 7);
}
}
}
break;
case ARMISD::FMRRD:
- return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
+ return CurDAG->getTargetNode(ARM::FMRRD, dl, EVT::i32, EVT::i32,
Op.getOperand(0), getAL(CurDAG),
- CurDAG->getRegister(0, MVT::i32));
+ CurDAG->getRegister(0, EVT::i32));
case ISD::UMUL_LOHI: {
if (Subtarget->isThumb1Only())
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
- CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
+ getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
+ CurDAG->getRegister(0, EVT::i32) };
+ return CurDAG->getTargetNode(ARM::t2UMULL, dl, EVT::i32, EVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
- CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
+ getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
+ CurDAG->getRegister(0, EVT::i32) };
+ return CurDAG->getTargetNode(ARM::UMULL, dl, EVT::i32, EVT::i32, Ops, 5);
}
}
case ISD::SMUL_LOHI: {
@@ -1088,13 +1088,13 @@
break;
if (Subtarget->isThumb()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
+ getAL(CurDAG), CurDAG->getRegister(0, EVT::i32) };
+ return CurDAG->getTargetNode(ARM::t2SMULL, dl, EVT::i32, EVT::i32, Ops,4);
} else {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
- getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
- CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
+ getAL(CurDAG), CurDAG->getRegister(0, EVT::i32),
+ CurDAG->getRegister(0, EVT::i32) };
+ return CurDAG->getTargetNode(ARM::SMULL, dl, EVT::i32, EVT::i32, Ops, 5);
}
}
case ISD::LOAD: {
@@ -1134,10 +1134,10 @@
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
- SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
- MVT::Flag, Ops, 5);
+ SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, EVT::Other,
+ EVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
if (Op.getNode()->getNumValues() == 2) {
InFlag = SDValue(ResNode, 1);
@@ -1147,7 +1147,7 @@
return NULL;
}
case ARMISD::CMOV: {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
@@ -1156,7 +1156,7 @@
assert(N2.getOpcode() == ISD::Constant);
assert(N3.getOpcode() == ISD::Register);
- if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
+ if (!Subtarget->isThumb1Only() && VT == EVT::i32) {
// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
// Pattern complexity = 18 cost = 1 size = 0
@@ -1178,21 +1178,21 @@
break;
}
SDValue SOShImm =
- CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
+ CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), EVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
- return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
+ return CurDAG->SelectNodeTo(Op.getNode(), Opc, EVT::i32,Ops, 6);
}
} else {
if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::MOVCCs, MVT::i32, Ops, 7);
+ ARM::MOVCCs, EVT::i32, Ops, 7);
}
}
@@ -1207,25 +1207,25 @@
if (Predicate_t2_so_imm(N3.getNode())) {
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::t2MOVCCi, MVT::i32, Ops, 5);
+ ARM::t2MOVCCi, EVT::i32, Ops, 5);
}
} else {
if (Predicate_so_imm(N3.getNode())) {
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
return CurDAG->SelectNodeTo(Op.getNode(),
- ARM::MOVCCi, MVT::i32, Ops, 5);
+ ARM::MOVCCi, EVT::i32, Ops, 5);
}
}
}
@@ -1242,28 +1242,28 @@
// Also FCPYScc and FCPYDcc.
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");
break;
- case MVT::i32:
+ case EVT::i32:
Opc = Subtarget->isThumb()
? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
: ARM::MOVCCr;
break;
- case MVT::f32:
+ case EVT::f32:
Opc = ARM::FCPYScc;
break;
- case MVT::f64:
+ case EVT::f64:
Opc = ARM::FCPYDcc;
break;
}
return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
}
case ARMISD::CNEG: {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
@@ -1274,16 +1274,16 @@
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getZExtValue()),
- MVT::i32);
+ EVT::i32);
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
unsigned Opc = 0;
switch (VT.getSimpleVT()) {
default: assert(false && "Illegal conditional move type!");
break;
- case MVT::f32:
+ case EVT::f32:
Opc = ARM::FNEGScc;
break;
- case MVT::f64:
+ case EVT::f64:
Opc = ARM::FNEGDcc;
break;
}
@@ -1328,11 +1328,11 @@
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
- MVT::Other, Ops, 3);
+ EVT::Other, Ops, 3);
}
case ISD::VECTOR_SHUFFLE: {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
// Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
// ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
@@ -1345,22 +1345,22 @@
Op.getOperand(1).getOpcode() == ISD::UNDEF) {
unsigned LaneVal = SVOp->getSplatIndex();
- MVT HalfVT;
+ EVT HalfVT;
unsigned Opc = 0;
switch (VT.getVectorElementType().getSimpleVT()) {
default: llvm_unreachable("unhandled VDUP splat type");
- case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
- case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
- case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
- case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
+ case EVT::i8: Opc = ARM::VDUPLN8q; HalfVT = EVT::v8i8; break;
+ case EVT::i16: Opc = ARM::VDUPLN16q; HalfVT = EVT::v4i16; break;
+ case EVT::i32: Opc = ARM::VDUPLN32q; HalfVT = EVT::v2i32; break;
+ case EVT::f32: Opc = ARM::VDUPLNfq; HalfVT = EVT::v2f32; break;
}
// The source operand needs to be changed to a subreg of the original
// 128-bit operand, and the lane number needs to be adjusted accordingly.
unsigned NumElts = VT.getVectorNumElements() / 2;
unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
- SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
- SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
+ SDValue SR = CurDAG->getTargetConstant(SRVal, EVT::i32);
+ SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, EVT::i32);
SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
dl, HalfVT, N->getOperand(0), SR);
return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
@@ -1374,16 +1374,16 @@
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
switch (VT.getSimpleVT()) {
default: llvm_unreachable("unhandled VLD2D type");
- case MVT::v8i8: Opc = ARM::VLD2d8; break;
- case MVT::v4i16: Opc = ARM::VLD2d16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VLD2d32; break;
+ case EVT::v8i8: Opc = ARM::VLD2d8; break;
+ case EVT::v4i16: Opc = ARM::VLD2d16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VLD2d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, EVT::Other, Ops, 3);
}
case ARMISD::VLD3D: {
@@ -1391,16 +1391,16 @@
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
switch (VT.getSimpleVT()) {
default: llvm_unreachable("unhandled VLD3D type");
- case MVT::v8i8: Opc = ARM::VLD3d8; break;
- case MVT::v4i16: Opc = ARM::VLD3d16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VLD3d32; break;
+ case EVT::v8i8: Opc = ARM::VLD3d8; break;
+ case EVT::v4i16: Opc = ARM::VLD3d16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VLD3d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
+ return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, EVT::Other, Ops, 3);
}
case ARMISD::VLD4D: {
@@ -1408,17 +1408,17 @@
if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
return NULL;
unsigned Opc = 0;
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
switch (VT.getSimpleVT()) {
default: llvm_unreachable("unhandled VLD4D type");
- case MVT::v8i8: Opc = ARM::VLD4d8; break;
- case MVT::v4i16: Opc = ARM::VLD4d16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VLD4d32; break;
+ case EVT::v8i8: Opc = ARM::VLD4d8; break;
+ case EVT::v4i16: Opc = ARM::VLD4d16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VLD4d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
- std::vector<MVT> ResTys(4, VT);
- ResTys.push_back(MVT::Other);
+ std::vector<EVT> ResTys(4, VT);
+ ResTys.push_back(EVT::Other);
return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
}
@@ -1429,14 +1429,14 @@
unsigned Opc = 0;
switch (N->getOperand(2).getValueType().getSimpleVT()) {
default: llvm_unreachable("unhandled VST2D type");
- case MVT::v8i8: Opc = ARM::VST2d8; break;
- case MVT::v4i16: Opc = ARM::VST2d16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VST2d32; break;
+ case EVT::v8i8: Opc = ARM::VST2d8; break;
+ case EVT::v4i16: Opc = ARM::VST2d16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VST2d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3) };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
+ return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 5);
}
case ARMISD::VST3D: {
@@ -1446,15 +1446,15 @@
unsigned Opc = 0;
switch (N->getOperand(2).getValueType().getSimpleVT()) {
default: llvm_unreachable("unhandled VST3D type");
- case MVT::v8i8: Opc = ARM::VST3d8; break;
- case MVT::v4i16: Opc = ARM::VST3d16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VST3d32; break;
+ case EVT::v8i8: Opc = ARM::VST3d8; break;
+ case EVT::v4i16: Opc = ARM::VST3d16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VST3d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
N->getOperand(4) };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
+ return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 6);
}
case ARMISD::VST4D: {
@@ -1464,20 +1464,20 @@
unsigned Opc = 0;
switch (N->getOperand(2).getValueType().getSimpleVT()) {
default: llvm_unreachable("unhandled VST4D type");
- case MVT::v8i8: Opc = ARM::VST4d8; break;
- case MVT::v4i16: Opc = ARM::VST4d16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VST4d32; break;
+ case EVT::v8i8: Opc = ARM::VST4d8; break;
+ case EVT::v4i16: Opc = ARM::VST4d16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VST4d32; break;
}
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(2), N->getOperand(3),
N->getOperand(4), N->getOperand(5) };
- return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
+ return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7);
}
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
unsigned Opc = 0;
// Match intrinsics that return multiple values.
@@ -1488,14 +1488,14 @@
case Intrinsic::arm_neon_vtrnf:
switch (VT.getSimpleVT()) {
default: return NULL;
- case MVT::v8i8: Opc = ARM::VTRNd8; break;
- case MVT::v4i16: Opc = ARM::VTRNd16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VTRNd32; break;
- case MVT::v16i8: Opc = ARM::VTRNq8; break;
- case MVT::v8i16: Opc = ARM::VTRNq16; break;
- case MVT::v4f32:
- case MVT::v4i32: Opc = ARM::VTRNq32; break;
+ case EVT::v8i8: Opc = ARM::VTRNd8; break;
+ case EVT::v4i16: Opc = ARM::VTRNd16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VTRNd32; break;
+ case EVT::v16i8: Opc = ARM::VTRNq8; break;
+ case EVT::v8i16: Opc = ARM::VTRNq16; break;
+ case EVT::v4f32:
+ case EVT::v4i32: Opc = ARM::VTRNq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
@@ -1504,14 +1504,14 @@
case Intrinsic::arm_neon_vuzpf:
switch (VT.getSimpleVT()) {
default: return NULL;
- case MVT::v8i8: Opc = ARM::VUZPd8; break;
- case MVT::v4i16: Opc = ARM::VUZPd16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VUZPd32; break;
- case MVT::v16i8: Opc = ARM::VUZPq8; break;
- case MVT::v8i16: Opc = ARM::VUZPq16; break;
- case MVT::v4f32:
- case MVT::v4i32: Opc = ARM::VUZPq32; break;
+ case EVT::v8i8: Opc = ARM::VUZPd8; break;
+ case EVT::v4i16: Opc = ARM::VUZPd16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VUZPd32; break;
+ case EVT::v16i8: Opc = ARM::VUZPq8; break;
+ case EVT::v8i16: Opc = ARM::VUZPq16; break;
+ case EVT::v4f32:
+ case EVT::v4i32: Opc = ARM::VUZPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
@@ -1520,14 +1520,14 @@
case Intrinsic::arm_neon_vzipf:
switch (VT.getSimpleVT()) {
default: return NULL;
- case MVT::v8i8: Opc = ARM::VZIPd8; break;
- case MVT::v4i16: Opc = ARM::VZIPd16; break;
- case MVT::v2f32:
- case MVT::v2i32: Opc = ARM::VZIPd32; break;
- case MVT::v16i8: Opc = ARM::VZIPq8; break;
- case MVT::v8i16: Opc = ARM::VZIPq16; break;
- case MVT::v4f32:
- case MVT::v4i32: Opc = ARM::VZIPq32; break;
+ case EVT::v8i8: Opc = ARM::VZIPd8; break;
+ case EVT::v4i16: Opc = ARM::VZIPd16; break;
+ case EVT::v2f32:
+ case EVT::v2i32: Opc = ARM::VZIPd32; break;
+ case EVT::v16i8: Opc = ARM::VZIPq8; break;
+ case EVT::v8i16: Opc = ARM::VZIPq16; break;
+ case EVT::v4f32:
+ case EVT::v4i32: Opc = ARM::VZIPq32; break;
}
return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1),
N->getOperand(2));
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Aug 10 17:56:29 2009
@@ -41,25 +41,25 @@
#include "llvm/Support/MathExtras.h"
using namespace llvm;
-static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
-static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
-static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
-static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State);
-void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
- MVT PromotedBitwiseVT) {
+void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
+ EVT PromotedBitwiseVT) {
if (VT != PromotedLdStVT) {
setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
@@ -70,10 +70,10 @@
PromotedLdStVT.getSimpleVT());
}
- MVT ElemTy = VT.getVectorElementType();
- if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
+ EVT ElemTy = VT.getVectorElementType();
+ if (ElemTy != EVT::i64 && ElemTy != EVT::f64)
setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
- if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
+ if (ElemTy == EVT::i8 || ElemTy == EVT::i16)
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
@@ -99,14 +99,14 @@
}
}
-void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
+void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
addRegisterClass(VT, ARM::DPRRegisterClass);
- addTypeForNEON(VT, MVT::f64, MVT::v2i32);
+ addTypeForNEON(VT, EVT::f64, EVT::v2i32);
}
-void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
+void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
addRegisterClass(VT, ARM::QPRRegisterClass);
- addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
+ addTypeForNEON(VT, EVT::v2f64, EVT::v4i32);
}
static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
@@ -202,29 +202,29 @@
setLibcallName(RTLIB::SRA_I128, 0);
if (Subtarget->isThumb1Only())
- addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
+ addRegisterClass(EVT::i32, ARM::tGPRRegisterClass);
else
- addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
+ addRegisterClass(EVT::i32, ARM::GPRRegisterClass);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
- addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
+ addRegisterClass(EVT::f32, ARM::SPRRegisterClass);
+ addRegisterClass(EVT::f64, ARM::DPRRegisterClass);
- setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ setTruncStoreAction(EVT::f64, EVT::f32, Expand);
}
if (Subtarget->hasNEON()) {
- addDRTypeForNEON(MVT::v2f32);
- addDRTypeForNEON(MVT::v8i8);
- addDRTypeForNEON(MVT::v4i16);
- addDRTypeForNEON(MVT::v2i32);
- addDRTypeForNEON(MVT::v1i64);
-
- addQRTypeForNEON(MVT::v4f32);
- addQRTypeForNEON(MVT::v2f64);
- addQRTypeForNEON(MVT::v16i8);
- addQRTypeForNEON(MVT::v8i16);
- addQRTypeForNEON(MVT::v4i32);
- addQRTypeForNEON(MVT::v2i64);
+ addDRTypeForNEON(EVT::v2f32);
+ addDRTypeForNEON(EVT::v8i8);
+ addDRTypeForNEON(EVT::v4i16);
+ addDRTypeForNEON(EVT::v2i32);
+ addDRTypeForNEON(EVT::v1i64);
+
+ addQRTypeForNEON(EVT::v4f32);
+ addQRTypeForNEON(EVT::v2f64);
+ addQRTypeForNEON(EVT::v16i8);
+ addQRTypeForNEON(EVT::v8i16);
+ addQRTypeForNEON(EVT::v4i32);
+ addQRTypeForNEON(EVT::v2i64);
setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
setTargetDAGCombine(ISD::SHL);
@@ -238,137 +238,137 @@
computeRegisterProperties();
// ARM does not have f32 extending load.
- setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
// ARM does not have i1 sign extending load.
- setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
// ARM supports all 4 flavors of integer indexed load / store.
if (!Subtarget->isThumb1Only()) {
for (unsigned im = (unsigned)ISD::PRE_INC;
im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
- setIndexedLoadAction(im, MVT::i1, Legal);
- setIndexedLoadAction(im, MVT::i8, Legal);
- setIndexedLoadAction(im, MVT::i16, Legal);
- setIndexedLoadAction(im, MVT::i32, Legal);
- setIndexedStoreAction(im, MVT::i1, Legal);
- setIndexedStoreAction(im, MVT::i8, Legal);
- setIndexedStoreAction(im, MVT::i16, Legal);
- setIndexedStoreAction(im, MVT::i32, Legal);
+ setIndexedLoadAction(im, EVT::i1, Legal);
+ setIndexedLoadAction(im, EVT::i8, Legal);
+ setIndexedLoadAction(im, EVT::i16, Legal);
+ setIndexedLoadAction(im, EVT::i32, Legal);
+ setIndexedStoreAction(im, EVT::i1, Legal);
+ setIndexedStoreAction(im, EVT::i8, Legal);
+ setIndexedStoreAction(im, EVT::i16, Legal);
+ setIndexedStoreAction(im, EVT::i32, Legal);
}
}
// i64 operation support.
if (Subtarget->isThumb1Only()) {
- setOperationAction(ISD::MUL, MVT::i64, Expand);
- setOperationAction(ISD::MULHU, MVT::i32, Expand);
- setOperationAction(ISD::MULHS, MVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::MUL, EVT::i64, Expand);
+ setOperationAction(ISD::MULHU, EVT::i32, Expand);
+ setOperationAction(ISD::MULHS, EVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
} else {
- setOperationAction(ISD::MUL, MVT::i64, Expand);
- setOperationAction(ISD::MULHU, MVT::i32, Expand);
+ setOperationAction(ISD::MUL, EVT::i64, Expand);
+ setOperationAction(ISD::MULHU, EVT::i32, Expand);
if (!Subtarget->hasV6Ops())
- setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::MULHS, EVT::i32, Expand);
}
- setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRL, MVT::i64, Custom);
- setOperationAction(ISD::SRA, MVT::i64, Custom);
+ setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SRL, EVT::i64, Custom);
+ setOperationAction(ISD::SRA, EVT::i64, Custom);
// ARM does not have ROTL.
- setOperationAction(ISD::ROTL, MVT::i32, Expand);
- setOperationAction(ISD::CTTZ, MVT::i32, Expand);
- setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::ROTL, EVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, EVT::i32, Expand);
if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
- setOperationAction(ISD::CTLZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, EVT::i32, Expand);
// Only ARMv6 has BSWAP.
if (!Subtarget->hasV6Ops())
- setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, EVT::i32, Expand);
// These are expanded into libcalls.
- setOperationAction(ISD::SDIV, MVT::i32, Expand);
- setOperationAction(ISD::UDIV, MVT::i32, Expand);
- setOperationAction(ISD::SREM, MVT::i32, Expand);
- setOperationAction(ISD::UREM, MVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, EVT::i32, Expand);
+ setOperationAction(ISD::UDIV, EVT::i32, Expand);
+ setOperationAction(ISD::SREM, EVT::i32, Expand);
+ setOperationAction(ISD::UREM, EVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
- setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
- setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
+ setOperationAction(ISD::GLOBAL_OFFSET_TABLE, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
// Use the default implementation.
- setOperationAction(ISD::VASTART, MVT::Other, Custom);
- setOperationAction(ISD::VAARG, MVT::Other, Expand);
- setOperationAction(ISD::VACOPY, MVT::Other, Expand);
- setOperationAction(ISD::VAEND, MVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::VASTART, EVT::Other, Custom);
+ setOperationAction(ISD::VAARG, EVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, EVT::Other, Expand);
+ setOperationAction(ISD::VAEND, EVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
if (Subtarget->isThumb())
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
else
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
- setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand);
+ setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand);
}
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
// Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
- setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
+ setOperationAction(ISD::BIT_CONVERT, EVT::i64, Custom);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
- setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
-
- setOperationAction(ISD::SETCC, MVT::i32, Expand);
- setOperationAction(ISD::SETCC, MVT::f32, Expand);
- setOperationAction(ISD::SETCC, MVT::f64, Expand);
- setOperationAction(ISD::SELECT, MVT::i32, Expand);
- setOperationAction(ISD::SELECT, MVT::f32, Expand);
- setOperationAction(ISD::SELECT, MVT::f64, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
-
- setOperationAction(ISD::BRCOND, MVT::Other, Expand);
- setOperationAction(ISD::BR_CC, MVT::i32, Custom);
- setOperationAction(ISD::BR_CC, MVT::f32, Custom);
- setOperationAction(ISD::BR_CC, MVT::f64, Custom);
- setOperationAction(ISD::BR_JT, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_W_CHAIN, EVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_VOID, EVT::Other, Custom);
+
+ setOperationAction(ISD::SETCC, EVT::i32, Expand);
+ setOperationAction(ISD::SETCC, EVT::f32, Expand);
+ setOperationAction(ISD::SETCC, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT, EVT::i32, Expand);
+ setOperationAction(ISD::SELECT, EVT::f32, Expand);
+ setOperationAction(ISD::SELECT, EVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, EVT::f32, Custom);
+ setOperationAction(ISD::SELECT_CC, EVT::f64, Custom);
+
+ setOperationAction(ISD::BRCOND, EVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, EVT::i32, Custom);
+ setOperationAction(ISD::BR_CC, EVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, EVT::f64, Custom);
+ setOperationAction(ISD::BR_JT, EVT::Other, Custom);
// We don't support sin/cos/fmod/copysign/pow
- setOperationAction(ISD::FSIN, MVT::f64, Expand);
- setOperationAction(ISD::FSIN, MVT::f32, Expand);
- setOperationAction(ISD::FCOS, MVT::f32, Expand);
- setOperationAction(ISD::FCOS, MVT::f64, Expand);
- setOperationAction(ISD::FREM, MVT::f64, Expand);
- setOperationAction(ISD::FREM, MVT::f32, Expand);
+ setOperationAction(ISD::FSIN, EVT::f64, Expand);
+ setOperationAction(ISD::FSIN, EVT::f32, Expand);
+ setOperationAction(ISD::FCOS, EVT::f32, Expand);
+ setOperationAction(ISD::FCOS, EVT::f64, Expand);
+ setOperationAction(ISD::FREM, EVT::f64, Expand);
+ setOperationAction(ISD::FREM, EVT::f32, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f64, Custom);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom);
}
- setOperationAction(ISD::FPOW, MVT::f64, Expand);
- setOperationAction(ISD::FPOW, MVT::f32, Expand);
+ setOperationAction(ISD::FPOW, EVT::f64, Expand);
+ setOperationAction(ISD::FPOW, EVT::f32, Expand);
// int <-> fp are custom expanded into bit_convert + ARMISD ops.
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
- setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
- setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
- setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
+ setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
}
// We have target-specific dag combine patterns for the following nodes:
@@ -549,7 +549,7 @@
#include "ARMGenCallingConv.inc"
// APCS f64 is in register pairs, possibly split to stack
-static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
CCState &State, bool CanFail) {
static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
@@ -579,20 +579,20 @@
return true;
}
-static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State) {
if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
return false;
- if (LocVT == MVT::v2f64 &&
+ if (LocVT == EVT::v2f64 &&
!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
return false;
return true; // we handled it
}
// AAPCS f64 is in aligned register pairs
-static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
CCState &State, bool CanFail) {
static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
@@ -622,19 +622,19 @@
return true;
}
-static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State) {
if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
return false;
- if (LocVT == MVT::v2f64 &&
+ if (LocVT == EVT::v2f64 &&
!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
return false;
return true; // we handled it
}
-static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo, CCState &State) {
static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
@@ -654,18 +654,18 @@
return true;
}
-static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State) {
if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
return false;
- if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
+ if (LocVT == EVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
return false;
return true; // we handled it
}
-static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags,
CCState &State) {
@@ -725,33 +725,33 @@
SDValue Val;
if (VA.needsCustom()) {
// Handle f64 or half of a v2f64.
- SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
+ SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32,
InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
VA = RVLocs[++i]; // skip ahead to next loc
- SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
+ SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32,
InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
- Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
+ Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
- if (VA.getLocVT() == MVT::v2f64) {
- SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
- Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
- DAG.getConstant(0, MVT::i32));
+ if (VA.getLocVT() == EVT::v2f64) {
+ SDValue Vec = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64);
+ Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val,
+ DAG.getConstant(0, EVT::i32));
VA = RVLocs[++i]; // skip ahead to next loc
- Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
+ Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag);
Chain = Lo.getValue(1);
InFlag = Lo.getValue(2);
VA = RVLocs[++i]; // skip ahead to next loc
- Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
+ Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag);
Chain = Hi.getValue(1);
InFlag = Hi.getValue(2);
- Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
- DAG.getConstant(1, MVT::i32));
+ Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val,
+ DAG.getConstant(1, EVT::i32));
}
} else {
Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
@@ -784,7 +784,7 @@
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
DebugLoc dl) {
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*AlwaysInline=*/false, NULL, 0, NULL, 0);
}
@@ -815,7 +815,7 @@
ISD::ArgFlagsTy Flags) {
SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(MVT::i32, MVT::i32), Arg);
+ DAG.getVTList(EVT::i32, EVT::i32), Arg);
RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
if (NextVA.isRegLoc())
@@ -858,7 +858,7 @@
// These operations are automatically eliminated by the prolog/epilog pass
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
- SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
+ SDValue StackPtr = DAG.getRegister(ARM::SP, EVT::i32);
RegsToPassVector RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
@@ -892,11 +892,11 @@
// f64 and v2f64 might be passed in i32 pairs and must be split into pieces
if (VA.needsCustom()) {
- if (VA.getLocVT() == MVT::v2f64) {
- SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
- DAG.getConstant(0, MVT::i32));
- SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
- DAG.getConstant(1, MVT::i32));
+ if (VA.getLocVT() == EVT::v2f64) {
+ SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
+ DAG.getConstant(0, EVT::i32));
+ SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
+ DAG.getConstant(1, EVT::i32));
PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
@@ -930,7 +930,7 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
@@ -962,10 +962,10 @@
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
getPointerTy(), Callee, PICLabel);
} else
@@ -981,10 +981,10 @@
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
Callee = DAG.getLoad(getPointerTy(), dl,
DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
getPointerTy(), Callee, PICLabel);
} else
@@ -1005,7 +1005,7 @@
}
if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
- Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(EVT::i32),InFlag);
InFlag = Chain.getValue(1);
}
@@ -1022,7 +1022,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
@@ -1082,12 +1082,12 @@
}
if (VA.needsCustom()) {
- if (VA.getLocVT() == MVT::v2f64) {
+ if (VA.getLocVT() == EVT::v2f64) {
// Extract the first half and return it in two registers.
- SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
- DAG.getConstant(0, MVT::i32));
+ SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
+ DAG.getConstant(0, EVT::i32));
SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(MVT::i32, MVT::i32), Half);
+ DAG.getVTList(EVT::i32, EVT::i32), Half);
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
Flag = Chain.getValue(1);
@@ -1098,13 +1098,13 @@
VA = RVLocs[++i]; // skip ahead to next loc
// Extract the 2nd half and fall through to handle it as an f64 value.
- Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
- DAG.getConstant(1, MVT::i32));
+ Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg,
+ DAG.getConstant(1, EVT::i32));
}
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
// available.
SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
+ DAG.getVTList(EVT::i32, EVT::i32), &Arg, 1);
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
Flag = Chain.getValue(1);
VA = RVLocs[++i]; // skip ahead to next loc
@@ -1120,9 +1120,9 @@
SDValue result;
if (Flag.getNode())
- result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
+ result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
else // Return Void
- result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
+ result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain);
return result;
}
@@ -1134,7 +1134,7 @@
// be used to form addressing mode. These wrapped nodes will be selected
// into MOVi.
static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
- MVT PtrVT = Op.getValueType();
+ EVT PtrVT = Op.getValueType();
// FIXME there is no actual debug info here
DebugLoc dl = Op.getDebugLoc();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
@@ -1145,7 +1145,7 @@
else
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
- return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
+ return DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Res);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model
@@ -1153,17 +1153,17 @@
ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
DebugLoc dl = GA->getDebugLoc();
- MVT PtrVT = getPointerTy();
+ EVT PtrVT = getPointerTy();
unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "tlsgd", true);
SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
+ Argument = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Argument);
Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
SDValue Chain = Argument.getValue(1);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
// call __tls_get_addr.
@@ -1189,7 +1189,7 @@
DebugLoc dl = GA->getDebugLoc();
SDValue Offset;
SDValue Chain = DAG.getEntryNode();
- MVT PtrVT = getPointerTy();
+ EVT PtrVT = getPointerTy();
// Get the Thread Pointer
SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
@@ -1200,11 +1200,11 @@
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "gottpoff", true);
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
Chain = Offset.getValue(1);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
@@ -1213,7 +1213,7 @@
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset);
Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
}
@@ -1238,7 +1238,7 @@
SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
SelectionDAG &DAG) {
- MVT PtrVT = getPointerTy();
+ EVT PtrVT = getPointerTy();
DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
@@ -1247,7 +1247,7 @@
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
@@ -1258,7 +1258,7 @@
return Result;
} else {
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
}
}
@@ -1276,7 +1276,7 @@
SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
SelectionDAG &DAG) {
- MVT PtrVT = getPointerTy();
+ EVT PtrVT = getPointerTy();
DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
@@ -1293,13 +1293,13 @@
Kind, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
}
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
if (IsIndirect)
@@ -1312,23 +1312,23 @@
SelectionDAG &DAG){
assert(Subtarget->isTargetELF() &&
"GLOBAL OFFSET TABLE not implemented for non-ELF targets");
- MVT PtrVT = getPointerTy();
+ EVT PtrVT = getPointerTy();
DebugLoc dl = Op.getDebugLoc();
unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
ARMPCLabelIndex,
ARMCP::CPValue, PCAdj);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
- CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
- SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
+ SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned Opcode) {
SDNode *Node = Op.getNode();
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
DebugLoc dl = Op.getDebugLoc();
if (!VT.is64BitVector())
@@ -1342,7 +1342,7 @@
static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned Opcode, unsigned NumVecs) {
SDNode *Node = Op.getNode();
- MVT VT = Node->getOperand(3).getValueType();
+ EVT VT = Node->getOperand(3).getValueType();
DebugLoc dl = Op.getDebugLoc();
if (!VT.is64BitVector())
@@ -1353,7 +1353,7 @@
Ops.push_back(Node->getOperand(2));
for (unsigned N = 0; N < NumVecs; ++N)
Ops.push_back(Node->getOperand(N + 3));
- return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
+ return DAG.getNode(Opcode, dl, EVT::Other, Ops.data(), Ops.size());
}
SDValue
@@ -1389,11 +1389,11 @@
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::arm_thread_pointer: {
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
}
case Intrinsic::eh_sjlj_setjmp:
- return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
+ return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, EVT::i32, Op.getOperand(1));
}
}
@@ -1402,7 +1402,7 @@
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
DebugLoc dl = Op.getDebugLoc();
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
@@ -1412,7 +1412,7 @@
ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc();
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
@@ -1445,7 +1445,7 @@
Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
}
- SDVTList VTList = DAG.getVTList(VT, MVT::Other);
+ SDVTList VTList = DAG.getVTList(VT, EVT::Other);
SDValue Ops1[] = { Chain, Size, Align };
SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
Chain = Res.getValue(1);
@@ -1470,7 +1470,7 @@
// Transform the arguments stored in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
- SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
+ SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32);
SDValue ArgValue2;
if (NextVA.isMemLoc()) {
@@ -1480,13 +1480,13 @@
// Create load node to retrieve arguments from the stack.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
+ ArgValue2 = DAG.getLoad(EVT::i32, dl, Root, FIN, NULL, 0);
} else {
Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
- ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
+ ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32);
}
- return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
+ return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, ArgValue, ArgValue2);
}
SDValue
@@ -1517,24 +1517,24 @@
// Arguments stored in registers.
if (VA.isRegLoc()) {
- MVT RegVT = VA.getLocVT();
+ EVT RegVT = VA.getLocVT();
SDValue ArgValue;
if (VA.needsCustom()) {
// f64 and vector types are split up into multiple registers or
// combinations of registers and stack slots.
- RegVT = MVT::i32;
+ RegVT = EVT::i32;
- if (VA.getLocVT() == MVT::v2f64) {
+ if (VA.getLocVT() == EVT::v2f64) {
SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
VA = ArgLocs[++i]; // skip ahead to next loc
SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
Chain, DAG, dl);
- ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
- ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
+ ArgValue = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64);
+ ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64,
ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
- ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
+ ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64,
ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
} else
ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
@@ -1542,13 +1542,13 @@
} else {
TargetRegisterClass *RC;
- if (RegVT == MVT::f32)
+ if (RegVT == EVT::f32)
RC = ARM::SPRRegisterClass;
- else if (RegVT == MVT::f64)
+ else if (RegVT == EVT::f64)
RC = ARM::DPRRegisterClass;
- else if (RegVT == MVT::v2f64)
+ else if (RegVT == EVT::v2f64)
RC = ARM::QPRRegisterClass;
- else if (RegVT == MVT::i32)
+ else if (RegVT == EVT::i32)
RC = (AFI->isThumb1OnlyFunction() ?
ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
else
@@ -1586,7 +1586,7 @@
// sanity check
assert(VA.isMemLoc());
- assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
+ assert(VA.getValVT() != EVT::i64 && "i64 should already be lowered");
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
@@ -1629,14 +1629,14 @@
RC = ARM::GPRRegisterClass;
unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
- SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
DAG.getConstant(4, getPointerTy()));
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOps[0], MemOps.size());
} else
// This will point to the next argument passed via stack.
@@ -1682,28 +1682,28 @@
case ISD::SETGE:
if (isLegalCmpImmediate(C-1, isThumb1Only)) {
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
- RHS = DAG.getConstant(C-1, MVT::i32);
+ RHS = DAG.getConstant(C-1, EVT::i32);
}
break;
case ISD::SETULT:
case ISD::SETUGE:
if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
- RHS = DAG.getConstant(C-1, MVT::i32);
+ RHS = DAG.getConstant(C-1, EVT::i32);
}
break;
case ISD::SETLE:
case ISD::SETGT:
if (isLegalCmpImmediate(C+1, isThumb1Only)) {
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
- RHS = DAG.getConstant(C+1, MVT::i32);
+ RHS = DAG.getConstant(C+1, EVT::i32);
}
break;
case ISD::SETULE:
case ISD::SETUGT:
if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
- RHS = DAG.getConstant(C+1, MVT::i32);
+ RHS = DAG.getConstant(C+1, EVT::i32);
}
break;
}
@@ -1722,8 +1722,8 @@
CompareType = ARMISD::CMPZ;
break;
}
- ARMCC = DAG.getConstant(CondCode, MVT::i32);
- return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
+ ARMCC = DAG.getConstant(CondCode, EVT::i32);
+ return DAG.getNode(CompareType, dl, EVT::Flag, LHS, RHS);
}
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
@@ -1731,15 +1731,15 @@
DebugLoc dl) {
SDValue Cmp;
if (!isFloatingPointZero(RHS))
- Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
+ Cmp = DAG.getNode(ARMISD::CMPFP, dl, EVT::Flag, LHS, RHS);
else
- Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
- return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
+ Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, EVT::Flag, LHS);
+ return DAG.getNode(ARMISD::FMSTAT, dl, EVT::Flag, Cmp);
}
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
@@ -1747,9 +1747,9 @@
SDValue FalseVal = Op.getOperand(3);
DebugLoc dl = Op.getDebugLoc();
- if (LHS.getValueType() == MVT::i32) {
+ if (LHS.getValueType() == EVT::i32) {
SDValue ARMCC;
- SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
}
@@ -1758,13 +1758,13 @@
if (FPCCToARMCC(CC, CondCode, CondCode2))
std::swap(TrueVal, FalseVal);
- SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
- SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
+ SDValue ARMCC2 = DAG.getConstant(CondCode2, EVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
Result = DAG.getNode(ARMISD::CMOV, dl, VT,
@@ -1782,28 +1782,28 @@
SDValue Dest = Op.getOperand(4);
DebugLoc dl = Op.getDebugLoc();
- if (LHS.getValueType() == MVT::i32) {
+ if (LHS.getValueType() == EVT::i32) {
SDValue ARMCC;
- SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
- return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
+ return DAG.getNode(ARMISD::BRCOND, dl, EVT::Other,
Chain, Dest, ARMCC, CCR,Cmp);
}
- assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
+ assert(LHS.getValueType() == EVT::f32 || LHS.getValueType() == EVT::f64);
ARMCC::CondCodes CondCode, CondCode2;
if (FPCCToARMCC(CC, CondCode, CondCode2))
// Swap the LHS/RHS of the comparison if needed.
std::swap(LHS, RHS);
SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
- SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
+ SDVTList VTList = DAG.getVTList(EVT::Other, EVT::Flag);
SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
if (CondCode2 != ARMCC::AL) {
- ARMCC = DAG.getConstant(CondCode2, MVT::i32);
+ ARMCC = DAG.getConstant(CondCode2, EVT::i32);
SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
}
@@ -1816,12 +1816,12 @@
SDValue Index = Op.getOperand(2);
DebugLoc dl = Op.getDebugLoc();
- MVT PTy = getPointerTy();
+ EVT PTy = getPointerTy();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
- Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
+ Table = DAG.getNode(ARMISD::WrapperJT, dl, EVT::i32, JTI, UId);
Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
if (Subtarget->isThumb2()) {
@@ -1829,18 +1829,18 @@
// which does another jump to the destination. This also makes it easier
// to translate it to TBB / TBH later.
// FIXME: This might not work if the function is extremely large.
- return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
+ return DAG.getNode(ARMISD::BR2_JT, dl, EVT::Other, Chain,
Addr, Op.getOperand(2), JTI, UId);
}
if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
- Addr = DAG.getLoad((MVT)MVT::i32, dl, Chain, Addr, NULL, 0);
+ Addr = DAG.getLoad((EVT)EVT::i32, dl, Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
- return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
+ return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId);
} else {
Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
- return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
+ return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId);
}
}
@@ -1848,17 +1848,17 @@
DebugLoc dl = Op.getDebugLoc();
unsigned Opc =
Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
- Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ Op = DAG.getNode(Opc, dl, EVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
}
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
unsigned Opc =
Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
- Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Op.getOperand(0));
return DAG.getNode(Opc, dl, VT, Op);
}
@@ -1867,19 +1867,19 @@
SDValue Tmp0 = Op.getOperand(0);
SDValue Tmp1 = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
- MVT VT = Op.getValueType();
- MVT SrcVT = Tmp1.getValueType();
+ EVT VT = Op.getValueType();
+ EVT SrcVT = Tmp1.getValueType();
SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
- SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
- SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue ARMCC = DAG.getConstant(ARMCC::LT, EVT::i32);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32);
return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true);
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
@@ -1914,7 +1914,7 @@
unsigned BytesLeft = SizeVal & 3;
unsigned NumMemOps = SizeVal >> 2;
unsigned EmittedNumMemOps = 0;
- MVT VT = MVT::i32;
+ EVT VT = EVT::i32;
unsigned VTSize = 4;
unsigned i = 0;
const unsigned MAX_LOADS_IN_LDM = 6;
@@ -1929,23 +1929,23 @@
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
Loads[i] = DAG.getLoad(VT, dl, Chain,
- DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
- DAG.getConstant(SrcOff, MVT::i32)),
+ DAG.getNode(ISD::ADD, dl, EVT::i32, Src,
+ DAG.getConstant(SrcOff, EVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
- DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
- DAG.getConstant(DstOff, MVT::i32)),
+ DAG.getNode(ISD::ADD, dl, EVT::i32, Dst,
+ DAG.getConstant(DstOff, EVT::i32)),
DstSV, DstSVOff + DstOff);
DstOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
EmittedNumMemOps += i;
}
@@ -1958,69 +1958,69 @@
i = 0;
while (BytesLeft) {
if (BytesLeft >= 2) {
- VT = MVT::i16;
+ VT = EVT::i16;
VTSize = 2;
} else {
- VT = MVT::i8;
+ VT = EVT::i8;
VTSize = 1;
}
Loads[i] = DAG.getLoad(VT, dl, Chain,
- DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
- DAG.getConstant(SrcOff, MVT::i32)),
+ DAG.getNode(ISD::ADD, dl, EVT::i32, Src,
+ DAG.getConstant(SrcOff, EVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
++i;
SrcOff += VTSize;
BytesLeft -= VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
i = 0;
BytesLeft = BytesLeftSave;
while (BytesLeft) {
if (BytesLeft >= 2) {
- VT = MVT::i16;
+ VT = EVT::i16;
VTSize = 2;
} else {
- VT = MVT::i8;
+ VT = EVT::i8;
VTSize = 1;
}
TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
- DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
- DAG.getConstant(DstOff, MVT::i32)),
+ DAG.getNode(ISD::ADD, dl, EVT::i32, Dst,
+ DAG.getConstant(DstOff, EVT::i32)),
DstSV, DstSVOff + DstOff);
++i;
DstOff += VTSize;
BytesLeft -= VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i);
}
static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
SDValue Op = N->getOperand(0);
DebugLoc dl = N->getDebugLoc();
- if (N->getValueType(0) == MVT::f64) {
+ if (N->getValueType(0) == EVT::f64) {
// Turn i64->f64 into FMDRR.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
- DAG.getConstant(0, MVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
- DAG.getConstant(1, MVT::i32));
- return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op,
+ DAG.getConstant(0, EVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op,
+ DAG.getConstant(1, EVT::i32));
+ return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi);
}
// Turn f64->i64 into FMRRD.
SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
- DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
+ DAG.getVTList(EVT::i32, EVT::i32), &Op, 1);
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
+ return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Cvt, Cvt.getValue(1));
}
/// getZeroVector - Returns a vector of specified type with all zero elements.
///
-static SDValue getZeroVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
+static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
// Zero vectors are used to represent vector negation and in those cases
@@ -2030,35 +2030,35 @@
// the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
// to their dest type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
+ SDValue Cst = DAG.getTargetConstant(0, EVT::i32);
if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
/// getOnesVector - Returns a vector of specified type with all bits set.
///
-static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
+static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
// type. This ensures they get CSE'd.
SDValue Vec;
- SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
+ SDValue Cst = DAG.getTargetConstant(~0U, EVT::i32);
if (VT.getSizeInBits() == 64)
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst);
else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *ST) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// Lower vector shifts on NEON to use VSHL.
@@ -2068,7 +2068,7 @@
// Left shifts translate directly to the vshiftu intrinsic.
if (N->getOpcode() == ISD::SHL)
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
+ DAG.getConstant(Intrinsic::arm_neon_vshiftu, EVT::i32),
N->getOperand(0), N->getOperand(1));
assert((N->getOpcode() == ISD::SRA ||
@@ -2077,7 +2077,7 @@
// NEON uses the same intrinsics for both left and right shifts. For
// right shifts, the shift amounts are negative, so negate the vector of
// shift amounts.
- MVT ShiftVT = N->getOperand(1).getValueType();
+ EVT ShiftVT = N->getOperand(1).getValueType();
SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
getZeroVector(ShiftVT, DAG, dl),
N->getOperand(1));
@@ -2085,11 +2085,11 @@
Intrinsic::arm_neon_vshifts :
Intrinsic::arm_neon_vshiftu);
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
- DAG.getConstant(vshiftInt, MVT::i32),
+ DAG.getConstant(vshiftInt, EVT::i32),
N->getOperand(0), NegatedCount);
}
- assert(VT == MVT::i64 &&
+ assert(VT == EVT::i64 &&
(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
"Unknown shift to lower!");
@@ -2102,21 +2102,21 @@
if (ST->isThumb1Only()) return SDValue();
// Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
- DAG.getConstant(0, MVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
- DAG.getConstant(1, MVT::i32));
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0),
+ DAG.getConstant(0, EVT::i32));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0),
+ DAG.getConstant(1, EVT::i32));
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
// captures the result into a carry flag.
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
- Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
+ Hi = DAG.getNode(Opc, dl, DAG.getVTList(EVT::i32, EVT::Flag), &Hi, 1);
// The low part is an ARMISD::RRX operand, which shifts the carry in.
- Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
+ Lo = DAG.getNode(ARMISD::RRX, dl, EVT::i32, Lo, Hi.getValue(1));
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Lo, Hi);
}
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
@@ -2128,7 +2128,7 @@
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
SDValue CC = Op.getOperand(2);
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
DebugLoc dl = Op.getDebugLoc();
@@ -2227,13 +2227,13 @@
case 8:
// Any 1-byte value is OK.
assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
- return DAG.getTargetConstant(SplatBits, MVT::i8);
+ return DAG.getTargetConstant(SplatBits, EVT::i8);
case 16:
// NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
if ((SplatBits & ~0xff) == 0 ||
(SplatBits & ~0xff00) == 0)
- return DAG.getTargetConstant(SplatBits, MVT::i16);
+ return DAG.getTargetConstant(SplatBits, EVT::i16);
break;
case 32:
@@ -2245,15 +2245,15 @@
(SplatBits & ~0xff00) == 0 ||
(SplatBits & ~0xff0000) == 0 ||
(SplatBits & ~0xff000000) == 0)
- return DAG.getTargetConstant(SplatBits, MVT::i32);
+ return DAG.getTargetConstant(SplatBits, EVT::i32);
if ((SplatBits & ~0xffff) == 0 &&
((SplatBits | SplatUndef) & 0xff) == 0xff)
- return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
+ return DAG.getTargetConstant(SplatBits | 0xff, EVT::i32);
if ((SplatBits & ~0xffffff) == 0 &&
((SplatBits | SplatUndef) & 0xffff) == 0xffff)
- return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
+ return DAG.getTargetConstant(SplatBits | 0xffff, EVT::i32);
// Note: there are a few 32-bit splat values (specifically: 00ffff00,
// ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
@@ -2273,7 +2273,7 @@
return SDValue();
BitMask <<= 8;
}
- return DAG.getTargetConstant(Val, MVT::i64);
+ return DAG.getTargetConstant(Val, EVT::i64);
}
default:
@@ -2311,7 +2311,7 @@
assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
"Only possible block sizes for VREV are: 16, 32, 64");
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
unsigned NumElts = VT.getVectorNumElements();
unsigned EltSz = VT.getVectorElementType().getSizeInBits();
unsigned BlockElts = N->getMaskElt(0) + 1;
@@ -2328,7 +2328,7 @@
return true;
}
-static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) {
+static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
// Canonicalize all-zeros and all-ones vectors.
ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
if (ConstVal->isNullValue())
@@ -2336,22 +2336,22 @@
if (ConstVal->isAllOnesValue())
return getOnesVector(VT, DAG, dl);
- MVT CanonicalVT;
+ EVT CanonicalVT;
if (VT.is64BitVector()) {
switch (Val.getValueType().getSizeInBits()) {
- case 8: CanonicalVT = MVT::v8i8; break;
- case 16: CanonicalVT = MVT::v4i16; break;
- case 32: CanonicalVT = MVT::v2i32; break;
- case 64: CanonicalVT = MVT::v1i64; break;
+ case 8: CanonicalVT = EVT::v8i8; break;
+ case 16: CanonicalVT = EVT::v4i16; break;
+ case 32: CanonicalVT = EVT::v2i32; break;
+ case 64: CanonicalVT = EVT::v1i64; break;
default: llvm_unreachable("unexpected splat element type"); break;
}
} else {
assert(VT.is128BitVector() && "unknown splat vector size");
switch (Val.getValueType().getSizeInBits()) {
- case 8: CanonicalVT = MVT::v16i8; break;
- case 16: CanonicalVT = MVT::v8i16; break;
- case 32: CanonicalVT = MVT::v4i32; break;
- case 64: CanonicalVT = MVT::v2i64; break;
+ case 8: CanonicalVT = EVT::v16i8; break;
+ case 16: CanonicalVT = EVT::v8i16; break;
+ case 32: CanonicalVT = EVT::v4i32; break;
+ case 64: CanonicalVT = EVT::v2i64; break;
default: llvm_unreachable("unexpected splat element type"); break;
}
}
@@ -2370,7 +2370,7 @@
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
DebugLoc dl = Op.getDebugLoc();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
APInt SplatBits, SplatUndef;
unsigned SplatBitSize;
@@ -2411,14 +2411,14 @@
}
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- assert((VT == MVT::i8 || VT == MVT::i16) &&
+ assert((VT == EVT::i8 || VT == EVT::i16) &&
"unexpected type for custom-lowering vector extract");
SDValue Vec = Op.getOperand(0);
SDValue Lane = Op.getOperand(1);
- Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
- Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
+ Op = DAG.getNode(ARMISD::VGETLANEu, dl, EVT::i32, Vec, Lane);
+ Op = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Op, DAG.getValueType(VT));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
}
@@ -2428,16 +2428,16 @@
assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
"unexpected CONCAT_VECTORS");
DebugLoc dl = Op.getDebugLoc();
- SDValue Val = DAG.getUNDEF(MVT::v2f64);
+ SDValue Val = DAG.getUNDEF(EVT::v2f64);
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
if (Op0.getOpcode() != ISD::UNDEF)
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op0),
DAG.getIntPtrConstant(0));
if (Op1.getOpcode() != ISD::UNDEF)
- Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
+ Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val,
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op1),
DAG.getIntPtrConstant(1));
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
}
@@ -2652,7 +2652,7 @@
TargetLowering::DAGCombinerInfo &DCI) {
SelectionDAG &DAG = DCI.DAG;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
unsigned Opc = N->getOpcode();
bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
@@ -2680,7 +2680,7 @@
cast<ConstantSDNode>(RHS)->isNullValue()) {
std::swap(LHS, RHS);
SDValue Op0 = Slct.getOperand(0);
- MVT OpVT = isSlctCC ? Op0.getValueType() :
+ EVT OpVT = isSlctCC ? Op0.getValueType() :
Op0.getOperand(0).getValueType();
bool isInt = OpVT.isInteger();
CC = ISD::getSetCCInverse(CC, isInt);
@@ -2775,7 +2775,7 @@
/// operand of a vector shift left operation. That value must be in the range:
/// 0 <= Value < ElementBits for a left shift; or
/// 0 <= Value <= ElementBits for a long left shift.
-static bool isVShiftLImm(SDValue Op, MVT VT, bool isLong, int64_t &Cnt) {
+static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
assert(VT.isVector() && "vector shift count is not a vector type");
unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
if (! getVShiftImm(Op, ElementBits, Cnt))
@@ -2789,7 +2789,7 @@
/// absolute value must be in the range:
/// 1 <= |Value| <= ElementBits for a right shift; or
/// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
-static bool isVShiftRImm(SDValue Op, MVT VT, bool isNarrow, bool isIntrinsic,
+static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
int64_t &Cnt) {
assert(VT.isVector() && "vector shift count is not a vector type");
unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
@@ -2830,7 +2830,7 @@
case Intrinsic::arm_neon_vqrshiftns:
case Intrinsic::arm_neon_vqrshiftnu:
case Intrinsic::arm_neon_vqrshiftnsu: {
- MVT VT = N->getOperand(1).getValueType();
+ EVT VT = N->getOperand(1).getValueType();
int64_t Cnt;
unsigned VShiftOpc = 0;
@@ -2930,11 +2930,11 @@
}
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
- N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
+ N->getOperand(1), DAG.getConstant(Cnt, EVT::i32));
}
case Intrinsic::arm_neon_vshiftins: {
- MVT VT = N->getOperand(1).getValueType();
+ EVT VT = N->getOperand(1).getValueType();
int64_t Cnt;
unsigned VShiftOpc = 0;
@@ -2948,7 +2948,7 @@
return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
N->getOperand(1), N->getOperand(2),
- DAG.getConstant(Cnt, MVT::i32));
+ DAG.getConstant(Cnt, EVT::i32));
}
case Intrinsic::arm_neon_vqrshifts:
@@ -2967,7 +2967,7 @@
/// their values after they get legalized to loads from a constant pool.
static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *ST) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// Nothing to be done for scalar shifts.
if (! VT.isVector())
@@ -2982,7 +2982,7 @@
case ISD::SHL:
if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
- DAG.getConstant(Cnt, MVT::i32));
+ DAG.getConstant(Cnt, EVT::i32));
break;
case ISD::SRA:
@@ -2991,7 +2991,7 @@
unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
ARMISD::VSHRs : ARMISD::VSHRu);
return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
- DAG.getConstant(Cnt, MVT::i32));
+ DAG.getConstant(Cnt, EVT::i32));
}
}
return SDValue();
@@ -3010,12 +3010,12 @@
if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
SDValue Vec = N0.getOperand(0);
SDValue Lane = N0.getOperand(1);
- MVT VT = N->getValueType(0);
- MVT EltVT = N0.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = N0.getValueType();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (VT == MVT::i32 &&
- (EltVT == MVT::i8 || EltVT == MVT::i16) &&
+ if (VT == EVT::i32 &&
+ (EltVT == EVT::i8 || EltVT == EVT::i16) &&
TLI.isTypeLegal(Vec.getValueType())) {
unsigned Opc = 0;
@@ -3060,7 +3060,7 @@
/// isLegalAddressImmediate - Return true if the integer value can be used
/// as the offset of the target addressing mode for load / store of the
/// given type.
-static bool isLegalAddressImmediate(int64_t V, MVT VT,
+static bool isLegalAddressImmediate(int64_t V, EVT VT,
const ARMSubtarget *Subtarget) {
if (V == 0)
return true;
@@ -3075,15 +3075,15 @@
unsigned Scale = 1;
switch (VT.getSimpleVT()) {
default: return false;
- case MVT::i1:
- case MVT::i8:
+ case EVT::i1:
+ case EVT::i8:
// Scale == 1;
break;
- case MVT::i16:
+ case EVT::i16:
// Scale == 2;
Scale = 2;
break;
- case MVT::i32:
+ case EVT::i32:
// Scale == 4;
Scale = 4;
break;
@@ -3099,16 +3099,16 @@
V = - V;
switch (VT.getSimpleVT()) {
default: return false;
- case MVT::i1:
- case MVT::i8:
- case MVT::i32:
+ case EVT::i1:
+ case EVT::i8:
+ case EVT::i32:
// +- imm12
return V == (V & ((1LL << 12) - 1));
- case MVT::i16:
+ case EVT::i16:
// +- imm8
return V == (V & ((1LL << 8) - 1));
- case MVT::f32:
- case MVT::f64:
+ case EVT::f32:
+ case EVT::f64:
if (!Subtarget->hasVFP2())
return false;
if ((V & 3) != 0)
@@ -3122,7 +3122,7 @@
/// by AM is legal for this target, for a load/store of the specified type.
bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
const Type *Ty) const {
- MVT VT = getValueType(Ty, true);
+ EVT VT = getValueType(Ty, true);
if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
return false;
@@ -3148,10 +3148,10 @@
int Scale = AM.Scale;
switch (VT.getSimpleVT()) {
default: return false;
- case MVT::i1:
- case MVT::i8:
- case MVT::i32:
- case MVT::i64:
+ case EVT::i1:
+ case EVT::i8:
+ case EVT::i32:
+ case EVT::i64:
// This assumes i64 is legalized to a pair of i32. If not (i.e.
// ldrd / strd are used, then its address mode is same as i16.
// r + r
@@ -3160,13 +3160,13 @@
return true;
// r + r << imm
return isPowerOf2_32(Scale & ~1);
- case MVT::i16:
+ case EVT::i16:
// r + r
if (((unsigned)AM.HasBaseReg + Scale) <= 2)
return true;
return false;
- case MVT::isVoid:
+ case EVT::isVoid:
// Note, we allow "void" uses (basically, uses that aren't loads or
// stores), because arm allows folding a scale into many arithmetic
// operations. This should be made more precise and revisited later.
@@ -3180,14 +3180,14 @@
return true;
}
-static bool getARMIndexedAddressParts(SDNode *Ptr, MVT VT,
+static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
bool isSEXTLoad, SDValue &Base,
SDValue &Offset, bool &isInc,
SelectionDAG &DAG) {
if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
return false;
- if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
+ if (VT == EVT::i16 || ((VT == EVT::i8 || VT == EVT::i1) && isSEXTLoad)) {
// AddressingMode 3
Base = Ptr->getOperand(0);
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
@@ -3202,7 +3202,7 @@
isInc = (Ptr->getOpcode() == ISD::ADD);
Offset = Ptr->getOperand(1);
return true;
- } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
+ } else if (VT == EVT::i32 || VT == EVT::i8 || VT == EVT::i1) {
// AddressingMode 2
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
int RHSC = (int)RHS->getZExtValue();
@@ -3238,7 +3238,7 @@
return false;
}
-static bool getT2IndexedAddressParts(SDNode *Ptr, MVT VT,
+static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
bool isSEXTLoad, SDValue &Base,
SDValue &Offset, bool &isInc,
SelectionDAG &DAG) {
@@ -3274,7 +3274,7 @@
if (Subtarget->isThumb1Only())
return false;
- MVT VT;
+ EVT VT;
SDValue Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
@@ -3313,7 +3313,7 @@
if (Subtarget->isThumb1Only())
return false;
- MVT VT;
+ EVT VT;
SDValue Ptr;
bool isSEXTLoad = false;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
@@ -3383,7 +3383,7 @@
std::pair<unsigned, const TargetRegisterClass*>
ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
switch (Constraint[0]) {
@@ -3395,9 +3395,9 @@
case 'r':
return std::make_pair(0U, ARM::GPRRegisterClass);
case 'w':
- if (VT == MVT::f32)
+ if (VT == EVT::f32)
return std::make_pair(0U, ARM::SPRRegisterClass);
- if (VT == MVT::f64)
+ if (VT == EVT::f64)
return std::make_pair(0U, ARM::DPRRegisterClass);
break;
}
@@ -3407,7 +3407,7 @@
std::vector<unsigned> ARMTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
if (Constraint.size() != 1)
return std::vector<unsigned>();
@@ -3423,7 +3423,7 @@
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R12, ARM::LR, 0);
case 'w':
- if (VT == MVT::f32)
+ if (VT == EVT::f32)
return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
ARM::S4, ARM::S5, ARM::S6, ARM::S7,
ARM::S8, ARM::S9, ARM::S10, ARM::S11,
@@ -3432,7 +3432,7 @@
ARM::S20,ARM::S21,ARM::S22,ARM::S23,
ARM::S24,ARM::S25,ARM::S26,ARM::S27,
ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
- if (VT == MVT::f64)
+ if (VT == EVT::f64)
return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
ARM::D4, ARM::D5, ARM::D6, ARM::D7,
ARM::D8, ARM::D9, ARM::D10,ARM::D11,
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Aug 10 17:56:29 2009
@@ -194,10 +194,10 @@
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
@@ -225,9 +225,9 @@
///
unsigned ARMPCLabelIndex;
- void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
- void addDRTypeForNEON(MVT VT);
- void addQRTypeForNEON(MVT VT);
+ void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
+ void addDRTypeForNEON(EVT VT);
+ void addQRTypeForNEON(EVT VT);
typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Aug 10 17:56:29 2009
@@ -129,13 +129,13 @@
// so_imm_neg_XFORM - Return a so_imm value packed into the format described for
// so_imm_neg def below.
def so_imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32);
}]>;
// so_imm_not_XFORM - Return a so_imm value packed into the format described for
// so_imm_not def below.
def so_imm_not_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
+ return CurDAG->getTargetConstant(~(int)N->getZExtValue(), EVT::i32);
}]>;
// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
@@ -254,12 +254,12 @@
def so_imm2part_1 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
+ return CurDAG->getTargetConstant(V, EVT::i32);
}]>;
def so_imm2part_2 : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
+ return CurDAG->getTargetConstant(V, EVT::i32);
}]>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Aug 10 17:56:29 2009
@@ -277,33 +277,33 @@
// Extract D sub-registers of Q registers.
// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
def DSubReg_i8_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, EVT::i32);
}]>;
def DSubReg_i16_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, EVT::i32);
}]>;
def DSubReg_i32_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, EVT::i32);
}]>;
def DSubReg_f64_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
+ return CurDAG->getTargetConstant(5 + N->getZExtValue(), EVT::i32);
}]>;
// Extract S sub-registers of Q registers.
// (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
def SSubReg_f32_reg : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
+ return CurDAG->getTargetConstant(1 + N->getZExtValue(), EVT::i32);
}]>;
// Translate lane numbers from Q registers to D subregs.
def SubReg_i8_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 7, EVT::i32);
}]>;
def SubReg_i16_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 3, EVT::i32);
}]>;
def SubReg_i32_lane : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
+ return CurDAG->getTargetConstant(N->getZExtValue() & 1, EVT::i32);
}]>;
//===----------------------------------------------------------------------===//
@@ -1772,7 +1772,7 @@
def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
- return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
+ return CurDAG->getTargetConstant(SVOp->getSplatIndex(), EVT::i32);
}]>;
def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Aug 10 17:56:29 2009
@@ -19,10 +19,10 @@
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
+ return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32);
}]>;
def imm_comp_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32);
}]>;
@@ -58,12 +58,12 @@
def thumb_immshifted_val : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
+ return CurDAG->getTargetConstant(V, EVT::i32);
}]>;
def thumb_immshifted_shamt : SDNodeXForm<imm, [{
unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
- return CurDAG->getTargetConstant(V, MVT::i32);
+ return CurDAG->getTargetConstant(V, EVT::i32);
}]>;
// Define Thumb specific addressing modes.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 10 17:56:29 2009
@@ -37,12 +37,12 @@
// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
+ return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32);
}]>;
// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
+ return CurDAG->getTargetConstant(-((int)N->getZExtValue()), EVT::i32);
}]>;
// t2_so_imm - Match a 32-bit immediate operand, which is an
@@ -97,11 +97,11 @@
/// Split a 32-bit immediate into two 16 bit parts.
def t2_lo16 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
- MVT::i32);
+ EVT::i32);
}]>;
def t2_hi16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, EVT::i32);
}]>;
def t2_lo16AllZero : PatLeaf<(i32 imm), [{
Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Aug 10 17:56:29 2009
@@ -67,7 +67,7 @@
}
const TargetRegisterClass*
-Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const {
+Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
if (isARMLowRegister(Reg))
return ARM::tGPRRegisterClass;
switch (Reg) {
Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h Mon Aug 10 17:56:29 2009
@@ -38,7 +38,7 @@
/// Code Generation virtual methods...
const TargetRegisterClass *
- getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
+ getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Mon Aug 10 17:56:29 2009
@@ -152,7 +152,7 @@
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(int64_t Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i64);
+ return CurDAG->getTargetConstant(Imm, EVT::i64);
}
// Select - Convert the specified operand from a target-independent to a
@@ -251,8 +251,8 @@
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i32),
+ return CurDAG->SelectNodeTo(N, Alpha::LDA, EVT::i64,
+ CurDAG->getTargetFrameIndex(FI, EVT::i32),
getI64Imm(0));
}
case ISD::GLOBAL_OFFSET_TABLE:
@@ -272,16 +272,16 @@
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
Chain.getValue(1));
SDNode *CNode =
- CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
+ CurDAG->getTargetNode(Alpha::JSRs, dl, EVT::Other, EVT::Flag,
Chain, Chain.getValue(1));
- Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
+ Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, EVT::i64,
SDValue(CNode, 1));
- return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
+ return CurDAG->SelectNodeTo(N, Alpha::BISr, EVT::i64, Chain, Chain);
}
case ISD::READCYCLECOUNTER: {
SDValue Chain = N->getOperand(0);
- return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
+ return CurDAG->getTargetNode(Alpha::RPCC, dl, EVT::i64, EVT::Other,
Chain);
}
@@ -290,7 +290,7 @@
if (uval == 0) {
SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
- Alpha::R31, MVT::i64);
+ Alpha::R31, EVT::i64);
ReplaceUses(Op, Result);
return NULL;
}
@@ -306,17 +306,17 @@
break; //(zext (LDAH (LDA)))
//Else use the constant pool
ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
- SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
- SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI,
+ SDValue CPI = CurDAG->getTargetConstantPool(C, EVT::i64);
+ SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, EVT::i64, CPI,
SDValue(getGlobalBaseReg(), 0));
- return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
+ return CurDAG->SelectNodeTo(N, Alpha::LDQr, EVT::i64, EVT::Other,
CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP:
case ISD::ConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
- bool isDouble = N->getValueType(0) == MVT::f64;
- MVT T = isDouble ? MVT::f64 : MVT::f32;
+ bool isDouble = N->getValueType(0) == EVT::f64;
+ EVT T = isDouble ? EVT::f64 : EVT::f32;
if (CN->getValueAPF().isPosZero()) {
return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
T, CurDAG->getRegister(Alpha::F31, T),
@@ -359,18 +359,18 @@
};
SDValue tmp1 = N->getOperand(rev?1:0);
SDValue tmp2 = N->getOperand(rev?0:1);
- SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2);
+ SDNode *cmp = CurDAG->getTargetNode(Opc, dl, EVT::f64, tmp1, tmp2);
if (inv)
cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl,
- MVT::f64, SDValue(cmp, 0),
- CurDAG->getRegister(Alpha::F31, MVT::f64));
+ EVT::f64, SDValue(cmp, 0),
+ CurDAG->getRegister(Alpha::F31, EVT::f64));
switch(CC) {
case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
{
- SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64,
+ SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, EVT::f64,
tmp1, tmp2);
- cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64,
+ cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, EVT::f64,
SDValue(cmp2, 0), SDValue(cmp, 0));
break;
}
@@ -378,9 +378,9 @@
}
SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl,
- MVT::i64, SDValue(cmp, 0));
- return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64,
- CurDAG->getRegister(Alpha::R31, MVT::i64),
+ EVT::i64, SDValue(cmp, 0));
+ return CurDAG->getTargetNode(Alpha::CMPULT, dl, EVT::i64,
+ CurDAG->getRegister(Alpha::R31, EVT::i64),
SDValue(LD,0));
}
break;
@@ -406,10 +406,10 @@
if (get_zapImm(mask)) {
SDValue Z =
- SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64,
+ SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, EVT::i64,
N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
- return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z,
+ return CurDAG->getTargetNode(Alpha::SRLr, dl, EVT::i64, Z,
getI64Imm(sval));
}
}
@@ -434,14 +434,14 @@
SDValue GOT = SDValue(getGlobalBaseReg(), 0);
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other,
- MVT::Flag, Addr.getOperand(0),
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, EVT::Other,
+ EVT::Flag, Addr.getOperand(0),
Chain, InFlag), 0);
} else {
Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other,
- MVT::Flag, Chain, InFlag), 0);
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, EVT::Other,
+ EVT::Flag, Chain, InFlag), 0);
}
InFlag = Chain.getValue(1);
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Mon Aug 10 17:56:29 2009
@@ -46,114 +46,114 @@
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
// Set up the TargetLowering object.
//I am having problems with shr n i8 1
- setShiftAmountType(MVT::i64);
+ setShiftAmountType(EVT::i64);
setBooleanContents(ZeroOrOneBooleanContent);
setUsesGlobalOffsetTable(true);
- addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
- addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
- addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
+ addRegisterClass(EVT::i64, Alpha::GPRCRegisterClass);
+ addRegisterClass(EVT::f64, Alpha::F8RCRegisterClass);
+ addRegisterClass(EVT::f32, Alpha::F4RCRegisterClass);
// We want to custom lower some of our intrinsics.
- setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom);
- setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, EVT::i32, Expand);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand);
- setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ setTruncStoreAction(EVT::f64, EVT::f32, Expand);
- // setOperationAction(ISD::BRIND, MVT::Other, Expand);
- setOperationAction(ISD::BR_JT, MVT::Other, Expand);
- setOperationAction(ISD::BR_CC, MVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
+ // setOperationAction(ISD::BRIND, EVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, EVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, EVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
- setOperationAction(ISD::FREM, MVT::f32, Expand);
- setOperationAction(ISD::FREM, MVT::f64, Expand);
+ setOperationAction(ISD::FREM, EVT::f32, Expand);
+ setOperationAction(ISD::FREM, EVT::f64, Expand);
- setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
- setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
- setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
- setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand);
+ setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
- setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
- setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
- setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
- }
- setOperationAction(ISD::BSWAP , MVT::i64, Expand);
- setOperationAction(ISD::ROTL , MVT::i64, Expand);
- setOperationAction(ISD::ROTR , MVT::i64, Expand);
-
- setOperationAction(ISD::SREM , MVT::i64, Custom);
- setOperationAction(ISD::UREM , MVT::i64, Custom);
- setOperationAction(ISD::SDIV , MVT::i64, Custom);
- setOperationAction(ISD::UDIV , MVT::i64, Custom);
-
- setOperationAction(ISD::ADDC , MVT::i64, Expand);
- setOperationAction(ISD::ADDE , MVT::i64, Expand);
- setOperationAction(ISD::SUBC , MVT::i64, Expand);
- setOperationAction(ISD::SUBE , MVT::i64, Expand);
-
- setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
-
- setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
- setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
- setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
+ setOperationAction(ISD::CTPOP , EVT::i64 , Expand);
+ setOperationAction(ISD::CTTZ , EVT::i64 , Expand);
+ setOperationAction(ISD::CTLZ , EVT::i64 , Expand);
+ }
+ setOperationAction(ISD::BSWAP , EVT::i64, Expand);
+ setOperationAction(ISD::ROTL , EVT::i64, Expand);
+ setOperationAction(ISD::ROTR , EVT::i64, Expand);
+
+ setOperationAction(ISD::SREM , EVT::i64, Custom);
+ setOperationAction(ISD::UREM , EVT::i64, Custom);
+ setOperationAction(ISD::SDIV , EVT::i64, Custom);
+ setOperationAction(ISD::UDIV , EVT::i64, Custom);
+
+ setOperationAction(ISD::ADDC , EVT::i64, Expand);
+ setOperationAction(ISD::ADDE , EVT::i64, Expand);
+ setOperationAction(ISD::SUBC , EVT::i64, Expand);
+ setOperationAction(ISD::SUBE , EVT::i64, Expand);
+
+ setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
+
+ setOperationAction(ISD::SRL_PARTS, EVT::i64, Custom);
+ setOperationAction(ISD::SRA_PARTS, EVT::i64, Expand);
+ setOperationAction(ISD::SHL_PARTS, EVT::i64, Expand);
// We don't support sin/cos/sqrt/pow
- setOperationAction(ISD::FSIN , MVT::f64, Expand);
- setOperationAction(ISD::FCOS , MVT::f64, Expand);
- setOperationAction(ISD::FSIN , MVT::f32, Expand);
- setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::FSIN , EVT::f64, Expand);
+ setOperationAction(ISD::FCOS , EVT::f64, Expand);
+ setOperationAction(ISD::FSIN , EVT::f32, Expand);
+ setOperationAction(ISD::FCOS , EVT::f32, Expand);
- setOperationAction(ISD::FSQRT, MVT::f64, Expand);
- setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, EVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, EVT::f32, Expand);
- setOperationAction(ISD::FPOW , MVT::f32, Expand);
- setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FPOW , EVT::f32, Expand);
+ setOperationAction(ISD::FPOW , EVT::f64, Expand);
- setOperationAction(ISD::SETCC, MVT::f32, Promote);
+ setOperationAction(ISD::SETCC, EVT::f32, Promote);
- setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
+ setOperationAction(ISD::BIT_CONVERT, EVT::f32, Promote);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
// Not implemented yet.
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+ setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand);
// We want to legalize GlobalAddress and ConstantPool and
// ExternalSymbols nodes into the appropriate instructions to
// materialize the address.
- setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
- setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
- setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
- setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
-
- setOperationAction(ISD::VASTART, MVT::Other, Custom);
- setOperationAction(ISD::VAEND, MVT::Other, Expand);
- setOperationAction(ISD::VACOPY, MVT::Other, Custom);
- setOperationAction(ISD::VAARG, MVT::Other, Custom);
- setOperationAction(ISD::VAARG, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, EVT::i64, Custom);
+ setOperationAction(ISD::ConstantPool, EVT::i64, Custom);
+ setOperationAction(ISD::ExternalSymbol, EVT::i64, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom);
+
+ setOperationAction(ISD::VASTART, EVT::Other, Custom);
+ setOperationAction(ISD::VAEND, EVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, EVT::Other, Custom);
+ setOperationAction(ISD::VAARG, EVT::Other, Custom);
+ setOperationAction(ISD::VAARG, EVT::i32, Custom);
- setOperationAction(ISD::JumpTable, MVT::i64, Custom);
- setOperationAction(ISD::JumpTable, MVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, EVT::i64, Custom);
+ setOperationAction(ISD::JumpTable, EVT::i32, Custom);
setStackPointerRegisterToSaveRestore(Alpha::R30);
@@ -168,8 +168,8 @@
computeRegisterProperties();
}
-MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(MVT VT) const {
- return MVT::i64;
+EVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
+ return EVT::i64;
}
const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -196,16 +196,16 @@
}
static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
- MVT PtrVT = Op.getValueType();
+ EVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDValue Zero = DAG.getConstant(0, PtrVT);
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
- DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, JTI,
+ DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, JTI, Hi);
return Lo;
}
@@ -285,7 +285,7 @@
assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
- StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
+ StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, EVT::i64);
SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
StackPtr,
@@ -299,7 +299,7 @@
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
@@ -313,7 +313,7 @@
}
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -406,27 +406,27 @@
for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
SDValue argt;
- MVT ObjectVT = Ins[ArgNo].VT;
+ EVT ObjectVT = Ins[ArgNo].VT;
SDValue ArgVal;
if (ArgNo < 6) {
switch (ObjectVT.getSimpleVT()) {
default:
assert(false && "Invalid value type!");
- case MVT::f64:
+ case EVT::f64:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F8RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
- case MVT::f32:
+ case EVT::f32:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F4RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
- case MVT::i64:
+ case EVT::i64:
args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
&Alpha::GPRCRegClass);
- ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], EVT::i64);
break;
}
} else { //more args
@@ -435,7 +435,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
+ SDValue FIN = DAG.getFrameIndex(FI, EVT::i64);
ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
}
InVals.push_back(ArgVal);
@@ -448,22 +448,22 @@
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
- SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
+ SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], EVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
- SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
+ SDValue SDFI = DAG.getFrameIndex(FI, EVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
- argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
+ argt = DAG.getCopyFromReg(Chain, dl, args_float[i], EVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
- SDFI = DAG.getFrameIndex(FI, MVT::i64);
+ SDFI = DAG.getFrameIndex(FI, EVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
}
//Set up a token factor with all the stack traffic
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LS[0], LS.size());
}
return Chain;
@@ -478,7 +478,7 @@
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
DebugLoc::getUnknownLoc(),
- MVT::i64),
+ EVT::i64),
SDValue());
switch (Outs.size()) {
default:
@@ -487,7 +487,7 @@
break;
//return SDValue(); // ret void is legal
case 1: {
- MVT ArgVT = Outs[0].Val.getValueType();
+ EVT ArgVT = Outs[0].Val.getValueType();
unsigned ArgReg;
if (ArgVT.isInteger())
ArgReg = Alpha::R0;
@@ -502,7 +502,7 @@
break;
}
case 2: {
- MVT ArgVT = Outs[0].Val.getValueType();
+ EVT ArgVT = Outs[0].Val.getValueType();
unsigned ArgReg1, ArgReg2;
if (ArgVT.isInteger()) {
ArgReg1 = Alpha::R0;
@@ -528,7 +528,7 @@
}
}
return DAG.getNode(AlphaISD::RET_FLAG, dl,
- MVT::Other, Copy, Copy.getValue(1));
+ EVT::Other, Copy, Copy.getValue(1));
}
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
@@ -538,26 +538,26 @@
const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
DebugLoc dl = N->getDebugLoc();
- SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0);
- SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
- DAG.getConstant(8, MVT::i64));
- SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
- Tmp, NULL, 0, MVT::i32);
- DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
+ SDValue Base = DAG.getLoad(EVT::i64, dl, Chain, VAListP, VAListS, 0);
+ SDValue Tmp = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP,
+ DAG.getConstant(8, EVT::i64));
+ SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Base.getValue(1),
+ Tmp, NULL, 0, EVT::i32);
+ DataPtr = DAG.getNode(ISD::ADD, dl, EVT::i64, Base, Offset);
if (N->getValueType(0).isFloatingPoint())
{
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
- SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
- DAG.getConstant(8*6, MVT::i64));
- SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
- DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
- DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
+ SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, EVT::i64, DataPtr,
+ DAG.getConstant(8*6, EVT::i64));
+ SDValue CC = DAG.getSetCC(dl, EVT::i64, Offset,
+ DAG.getConstant(8*6, EVT::i64), ISD::SETLT);
+ DataPtr = DAG.getNode(ISD::SELECT, dl, EVT::i64, CC, FPDataPtr, DataPtr);
}
- SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
- DAG.getConstant(8, MVT::i64));
+ SDValue NewOffset = DAG.getNode(ISD::ADD, dl, EVT::i64, Offset,
+ DAG.getConstant(8, EVT::i64));
Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
- MVT::i32);
+ EVT::i32);
}
/// LowerOperation - Provide custom lowering hooks for some operations.
@@ -573,7 +573,7 @@
switch (IntNo) {
default: break; // Don't custom lower most intrinsics.
case Intrinsic::alpha_umulh:
- return DAG.getNode(ISD::MULHU, dl, MVT::i64,
+ return DAG.getNode(ISD::MULHU, dl, EVT::i64,
Op.getOperand(1), Op.getOperand(2));
}
}
@@ -582,23 +582,23 @@
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
- SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
- DAG.getConstant(64, MVT::i64), ShAmt);
- SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm,
- DAG.getConstant(0, MVT::i64), ISD::SETLE);
+ SDValue bm = DAG.getNode(ISD::SUB, dl, EVT::i64,
+ DAG.getConstant(64, EVT::i64), ShAmt);
+ SDValue BMCC = DAG.getSetCC(dl, EVT::i64, bm,
+ DAG.getConstant(0, EVT::i64), ISD::SETLE);
// if 64 - shAmt <= 0
- SDValue Hi_Neg = DAG.getConstant(0, MVT::i64);
- SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
- DAG.getConstant(0, MVT::i64), bm);
- SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
+ SDValue Hi_Neg = DAG.getConstant(0, EVT::i64);
+ SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, EVT::i64,
+ DAG.getConstant(0, EVT::i64), bm);
+ SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt_Neg);
// else
- SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm);
- SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
- SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
- Lo_Pos = DAG.getNode(ISD::OR, dl, MVT::i64, Lo_Pos, carries);
+ SDValue carries = DAG.getNode(ISD::SHL, dl, EVT::i64, ShOpHi, bm);
+ SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt);
+ SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpLo, ShAmt);
+ Lo_Pos = DAG.getNode(ISD::OR, dl, EVT::i64, Lo_Pos, carries);
// Merge
- SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
- SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos);
+ SDValue Hi = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Hi_Neg, Hi_Pos);
+ SDValue Lo = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Lo_Neg, Lo_Pos);
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, 2, dl);
}
@@ -608,35 +608,35 @@
case ISD::SINT_TO_FP: {
- assert(Op.getOperand(0).getValueType() == MVT::i64 &&
+ assert(Op.getOperand(0).getValueType() == EVT::i64 &&
"Unhandled SINT_TO_FP type in custom expander!");
SDValue LD;
- bool isDouble = Op.getValueType() == MVT::f64;
- LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
+ bool isDouble = Op.getValueType() == EVT::f64;
+ LD = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op.getOperand(0));
SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
- isDouble?MVT::f64:MVT::f32, LD);
+ isDouble?EVT::f64:EVT::f32, LD);
return FP;
}
case ISD::FP_TO_SINT: {
- bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
+ bool isDouble = Op.getOperand(0).getValueType() == EVT::f64;
SDValue src = Op.getOperand(0);
if (!isDouble) //Promote
- src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
+ src = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, src);
- src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
+ src = DAG.getNode(AlphaISD::CVTTQ_, dl, EVT::f64, src);
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, src);
}
case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
- SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
+ SDValue CPI = DAG.getTargetConstantPool(C, EVT::i64, CP->getAlignment());
// FIXME there isn't really any debug info here
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
- DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, CPI,
+ DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, CPI, Hi);
return Lo;
}
case ISD::GlobalTLSAddress:
@@ -644,31 +644,31 @@
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i64, GSDN->getOffset());
// FIXME there isn't really any debug info here
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasLocalLinkage()) {
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
- DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, GA, Hi);
return Lo;
} else
- return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
- DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
}
case ISD::ExternalSymbol: {
- return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
+ return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64,
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
- ->getSymbol(), MVT::i64),
- DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ ->getSymbol(), EVT::i64),
+ DAG.getGLOBAL_OFFSET_TABLE(EVT::i64));
}
case ISD::UREM:
case ISD::SREM:
//Expand only on constant case
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
- MVT VT = Op.getNode()->getValueType(0);
+ EVT VT = Op.getNode()->getValueType(0);
SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
BuildUDIV(Op.getNode(), DAG, NULL) :
BuildSDIV(Op.getNode(), DAG, NULL);
@@ -692,8 +692,8 @@
}
SDValue Tmp1 = Op.getOperand(0),
Tmp2 = Op.getOperand(1),
- Addr = DAG.getExternalSymbol(opstr, MVT::i64);
- return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
+ Addr = DAG.getExternalSymbol(opstr, EVT::i64);
+ return DAG.getNode(AlphaISD::DivCall, dl, EVT::i64, Addr, Tmp1, Tmp2);
}
break;
@@ -702,9 +702,9 @@
LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
SDValue Result;
- if (Op.getValueType() == MVT::i32)
- Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
- NULL, 0, MVT::i32);
+ if (Op.getValueType() == EVT::i32)
+ Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Chain, DataPtr,
+ NULL, 0, EVT::i32);
else
Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
return Result;
@@ -718,13 +718,13 @@
SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
- SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
- DAG.getConstant(8, MVT::i64));
- Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
- NP, NULL,0, MVT::i32);
- SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
- DAG.getConstant(8, MVT::i64));
- return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
+ SDValue NP = DAG.getNode(ISD::ADD, dl, EVT::i64, SrcP,
+ DAG.getConstant(8, EVT::i64));
+ Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Result,
+ NP, NULL,0, EVT::i32);
+ SDValue NPD = DAG.getNode(ISD::ADD, dl, EVT::i64, DestP,
+ DAG.getConstant(8, EVT::i64));
+ return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, EVT::i32);
}
case ISD::VASTART: {
SDValue Chain = Op.getOperand(0);
@@ -732,16 +732,16 @@
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// vastart stores the address of the VarArgsBase and VarArgsOffset
- SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
+ SDValue FR = DAG.getFrameIndex(VarArgsBase, EVT::i64);
SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
- SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
- DAG.getConstant(8, MVT::i64));
- return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
- SA2, NULL, 0, MVT::i32);
+ SDValue SA2 = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP,
+ DAG.getConstant(8, EVT::i64));
+ return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, EVT::i64),
+ SA2, NULL, 0, EVT::i32);
}
case ISD::RETURNADDR:
return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
- MVT::i64);
+ EVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
}
@@ -753,7 +753,7 @@
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
DebugLoc dl = N->getDebugLoc();
- assert(N->getValueType(0) == MVT::i32 &&
+ assert(N->getValueType(0) == EVT::i32 &&
N->getOpcode() == ISD::VAARG &&
"Unknown node to custom promote!");
@@ -784,7 +784,7 @@
std::vector<unsigned> AlphaTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break; // Unknown constriant letter
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Mon Aug 10 17:56:29 2009
@@ -67,7 +67,7 @@
explicit AlphaTargetLowering(TargetMachine &TM);
/// getSetCCResultType - Get the SETCC result ValueType
- virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const;
+ virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
///
@@ -92,7 +92,7 @@
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
bool hasITOF() { return useITOF; }
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp Mon Aug 10 17:56:29 2009
@@ -94,9 +94,9 @@
// Selects to ADDpp FI, 0 which in turn will become ADDimm7 SP, imm or ADDpp
// SP, Px
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
- return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI,
- CurDAG->getTargetConstant(0, MVT::i32));
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i32);
+ return CurDAG->SelectNodeTo(N, BF::ADDpp, EVT::i32, TFI,
+ CurDAG->getTargetConstant(0, EVT::i32));
}
}
@@ -109,8 +109,8 @@
SDValue &Offset) {
FrameIndexSDNode *FIN = 0;
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
- Offset = CurDAG->getTargetConstant(0, MVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
@@ -119,8 +119,8 @@
(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
(CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
// Constant positive word offset from frame index
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32);
return true;
}
}
@@ -179,9 +179,9 @@
SDNode *Copy =
DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS,
NI->getDebugLoc(),
- MVT::i32,
+ EVT::i32,
UI.getUse().get(),
- DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
+ DAG.getTargetConstant(BF::DRegClassID, EVT::i32));
UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0));
}
}
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Mon Aug 10 17:56:29 2009
@@ -40,92 +40,92 @@
BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
- setShiftAmountType(MVT::i16);
+ setShiftAmountType(EVT::i16);
setBooleanContents(ZeroOrOneBooleanContent);
setStackPointerRegisterToSaveRestore(BF::SP);
setIntDivIsCheap(false);
// Set up the legal register classes.
- addRegisterClass(MVT::i32, BF::DRegisterClass);
- addRegisterClass(MVT::i16, BF::D16RegisterClass);
+ addRegisterClass(EVT::i32, BF::DRegisterClass);
+ addRegisterClass(EVT::i16, BF::D16RegisterClass);
computeRegisterProperties();
// Blackfin doesn't have i1 loads or stores
- setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
-
- setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
- setOperationAction(ISD::JumpTable, MVT::i32, Custom);
-
- setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
- setOperationAction(ISD::BR_JT, MVT::Other, Expand);
- setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+
+ setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, EVT::i32, Custom);
+
+ setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, EVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, EVT::Other, Expand);
// i16 registers don't do much
- setOperationAction(ISD::AND, MVT::i16, Promote);
- setOperationAction(ISD::OR, MVT::i16, Promote);
- setOperationAction(ISD::XOR, MVT::i16, Promote);
- setOperationAction(ISD::CTPOP, MVT::i16, Promote);
+ setOperationAction(ISD::AND, EVT::i16, Promote);
+ setOperationAction(ISD::OR, EVT::i16, Promote);
+ setOperationAction(ISD::XOR, EVT::i16, Promote);
+ setOperationAction(ISD::CTPOP, EVT::i16, Promote);
// The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
// immediately.
- setOperationAction(ISD::CTLZ, MVT::i16, Promote);
- setOperationAction(ISD::CTTZ, MVT::i16, Promote);
- setOperationAction(ISD::SETCC, MVT::i16, Promote);
+ setOperationAction(ISD::CTLZ, EVT::i16, Promote);
+ setOperationAction(ISD::CTTZ, EVT::i16, Promote);
+ setOperationAction(ISD::SETCC, EVT::i16, Promote);
// Blackfin has no division
- setOperationAction(ISD::SDIV, MVT::i16, Expand);
- setOperationAction(ISD::SDIV, MVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
- setOperationAction(ISD::SREM, MVT::i16, Expand);
- setOperationAction(ISD::SREM, MVT::i32, Expand);
- setOperationAction(ISD::UDIV, MVT::i16, Expand);
- setOperationAction(ISD::UDIV, MVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
- setOperationAction(ISD::UREM, MVT::i16, Expand);
- setOperationAction(ISD::UREM, MVT::i32, Expand);
-
- setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
- setOperationAction(ISD::MULHU, MVT::i32, Expand);
- setOperationAction(ISD::MULHS, MVT::i32, Expand);
+ setOperationAction(ISD::SDIV, EVT::i16, Expand);
+ setOperationAction(ISD::SDIV, EVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::SREM, EVT::i16, Expand);
+ setOperationAction(ISD::SREM, EVT::i32, Expand);
+ setOperationAction(ISD::UDIV, EVT::i16, Expand);
+ setOperationAction(ISD::UDIV, EVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::UREM, EVT::i16, Expand);
+ setOperationAction(ISD::UREM, EVT::i32, Expand);
+
+ setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::MULHU, EVT::i32, Expand);
+ setOperationAction(ISD::MULHS, EVT::i32, Expand);
// No carry-in operations.
- setOperationAction(ISD::ADDE, MVT::i32, Custom);
- setOperationAction(ISD::SUBE, MVT::i32, Custom);
+ setOperationAction(ISD::ADDE, EVT::i32, Custom);
+ setOperationAction(ISD::SUBE, EVT::i32, Custom);
// Blackfin has no intrinsics for these particular operations.
- setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
- setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+ setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
+ setOperationAction(ISD::BSWAP, EVT::i32, Expand);
- setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
// i32 has native CTPOP, but not CTLZ/CTTZ
- setOperationAction(ISD::CTLZ, MVT::i32, Expand);
- setOperationAction(ISD::CTTZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, EVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, EVT::i32, Expand);
// READCYCLECOUNTER needs special type legalization.
- setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
+ setOperationAction(ISD::READCYCLECOUNTER, EVT::i64, Custom);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
- setOperationAction(ISD::DECLARE, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::DECLARE, EVT::Other, Expand);
// Use the default implementation.
- setOperationAction(ISD::VACOPY, MVT::Other, Expand);
- setOperationAction(ISD::VAEND, MVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::VACOPY, EVT::Other, Expand);
+ setOperationAction(ISD::VAEND, EVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
}
const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -137,10 +137,10 @@
}
}
-MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(MVT VT) const {
+EVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
// SETCC always sets the CC register. Technically that is an i1 register, but
// that type is not legal, so we treat it as an i32 register.
- return MVT::i32;
+ return EVT::i32;
}
SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
@@ -148,16 +148,16 @@
DebugLoc DL = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- Op = DAG.getTargetGlobalAddress(GV, MVT::i32);
- return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
+ Op = DAG.getTargetGlobalAddress(GV, EVT::i32);
+ return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op);
}
SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
DebugLoc DL = Op.getDebugLoc();
int JTI = cast<JumpTableSDNode>(Op)->getIndex();
- Op = DAG.getTargetJumpTable(JTI, MVT::i32);
- return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
+ Op = DAG.getTargetJumpTable(JTI, EVT::i32);
+ return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op);
}
SDValue
@@ -181,7 +181,7 @@
CCValAssign &VA = ArgLocs[i];
if (VA.isRegLoc()) {
- MVT RegVT = VA.getLocVT();
+ EVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
BF::PRegisterClass : BF::DRegisterClass;
assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
@@ -209,7 +209,7 @@
assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8;
int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
- SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
+ SDValue FIN = DAG.getFrameIndex(FI, EVT::i32);
InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
}
}
@@ -268,9 +268,9 @@
}
if (Flag.getNode()) {
- return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
+ return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
} else {
- return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
+ return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain);
}
}
@@ -325,10 +325,10 @@
assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
int Offset = VA.getLocMemOffset();
assert(Offset%4 == 0 && "Unaligned LocMemOffset");
- assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
- SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
+ assert(VA.getLocVT()==EVT::i32 && "Illegal CCValAssign type");
+ SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, EVT::i32);
SDValue OffsetN = DAG.getIntPtrConstant(Offset);
- OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
+ OffsetN = DAG.getNode(ISD::ADD, dl, EVT::i32, SPN, OffsetN);
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
PseudoSourceValue::getStack(),
Offset));
@@ -338,7 +338,7 @@
// Transform all store nodes into one single node because
// all store nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -356,13 +356,13 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32);
- std::vector<MVT> NodeTys;
- NodeTys.push_back(MVT::Other); // Returns a chain
- NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
+ std::vector<EVT> NodeTys;
+ NodeTys.push_back(EVT::Other); // Returns a chain
+ NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use.
SDValue Ops[] = { Chain, Callee, InFlag };
Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
InFlag.getNode() ? 3 : 2);
@@ -423,25 +423,25 @@
unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
// zext incoming carry flag in AC0 to 32 bits
- SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
+ SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32,
/* flag= */ Op.getOperand(2));
- CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, MVT::i32,
+ CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, EVT::i32,
SDValue(CarryIn, 0));
// Add operands, produce sum and carry flag
- SDNode *Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
+ SDNode *Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
Op.getOperand(0), Op.getOperand(1));
// Store intermediate carry from Sum
- SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
+ SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32,
/* flag= */ SDValue(Sum, 1));
// Add incoming carry, again producing an output flag
- Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
+ Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag,
SDValue(Sum, 0), SDValue(CarryIn, 0));
// Update AC0 with the intermediate carry, producing a flag.
- SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, MVT::Flag,
+ SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, EVT::Flag,
SDValue(Carry1, 0));
// Compose (i32, flag) pair
@@ -480,10 +480,10 @@
// CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
// CYCLES2 last.
SDValue TheChain = N->getOperand(0);
- SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
- SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
+ SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, EVT::i32);
+ SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, EVT::i32);
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, lo, hi));
// Outgoing chain. If we were to use the chain from lo instead, it would be
// possible to entirely eliminate the CYCLES2 read in (i32 (trunc
// readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
@@ -549,7 +549,7 @@
/// getRegForInlineAsmConstraint - Return register no and class for a C_Register
/// constraint.
std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
+getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
using namespace BF;
@@ -559,7 +559,7 @@
switch (Constraint[0]) {
// Standard constraints
case 'r':
- return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
+ return Pair(0U, VT == EVT::i16 ? D16RegisterClass : DPRegisterClass);
// Blackfin-specific constraints
case 'a': return Pair(0U, PRegisterClass);
@@ -585,7 +585,7 @@
}
std::vector<unsigned> BlackfinTargetLowering::
-getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
+getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
using namespace BF;
if (Constraint.size() != 1)
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h Mon Aug 10 17:56:29 2009
@@ -33,7 +33,7 @@
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
BlackfinTargetLowering(TargetMachine &TM);
- virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const;
+ virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual void ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,
@@ -43,10 +43,10 @@
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>
- getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
const char *getTargetNodeName(unsigned Opcode) const;
unsigned getFunctionAlignment(const Function *F) const;
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.td Mon Aug 10 17:56:29 2009
@@ -42,21 +42,21 @@
def trailingZeros_xform : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
- MVT::i32);
+ EVT::i32);
}]>;
def trailingOnes_xform : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(),
- MVT::i32);
+ EVT::i32);
}]>;
def LO16 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), MVT::i16);
+ return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), EVT::i16);
}]>;
def HI16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, MVT::i16);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, EVT::i16);
}]>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon Aug 10 17:56:29 2009
@@ -87,7 +87,7 @@
}
const TargetRegisterClass*
-BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
+BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
assert(isPhysicalRegister(reg) && "reg must be a physical register");
// Pick the smallest register class of the right type that contains
@@ -96,7 +96,7 @@
for (regclass_iterator I = regclass_begin(), E = regclass_end();
I != E; ++I) {
const TargetRegisterClass* RC = *I;
- if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
+ if ((VT == EVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
BestRC = RC;
}
Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Mon Aug 10 17:56:29 2009
@@ -62,7 +62,7 @@
}
const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned reg,
- MVT VT) const;
+ EVT VT) const;
bool hasFP(const MachineFunction &MF) const;
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Mon Aug 10 17:56:29 2009
@@ -103,11 +103,11 @@
bool
isIntS16Immediate(ConstantSDNode *CN, short &Imm)
{
- MVT vt = CN->getValueType(0);
+ EVT vt = CN->getValueType(0);
Imm = (short) CN->getZExtValue();
- if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
+ if (vt.getSimpleVT() >= EVT::i1 && vt.getSimpleVT() <= EVT::i16) {
return true;
- } else if (vt == MVT::i32) {
+ } else if (vt == EVT::i32) {
int32_t i_val = (int32_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
@@ -132,8 +132,8 @@
static bool
isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
{
- MVT vt = FPN->getValueType(0);
- if (vt == MVT::f32) {
+ EVT vt = FPN->getValueType(0);
+ if (vt == EVT::f32) {
int val = FloatToBits(FPN->getValueAPF().convertToFloat());
int sval = (int) ((val << 16) >> 16);
Imm = (short) val;
@@ -154,34 +154,34 @@
}
//===------------------------------------------------------------------===//
- //! MVT to "useful stuff" mapping structure:
+ //! EVT to "useful stuff" mapping structure:
struct valtype_map_s {
- MVT VT;
+ EVT VT;
unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
bool ldresult_imm; /// LDRESULT instruction requires immediate?
unsigned lrinst; /// LR instruction
};
const valtype_map_s valtype_map[] = {
- { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
- { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
- { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
- { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
- { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
- { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
+ { EVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
+ { EVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
+ { EVT::i32, SPU::ORIr32, true, SPU::LRr32 },
+ { EVT::i64, SPU::ORr64, false, SPU::LRr64 },
+ { EVT::f32, SPU::ORf32, false, SPU::LRf32 },
+ { EVT::f64, SPU::ORf64, false, SPU::LRf64 },
// vector types... (sigh!)
- { MVT::v16i8, 0, false, SPU::LRv16i8 },
- { MVT::v8i16, 0, false, SPU::LRv8i16 },
- { MVT::v4i32, 0, false, SPU::LRv4i32 },
- { MVT::v2i64, 0, false, SPU::LRv2i64 },
- { MVT::v4f32, 0, false, SPU::LRv4f32 },
- { MVT::v2f64, 0, false, SPU::LRv2f64 }
+ { EVT::v16i8, 0, false, SPU::LRv16i8 },
+ { EVT::v8i16, 0, false, SPU::LRv8i16 },
+ { EVT::v4i32, 0, false, SPU::LRv4i32 },
+ { EVT::v2i64, 0, false, SPU::LRv2i64 },
+ { EVT::v4f32, 0, false, SPU::LRv4f32 },
+ { EVT::v2f64, 0, false, SPU::LRv2f64 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
- const valtype_map_s *getValueTypeMapEntry(MVT VT)
+ const valtype_map_s *getValueTypeMapEntry(EVT VT)
{
const valtype_map_s *retval = 0;
for (size_t i = 0; i < n_valtype_map; ++i) {
@@ -197,7 +197,7 @@
std::string msg;
raw_string_ostream Msg(msg);
Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
- << VT.getMVTString();
+ << VT.getEVTString();
llvm_report_error(Msg.str());
}
#endif
@@ -211,12 +211,12 @@
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
@@ -226,12 +226,12 @@
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
@@ -263,13 +263,13 @@
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint32_t Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i32);
+ return CurDAG->getTargetConstant(Imm, EVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i64);
+ return CurDAG->getTargetConstant(Imm, EVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
@@ -278,24 +278,24 @@
}
SDNode *emitBuildVector(SDValue build_vec) {
- MVT vecVT = build_vec.getValueType();
- MVT eltVT = vecVT.getVectorElementType();
+ EVT vecVT = build_vec.getValueType();
+ EVT eltVT = vecVT.getVectorElementType();
SDNode *bvNode = build_vec.getNode();
DebugLoc dl = bvNode->getDebugLoc();
// Check to see if this vector can be represented as a CellSPU immediate
// constant by invoking all of the instruction selection predicates:
- if (((vecVT == MVT::v8i16) &&
- (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
- ((vecVT == MVT::v4i32) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
+ if (((vecVT == EVT::v8i16) &&
+ (SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i16).getNode() != 0)) ||
+ ((vecVT == EVT::v4i32) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
(SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
- ((vecVT == MVT::v2i64) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
+ ((vecVT == EVT::v2i64) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i64).getNode() != 0))))
return Select(build_vec);
// No, need to emit a constant pool spill:
@@ -323,19 +323,19 @@
SDNode *Select(SDValue Op);
//! Emit the instruction sequence for i64 shl
- SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
+ SDNode *SelectSHLi64(SDValue &Op, EVT OpVT);
//! Emit the instruction sequence for i64 srl
- SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
+ SDNode *SelectSRLi64(SDValue &Op, EVT OpVT);
//! Emit the instruction sequence for i64 sra
- SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
+ SDNode *SelectSRAi64(SDValue &Op, EVT OpVT);
//! Emit the necessary sequence for loading i64 constants:
- SDNode *SelectI64Constant(SDValue &Op, MVT OpVT, DebugLoc dl);
+ SDNode *SelectI64Constant(SDValue &Op, EVT OpVT, DebugLoc dl);
//! Alternate instruction emit sequence for loading i64 constants
- SDNode *SelectI64Constant(uint64_t i64const, MVT OpVT, DebugLoc dl);
+ SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
//! Returns true if the address N is an A-form (local store) address
bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
@@ -434,7 +434,7 @@
SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
// These match the addr256k operand type:
- MVT OffsVT = MVT::i16;
+ EVT OffsVT = EVT::i16;
SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
@@ -514,7 +514,7 @@
SDValue &Index, int minOffset,
int maxOffset) {
unsigned Opc = N.getOpcode();
- MVT PtrTy = SPUtli.getPointerTy();
+ EVT PtrTy = SPUtli.getPointerTy();
if (Opc == ISD::FrameIndex) {
// Stack frame index must be less than 512 (divided by 16):
@@ -692,7 +692,7 @@
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
- MVT OpVT = Op.getValueType();
+ EVT OpVT = Op.getValueType();
SDValue Ops[8];
DebugLoc dl = N->getDebugLoc();
@@ -717,45 +717,45 @@
TFI, Imm0), 0);
n_ops = 2;
}
- } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
+ } else if (Opc == ISD::Constant && OpVT == EVT::i64) {
// Catch the i64 constants that end up here. Note: The backend doesn't
// attempt to legalize the constant (it's useless because DAGCombiner
// will insert 64-bit constants and we can't stop it).
return SelectI64Constant(Op, OpVT, Op.getDebugLoc());
} else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
- && OpVT == MVT::i64) {
+ && OpVT == EVT::i64) {
SDValue Op0 = Op.getOperand(0);
- MVT Op0VT = Op0.getValueType();
- MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
- MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT Op0VT = Op0.getValueType();
+ EVT Op0VecVT = EVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
+ EVT OpVecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue shufMask;
switch (Op0VT.getSimpleVT()) {
default:
- llvm_report_error("CellSPU Select: Unhandled zero/any extend MVT");
+ llvm_report_error("CellSPU Select: Unhandled zero/any extend EVT");
/*NOTREACHED*/
- case MVT::i32:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x00010203, MVT::i32),
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x08090a0b, MVT::i32));
+ case EVT::i32:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x00010203, EVT::i32),
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x08090a0b, EVT::i32));
break;
- case MVT::i16:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x80800203, MVT::i32),
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x80800a0b, MVT::i32));
+ case EVT::i16:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x80800203, EVT::i32),
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x80800a0b, EVT::i32));
break;
- case MVT::i8:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x80808003, MVT::i32),
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x8080800b, MVT::i32));
+ case EVT::i8:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x80808003, EVT::i32),
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x8080800b, EVT::i32));
break;
}
@@ -775,21 +775,21 @@
SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
zextShuffle));
- } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ } else if (Opc == ISD::ADD && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ } else if (Opc == ISD::SUB && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ } else if (Opc == ISD::MUL && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
@@ -799,8 +799,8 @@
} else if (Opc == ISD::TRUNCATE) {
SDValue Op0 = Op.getOperand(0);
if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
- && OpVT == MVT::i32
- && Op0.getValueType() == MVT::i64) {
+ && OpVT == EVT::i32
+ && Op0.getValueType() == EVT::i64) {
// Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
//
// Take advantage of the fact that the upper 32 bits are in the
@@ -817,7 +817,7 @@
shift_amt -= 32;
if (shift_amt > 0) {
// Take care of the additional shift, if present:
- SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
+ SDValue shift = CurDAG->getTargetConstant(shift_amt, EVT::i32);
unsigned Opc = SPU::ROTMAIr32_i32;
if (Op0.getOpcode() == ISD::SRL)
@@ -832,19 +832,19 @@
}
}
} else if (Opc == ISD::SHL) {
- if (OpVT == MVT::i64) {
+ if (OpVT == EVT::i64) {
return SelectSHLi64(Op, OpVT);
}
} else if (Opc == ISD::SRL) {
- if (OpVT == MVT::i64) {
+ if (OpVT == EVT::i64) {
return SelectSRLi64(Op, OpVT);
}
} else if (Opc == ISD::SRA) {
- if (OpVT == MVT::i64) {
+ if (OpVT == EVT::i64) {
return SelectSRAi64(Op, OpVT);
}
} else if (Opc == ISD::FNEG
- && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
+ && (OpVT == EVT::f64 || OpVT == EVT::v2f64)) {
DebugLoc dl = Op.getDebugLoc();
// Check if the pattern is a special form of DFNMS:
// (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
@@ -853,7 +853,7 @@
SDValue Op00 = Op0.getOperand(0);
if (Op00.getOpcode() == ISD::FMUL) {
unsigned Opc = SPU::DFNMSf64;
- if (OpVT == MVT::v2f64)
+ if (OpVT == EVT::v2f64)
Opc = SPU::DFNMSv2f64;
return CurDAG->getTargetNode(Opc, dl, OpVT,
@@ -863,29 +863,29 @@
}
}
- SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
+ SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, EVT::i64);
SDNode *signMask = 0;
unsigned Opc = SPU::XORfneg64;
- if (OpVT == MVT::f64) {
- signMask = SelectI64Constant(negConst, MVT::i64, dl);
- } else if (OpVT == MVT::v2f64) {
+ if (OpVT == EVT::f64) {
+ signMask = SelectI64Constant(negConst, EVT::i64, dl);
+ } else if (OpVT == EVT::v2f64) {
Opc = SPU::XORfnegvec;
signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
- MVT::v2i64,
+ EVT::v2i64,
negConst, negConst));
}
return CurDAG->getTargetNode(Opc, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
} else if (Opc == ISD::FABS) {
- if (OpVT == MVT::f64) {
- SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
+ if (OpVT == EVT::f64) {
+ SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, EVT::i64, dl);
return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
- } else if (OpVT == MVT::v2f64) {
- SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
- SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
+ } else if (OpVT == EVT::v2f64) {
+ SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, EVT::i64);
+ SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64,
absConst, absConst);
SDNode *signMask = emitBuildVector(absVec);
return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT,
@@ -893,7 +893,7 @@
}
} else if (Opc == SPUISD::LDRESULT) {
// Custom select instructions for LDRESULT
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue Arg = N->getOperand(0);
SDValue Chain = N->getOperand(1);
SDNode *Result;
@@ -903,7 +903,7 @@
std::string msg;
raw_string_ostream Msg(msg);
Msg << "LDRESULT for unsupported type: "
- << VT.getMVTString();
+ << VT.getEVTString();
llvm_report_error(Msg.str());
}
@@ -911,9 +911,9 @@
if (vtm->ldresult_imm) {
SDValue Zero = CurDAG->getTargetConstant(0, VT);
- Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Zero, Chain);
} else {
- Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Arg, Chain);
}
return Result;
@@ -924,7 +924,7 @@
// SPUInstrInfo catches the following patterns:
// (SPUindirect (SPUhi ...), (SPUlo ...))
// (SPUindirect $sp, imm)
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
RegisterSDNode *RN;
@@ -967,17 +967,17 @@
* @return The SDNode with the entire instruction sequence
*/
SDNode *
-SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
+SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
- MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
- MVT ShiftAmtVT = ShiftAmt.getValueType();
+ EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
SDValue SelMaskVal;
DebugLoc dl = Op.getDebugLoc();
VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
- SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
+ SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, EVT::i16);
SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
CurDAG->getTargetConstant(0, OpVT));
@@ -1032,11 +1032,11 @@
* @return The SDNode with the entire instruction sequence
*/
SDNode *
-SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
+SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
- MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
- MVT ShiftAmtVT = ShiftAmt.getValueType();
+ EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *Shift = 0;
DebugLoc dl = Op.getDebugLoc();
@@ -1098,11 +1098,11 @@
* @return The SDNode with the entire instruction sequence
*/
SDNode *
-SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
+SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) {
// Promote Op0 to vector
- MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
- MVT ShiftAmtVT = ShiftAmt.getValueType();
+ EVT ShiftAmtVT = ShiftAmt.getValueType();
DebugLoc dl = Op.getDebugLoc();
SDNode *VecOp0 =
@@ -1110,16 +1110,16 @@
SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
SDNode *SignRot =
- CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
+ CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, EVT::v2i64,
SDValue(VecOp0, 0), SignRotAmt);
SDNode *UpperHalfSign =
- CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
+ CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, EVT::i32, SDValue(SignRot, 0));
SDNode *UpperHalfSignMask =
CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
SDNode *UpperLowerMask =
CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
- CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
+ CurDAG->getTargetConstant(0xff00ULL, EVT::i16));
SDNode *UpperLowerSelect =
CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
SDValue(UpperHalfSignMask, 0),
@@ -1166,15 +1166,15 @@
/*!
Do the necessary magic necessary to load a i64 constant
*/
-SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT,
+SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, EVT OpVT,
DebugLoc dl) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
}
-SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, MVT OpVT,
+SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
DebugLoc dl) {
- MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
+ EVT OpVecVT = EVT::getVectorVT(OpVT, 2);
SDValue i64vec =
SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Aug 10 17:56:29 2009
@@ -40,26 +40,26 @@
namespace {
std::map<unsigned, const char *> node_names;
- //! MVT mapping to useful data for Cell SPU
+ //! EVT mapping to useful data for Cell SPU
struct valtype_map_s {
- const MVT valtype;
+ const EVT valtype;
const int prefslot_byte;
};
const valtype_map_s valtype_map[] = {
- { MVT::i1, 3 },
- { MVT::i8, 3 },
- { MVT::i16, 2 },
- { MVT::i32, 0 },
- { MVT::f32, 0 },
- { MVT::i64, 0 },
- { MVT::f64, 0 },
- { MVT::i128, 0 }
+ { EVT::i1, 3 },
+ { EVT::i8, 3 },
+ { EVT::i16, 2 },
+ { EVT::i32, 0 },
+ { EVT::f32, 0 },
+ { EVT::i64, 0 },
+ { EVT::f64, 0 },
+ { EVT::i128, 0 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
- const valtype_map_s *getValueTypeMapEntry(MVT VT) {
+ const valtype_map_s *getValueTypeMapEntry(EVT VT) {
const valtype_map_s *retval = 0;
for (size_t i = 0; i < n_valtype_map; ++i) {
@@ -74,7 +74,7 @@
std::string msg;
raw_string_ostream Msg(msg);
Msg << "getValueTypeMapEntry returns NULL for "
- << VT.getMVTString();
+ << VT.getEVTString();
llvm_report_error(Msg.str());
}
#endif
@@ -100,8 +100,8 @@
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
- MVT ArgVT = Op.getOperand(i).getValueType();
- const Type *ArgTy = ArgVT.getTypeForMVT();
+ EVT ArgVT = Op.getOperand(i).getValueType();
+ const Type *ArgTy = ArgVT.getTypeForEVT();
Entry.Node = Op.getOperand(i);
Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
@@ -112,7 +112,7 @@
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
- const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT();
+ const Type *RetTy = Op.getNode()->getValueType(0).getTypeForEVT();
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
0, CallingConv::C, false,
@@ -138,37 +138,37 @@
setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
// Set up the SPU's register classes:
- addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
- addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
- addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
- addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
- addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
- addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
- addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
+ addRegisterClass(EVT::i8, SPU::R8CRegisterClass);
+ addRegisterClass(EVT::i16, SPU::R16CRegisterClass);
+ addRegisterClass(EVT::i32, SPU::R32CRegisterClass);
+ addRegisterClass(EVT::i64, SPU::R64CRegisterClass);
+ addRegisterClass(EVT::f32, SPU::R32FPRegisterClass);
+ addRegisterClass(EVT::f64, SPU::R64FPRegisterClass);
+ addRegisterClass(EVT::i128, SPU::GPRCRegisterClass);
// SPU has no sign or zero extended loads for i1, i8, i16:
- setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
-
- setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
- setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
-
- setTruncStoreAction(MVT::i128, MVT::i64, Expand);
- setTruncStoreAction(MVT::i128, MVT::i32, Expand);
- setTruncStoreAction(MVT::i128, MVT::i16, Expand);
- setTruncStoreAction(MVT::i128, MVT::i8, Expand);
+ setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
+
+ setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand);
+
+ setTruncStoreAction(EVT::i128, EVT::i64, Expand);
+ setTruncStoreAction(EVT::i128, EVT::i32, Expand);
+ setTruncStoreAction(EVT::i128, EVT::i16, Expand);
+ setTruncStoreAction(EVT::i128, EVT::i8, Expand);
- setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ setTruncStoreAction(EVT::f64, EVT::f32, Expand);
// SPU constant load actions are custom lowered:
- setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
- setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
+ setOperationAction(ISD::ConstantFP, EVT::f32, Legal);
+ setOperationAction(ISD::ConstantFP, EVT::f64, Custom);
// SPU's loads and stores have to be custom lowered:
- for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
+ for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::i128;
++sctype) {
- MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
+ EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
@@ -176,222 +176,222 @@
setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
- for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
- MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
+ for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::i8; --stype) {
+ EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype;
setTruncStoreAction(VT, StoreVT, Expand);
}
}
- for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
+ for (unsigned sctype = (unsigned) EVT::f32; sctype < (unsigned) EVT::f64;
++sctype) {
- MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
+ EVT::SimpleValueType VT = (EVT::SimpleValueType) sctype;
setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom);
- for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) {
- MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
+ for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::f32; --stype) {
+ EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype;
setTruncStoreAction(VT, StoreVT, Expand);
}
}
// Expand the jumptable branches
- setOperationAction(ISD::BR_JT, MVT::Other, Expand);
- setOperationAction(ISD::BR_CC, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, EVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, EVT::Other, Expand);
// Custom lower SELECT_CC for most cases, but expand by default
- setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
+ setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, EVT::i16, Custom);
+ setOperationAction(ISD::SELECT_CC, EVT::i32, Custom);
+ setOperationAction(ISD::SELECT_CC, EVT::i64, Custom);
// SPU has no intrinsics for these particular operations:
- setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
// SPU has no division/remainder instructions
- setOperationAction(ISD::SREM, MVT::i8, Expand);
- setOperationAction(ISD::UREM, MVT::i8, Expand);
- setOperationAction(ISD::SDIV, MVT::i8, Expand);
- setOperationAction(ISD::UDIV, MVT::i8, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
- setOperationAction(ISD::SREM, MVT::i16, Expand);
- setOperationAction(ISD::UREM, MVT::i16, Expand);
- setOperationAction(ISD::SDIV, MVT::i16, Expand);
- setOperationAction(ISD::UDIV, MVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
- setOperationAction(ISD::SREM, MVT::i32, Expand);
- setOperationAction(ISD::UREM, MVT::i32, Expand);
- setOperationAction(ISD::SDIV, MVT::i32, Expand);
- setOperationAction(ISD::UDIV, MVT::i32, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
- setOperationAction(ISD::SREM, MVT::i64, Expand);
- setOperationAction(ISD::UREM, MVT::i64, Expand);
- setOperationAction(ISD::SDIV, MVT::i64, Expand);
- setOperationAction(ISD::UDIV, MVT::i64, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
- setOperationAction(ISD::SREM, MVT::i128, Expand);
- setOperationAction(ISD::UREM, MVT::i128, Expand);
- setOperationAction(ISD::SDIV, MVT::i128, Expand);
- setOperationAction(ISD::UDIV, MVT::i128, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
+ setOperationAction(ISD::SREM, EVT::i8, Expand);
+ setOperationAction(ISD::UREM, EVT::i8, Expand);
+ setOperationAction(ISD::SDIV, EVT::i8, Expand);
+ setOperationAction(ISD::UDIV, EVT::i8, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i8, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i8, Expand);
+ setOperationAction(ISD::SREM, EVT::i16, Expand);
+ setOperationAction(ISD::UREM, EVT::i16, Expand);
+ setOperationAction(ISD::SDIV, EVT::i16, Expand);
+ setOperationAction(ISD::UDIV, EVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
+ setOperationAction(ISD::SREM, EVT::i32, Expand);
+ setOperationAction(ISD::UREM, EVT::i32, Expand);
+ setOperationAction(ISD::SDIV, EVT::i32, Expand);
+ setOperationAction(ISD::UDIV, EVT::i32, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i32, Expand);
+ setOperationAction(ISD::SREM, EVT::i64, Expand);
+ setOperationAction(ISD::UREM, EVT::i64, Expand);
+ setOperationAction(ISD::SDIV, EVT::i64, Expand);
+ setOperationAction(ISD::UDIV, EVT::i64, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i64, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i64, Expand);
+ setOperationAction(ISD::SREM, EVT::i128, Expand);
+ setOperationAction(ISD::UREM, EVT::i128, Expand);
+ setOperationAction(ISD::SDIV, EVT::i128, Expand);
+ setOperationAction(ISD::UDIV, EVT::i128, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i128, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i128, Expand);
// We don't support sin/cos/sqrt/fmod
- setOperationAction(ISD::FSIN , MVT::f64, Expand);
- setOperationAction(ISD::FCOS , MVT::f64, Expand);
- setOperationAction(ISD::FREM , MVT::f64, Expand);
- setOperationAction(ISD::FSIN , MVT::f32, Expand);
- setOperationAction(ISD::FCOS , MVT::f32, Expand);
- setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::FSIN , EVT::f64, Expand);
+ setOperationAction(ISD::FCOS , EVT::f64, Expand);
+ setOperationAction(ISD::FREM , EVT::f64, Expand);
+ setOperationAction(ISD::FSIN , EVT::f32, Expand);
+ setOperationAction(ISD::FCOS , EVT::f32, Expand);
+ setOperationAction(ISD::FREM , EVT::f32, Expand);
// Expand fsqrt to the appropriate libcall (NOTE: should use h/w fsqrt
// for f32!)
- setOperationAction(ISD::FSQRT, MVT::f64, Expand);
- setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+ setOperationAction(ISD::FSQRT, EVT::f64, Expand);
+ setOperationAction(ISD::FSQRT, EVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
// SPU can do rotate right and left, so legalize it... but customize for i8
// because instructions don't exist.
// FIXME: Change from "expand" to appropriate type once ROTR is supported in
// .td files.
- setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
- setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
- setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
-
- setOperationAction(ISD::ROTL, MVT::i32, Legal);
- setOperationAction(ISD::ROTL, MVT::i16, Legal);
- setOperationAction(ISD::ROTL, MVT::i8, Custom);
+ setOperationAction(ISD::ROTR, EVT::i32, Expand /*Legal*/);
+ setOperationAction(ISD::ROTR, EVT::i16, Expand /*Legal*/);
+ setOperationAction(ISD::ROTR, EVT::i8, Expand /*Custom*/);
+
+ setOperationAction(ISD::ROTL, EVT::i32, Legal);
+ setOperationAction(ISD::ROTL, EVT::i16, Legal);
+ setOperationAction(ISD::ROTL, EVT::i8, Custom);
// SPU has no native version of shift left/right for i8
- setOperationAction(ISD::SHL, MVT::i8, Custom);
- setOperationAction(ISD::SRL, MVT::i8, Custom);
- setOperationAction(ISD::SRA, MVT::i8, Custom);
+ setOperationAction(ISD::SHL, EVT::i8, Custom);
+ setOperationAction(ISD::SRL, EVT::i8, Custom);
+ setOperationAction(ISD::SRA, EVT::i8, Custom);
// Make these operations legal and handle them during instruction selection:
- setOperationAction(ISD::SHL, MVT::i64, Legal);
- setOperationAction(ISD::SRL, MVT::i64, Legal);
- setOperationAction(ISD::SRA, MVT::i64, Legal);
+ setOperationAction(ISD::SHL, EVT::i64, Legal);
+ setOperationAction(ISD::SRL, EVT::i64, Legal);
+ setOperationAction(ISD::SRA, EVT::i64, Legal);
// Custom lower i8, i32 and i64 multiplications
- setOperationAction(ISD::MUL, MVT::i8, Custom);
- setOperationAction(ISD::MUL, MVT::i32, Legal);
- setOperationAction(ISD::MUL, MVT::i64, Legal);
+ setOperationAction(ISD::MUL, EVT::i8, Custom);
+ setOperationAction(ISD::MUL, EVT::i32, Legal);
+ setOperationAction(ISD::MUL, EVT::i64, Legal);
// Expand double-width multiplication
// FIXME: It would probably be reasonable to support some of these operations
- setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
- setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
- setOperationAction(ISD::MULHU, MVT::i8, Expand);
- setOperationAction(ISD::MULHS, MVT::i8, Expand);
- setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
- setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
- setOperationAction(ISD::MULHU, MVT::i16, Expand);
- setOperationAction(ISD::MULHS, MVT::i16, Expand);
- setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
- setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
- setOperationAction(ISD::MULHU, MVT::i32, Expand);
- setOperationAction(ISD::MULHS, MVT::i32, Expand);
- setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
- setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
- setOperationAction(ISD::MULHU, MVT::i64, Expand);
- setOperationAction(ISD::MULHS, MVT::i64, Expand);
+ setOperationAction(ISD::UMUL_LOHI, EVT::i8, Expand);
+ setOperationAction(ISD::SMUL_LOHI, EVT::i8, Expand);
+ setOperationAction(ISD::MULHU, EVT::i8, Expand);
+ setOperationAction(ISD::MULHS, EVT::i8, Expand);
+ setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand);
+ setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand);
+ setOperationAction(ISD::MULHU, EVT::i16, Expand);
+ setOperationAction(ISD::MULHS, EVT::i16, Expand);
+ setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand);
+ setOperationAction(ISD::MULHU, EVT::i32, Expand);
+ setOperationAction(ISD::MULHS, EVT::i32, Expand);
+ setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand);
+ setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand);
+ setOperationAction(ISD::MULHU, EVT::i64, Expand);
+ setOperationAction(ISD::MULHS, EVT::i64, Expand);
// Need to custom handle (some) common i8, i64 math ops
- setOperationAction(ISD::ADD, MVT::i8, Custom);
- setOperationAction(ISD::ADD, MVT::i64, Legal);
- setOperationAction(ISD::SUB, MVT::i8, Custom);
- setOperationAction(ISD::SUB, MVT::i64, Legal);
+ setOperationAction(ISD::ADD, EVT::i8, Custom);
+ setOperationAction(ISD::ADD, EVT::i64, Legal);
+ setOperationAction(ISD::SUB, EVT::i8, Custom);
+ setOperationAction(ISD::SUB, EVT::i64, Legal);
// SPU does not have BSWAP. It does have i32 support CTLZ.
// CTPOP has to be custom lowered.
- setOperationAction(ISD::BSWAP, MVT::i32, Expand);
- setOperationAction(ISD::BSWAP, MVT::i64, Expand);
+ setOperationAction(ISD::BSWAP, EVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, EVT::i64, Expand);
- setOperationAction(ISD::CTPOP, MVT::i8, Custom);
- setOperationAction(ISD::CTPOP, MVT::i16, Custom);
- setOperationAction(ISD::CTPOP, MVT::i32, Custom);
- setOperationAction(ISD::CTPOP, MVT::i64, Custom);
- setOperationAction(ISD::CTPOP, MVT::i128, Expand);
-
- setOperationAction(ISD::CTTZ , MVT::i8, Expand);
- setOperationAction(ISD::CTTZ , MVT::i16, Expand);
- setOperationAction(ISD::CTTZ , MVT::i32, Expand);
- setOperationAction(ISD::CTTZ , MVT::i64, Expand);
- setOperationAction(ISD::CTTZ , MVT::i128, Expand);
-
- setOperationAction(ISD::CTLZ , MVT::i8, Promote);
- setOperationAction(ISD::CTLZ , MVT::i16, Promote);
- setOperationAction(ISD::CTLZ , MVT::i32, Legal);
- setOperationAction(ISD::CTLZ , MVT::i64, Expand);
- setOperationAction(ISD::CTLZ , MVT::i128, Expand);
+ setOperationAction(ISD::CTPOP, EVT::i8, Custom);
+ setOperationAction(ISD::CTPOP, EVT::i16, Custom);
+ setOperationAction(ISD::CTPOP, EVT::i32, Custom);
+ setOperationAction(ISD::CTPOP, EVT::i64, Custom);
+ setOperationAction(ISD::CTPOP, EVT::i128, Expand);
+
+ setOperationAction(ISD::CTTZ , EVT::i8, Expand);
+ setOperationAction(ISD::CTTZ , EVT::i16, Expand);
+ setOperationAction(ISD::CTTZ , EVT::i32, Expand);
+ setOperationAction(ISD::CTTZ , EVT::i64, Expand);
+ setOperationAction(ISD::CTTZ , EVT::i128, Expand);
+
+ setOperationAction(ISD::CTLZ , EVT::i8, Promote);
+ setOperationAction(ISD::CTLZ , EVT::i16, Promote);
+ setOperationAction(ISD::CTLZ , EVT::i32, Legal);
+ setOperationAction(ISD::CTLZ , EVT::i64, Expand);
+ setOperationAction(ISD::CTLZ , EVT::i128, Expand);
// SPU has a version of select that implements (a&~c)|(b&c), just like
// select ought to work:
- setOperationAction(ISD::SELECT, MVT::i8, Legal);
- setOperationAction(ISD::SELECT, MVT::i16, Legal);
- setOperationAction(ISD::SELECT, MVT::i32, Legal);
- setOperationAction(ISD::SELECT, MVT::i64, Legal);
-
- setOperationAction(ISD::SETCC, MVT::i8, Legal);
- setOperationAction(ISD::SETCC, MVT::i16, Legal);
- setOperationAction(ISD::SETCC, MVT::i32, Legal);
- setOperationAction(ISD::SETCC, MVT::i64, Legal);
- setOperationAction(ISD::SETCC, MVT::f64, Custom);
+ setOperationAction(ISD::SELECT, EVT::i8, Legal);
+ setOperationAction(ISD::SELECT, EVT::i16, Legal);
+ setOperationAction(ISD::SELECT, EVT::i32, Legal);
+ setOperationAction(ISD::SELECT, EVT::i64, Legal);
+
+ setOperationAction(ISD::SETCC, EVT::i8, Legal);
+ setOperationAction(ISD::SETCC, EVT::i16, Legal);
+ setOperationAction(ISD::SETCC, EVT::i32, Legal);
+ setOperationAction(ISD::SETCC, EVT::i64, Legal);
+ setOperationAction(ISD::SETCC, EVT::f64, Custom);
// Custom lower i128 -> i64 truncates
- setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
+ setOperationAction(ISD::TRUNCATE, EVT::i64, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
- setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
- setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
- setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i8, Promote);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i8, Promote);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i16, Promote);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i16, Promote);
// SPU has a legal FP -> signed INT instruction for f32, but for f64, need
// to expand to a libcall, hence the custom lowering:
- setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
- setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
- setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
- setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
- setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i128, Expand);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i128, Expand);
// FDIV on SPU requires custom lowering
- setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
+ setOperationAction(ISD::FDIV, EVT::f64, Expand); // to libcall
// SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
- setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
- setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
- setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
- setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
- setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
- setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
- setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
- setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
-
- setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
- setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
- setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
- setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
+ setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom);
+ setOperationAction(ISD::SINT_TO_FP, EVT::i16, Promote);
+ setOperationAction(ISD::SINT_TO_FP, EVT::i8, Promote);
+ setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom);
+ setOperationAction(ISD::UINT_TO_FP, EVT::i16, Promote);
+ setOperationAction(ISD::UINT_TO_FP, EVT::i8, Promote);
+ setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
+ setOperationAction(ISD::UINT_TO_FP, EVT::i64, Custom);
+
+ setOperationAction(ISD::BIT_CONVERT, EVT::i32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, EVT::f32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, EVT::i64, Legal);
+ setOperationAction(ISD::BIT_CONVERT, EVT::f64, Legal);
// We cannot sextinreg(i1). Expand to shifts.
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
// Support label based line numbers.
- setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
- for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
+ for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::f128;
++sctype) {
- MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
+ EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype;
setOperationAction(ISD::GlobalAddress, VT, Custom);
setOperationAction(ISD::ConstantPool, VT, Custom);
@@ -399,42 +399,42 @@
}
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
- setOperationAction(ISD::VASTART , MVT::Other, Custom);
+ setOperationAction(ISD::VASTART , EVT::Other, Custom);
// Use the default implementation.
- setOperationAction(ISD::VAARG , MVT::Other, Expand);
- setOperationAction(ISD::VACOPY , MVT::Other, Expand);
- setOperationAction(ISD::VAEND , MVT::Other, Expand);
- setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
+ setOperationAction(ISD::VAARG , EVT::Other, Expand);
+ setOperationAction(ISD::VACOPY , EVT::Other, Expand);
+ setOperationAction(ISD::VAEND , EVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE , EVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE , EVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64 , Expand);
// Cell SPU has instructions for converting between i64 and fp.
- setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
- setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom);
+ setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom);
// To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
- setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i32, Promote);
// BUILD_PAIR can't be handled natively, and should be expanded to shl/or
- setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
+ setOperationAction(ISD::BUILD_PAIR, EVT::i64, Expand);
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
- addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
- addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
- addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
- addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
- addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
- addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
+ addRegisterClass(EVT::v16i8, SPU::VECREGRegisterClass);
+ addRegisterClass(EVT::v8i16, SPU::VECREGRegisterClass);
+ addRegisterClass(EVT::v4i32, SPU::VECREGRegisterClass);
+ addRegisterClass(EVT::v2i64, SPU::VECREGRegisterClass);
+ addRegisterClass(EVT::v4f32, SPU::VECREGRegisterClass);
+ addRegisterClass(EVT::v2f64, SPU::VECREGRegisterClass);
// "Odd size" vector classes that we're willing to support:
- addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass);
+ addRegisterClass(EVT::v2i32, SPU::VECREGRegisterClass);
- for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
- MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
+ for (unsigned i = (unsigned)EVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
+ EVT::SimpleValueType VT = (EVT::SimpleValueType)i;
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD, VT, Legal);
@@ -465,14 +465,14 @@
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
}
- setOperationAction(ISD::AND, MVT::v16i8, Custom);
- setOperationAction(ISD::OR, MVT::v16i8, Custom);
- setOperationAction(ISD::XOR, MVT::v16i8, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
+ setOperationAction(ISD::AND, EVT::v16i8, Custom);
+ setOperationAction(ISD::OR, EVT::v16i8, Custom);
+ setOperationAction(ISD::XOR, EVT::v16i8, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4f32, Custom);
- setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
+ setOperationAction(ISD::FDIV, EVT::v4f32, Legal);
- setShiftAmountType(MVT::i32);
+ setShiftAmountType(EVT::i32);
setBooleanContents(ZeroOrNegativeOneBooleanContent);
setStackPointerRegisterToSaveRestore(SPU::R1);
@@ -539,11 +539,11 @@
// Return the Cell SPU's SETCC result type
//===----------------------------------------------------------------------===//
-MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(MVT VT) const {
+EVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
// i16 and i32 are valid SETCC result types
- return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ?
+ return ((VT == EVT::i8 || VT == EVT::i16 || VT == EVT::i32) ?
VT.getSimpleVT() :
- MVT::i32);
+ EVT::i32);
}
//===----------------------------------------------------------------------===//
@@ -562,7 +562,7 @@
within a 16-byte block, we have to rotate to extract the requested element.
For extending loads, we also want to ensure that the following sequence is
- emitted, e.g. for MVT::f32 extending load to MVT::f64:
+ emitted, e.g. for EVT::f32 extending load to EVT::f64:
\verbatim
%1 v16i8,ch = load
@@ -576,9 +576,9 @@
LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
LoadSDNode *LN = cast<LoadSDNode>(Op);
SDValue the_chain = LN->getChain();
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
- MVT InVT = LN->getMemoryVT();
- MVT OutVT = Op.getValueType();
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT InVT = LN->getMemoryVT();
+ EVT OutVT = Op.getValueType();
ISD::LoadExtType ExtType = LN->getExtensionType();
unsigned alignment = LN->getAlignment();
const valtype_map_s *vtm = getValueTypeMapEntry(InVT);
@@ -604,7 +604,7 @@
if (rotamt < 0)
rotamt += 16;
- rotate = DAG.getConstant(rotamt, MVT::i16);
+ rotate = DAG.getConstant(rotamt, EVT::i16);
// Simplify the base pointer for this case:
basePtr = basePtr.getOperand(0);
@@ -622,7 +622,7 @@
int64_t rotamt = -vtm->prefslot_byte;
if (rotamt < 0)
rotamt += 16;
- rotate = DAG.getConstant(rotamt, MVT::i16);
+ rotate = DAG.getConstant(rotamt, EVT::i16);
} else {
// Offset the rotate amount by the basePtr and the preferred slot
// byte offset
@@ -670,7 +670,7 @@
}
// Re-emit as a v16i8 vector load
- result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
+ result = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
LN->isVolatile(), 16);
@@ -678,12 +678,12 @@
the_chain = result.getValue(1);
// Rotate into the preferred slot:
- result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8,
+ result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, EVT::v16i8,
result.getValue(0), rotate);
// Convert the loaded v16i8 vector to the appropriate vector type
// specified by the operand:
- MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
+ EVT vecVT = EVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result));
@@ -701,7 +701,7 @@
result = DAG.getNode(NewOpc, dl, OutVT, result);
}
- SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
+ SDVTList retvts = DAG.getVTList(OutVT, EVT::Other);
SDValue retops[2] = {
result,
the_chain
@@ -740,17 +740,17 @@
LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
StoreSDNode *SN = cast<StoreSDNode>(Op);
SDValue Value = SN->getValue();
- MVT VT = Value.getValueType();
- MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT VT = Value.getValueType();
+ EVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
DebugLoc dl = Op.getDebugLoc();
unsigned alignment = SN->getAlignment();
switch (SN->getAddressingMode()) {
case ISD::UNINDEXED: {
// The vector type we really want to load from the 16-byte chunk.
- MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())),
- stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
+ EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits())),
+ stVecVT = EVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
SDValue alignLoadVec;
SDValue basePtr = SN->getBasePtr();
@@ -820,7 +820,7 @@
}
// Re-emit as a v16i8 vector load
- alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
+ alignLoadVec = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr,
SN->getSrcValue(), SN->getSrcValueOffset(),
SN->isVolatile(), 16);
@@ -859,7 +859,7 @@
result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
vectorizeOp, alignLoadVec,
DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::v4i32, insertEltOp));
+ EVT::v4i32, insertEltOp));
result = DAG.getStore(the_chain, dl, result, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
@@ -902,7 +902,7 @@
//! Generate the address of a constant pool entry.
static SDValue
LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
- MVT PtrVT = Op.getValueType();
+ EVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
@@ -935,7 +935,7 @@
static SDValue
LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
- MVT PtrVT = Op.getValueType();
+ EVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDValue Zero = DAG.getConstant(0, PtrVT);
@@ -960,7 +960,7 @@
static SDValue
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
- MVT PtrVT = Op.getValueType();
+ EVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
@@ -989,21 +989,21 @@
//! Custom lower double precision floating point constants
static SDValue
LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
// FIXME there is no actual debug info here
DebugLoc dl = Op.getDebugLoc();
- if (VT == MVT::f64) {
+ if (VT == EVT::f64) {
ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
assert((FP != 0) &&
"LowerConstantFP: Node is not ConstantFPSDNode");
uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
- SDValue T = DAG.getConstant(dbits, MVT::i64);
- SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
+ SDValue T = DAG.getConstant(dbits, EVT::i64);
+ SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T);
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Tvec));
}
return SDValue();
@@ -1028,11 +1028,11 @@
unsigned ArgRegIdx = 0;
unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Add DAG nodes to load the arguments or copy them out of registers.
for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
- MVT ObjectVT = Ins[ArgNo].VT;
+ EVT ObjectVT = Ins[ArgNo].VT;
unsigned ObjSize = ObjectVT.getSizeInBits()/8;
SDValue ArgVal;
@@ -1044,36 +1044,36 @@
std::string msg;
raw_string_ostream Msg(msg);
Msg << "LowerFormalArguments Unhandled argument type: "
- << ObjectVT.getMVTString();
+ << ObjectVT.getEVTString();
llvm_report_error(Msg.str());
}
- case MVT::i8:
+ case EVT::i8:
ArgRegClass = &SPU::R8CRegClass;
break;
- case MVT::i16:
+ case EVT::i16:
ArgRegClass = &SPU::R16CRegClass;
break;
- case MVT::i32:
+ case EVT::i32:
ArgRegClass = &SPU::R32CRegClass;
break;
- case MVT::i64:
+ case EVT::i64:
ArgRegClass = &SPU::R64CRegClass;
break;
- case MVT::i128:
+ case EVT::i128:
ArgRegClass = &SPU::GPRCRegClass;
break;
- case MVT::f32:
+ case EVT::f32:
ArgRegClass = &SPU::R32FPRegClass;
break;
- case MVT::f64:
+ case EVT::f64:
ArgRegClass = &SPU::R64FPRegClass;
break;
- case MVT::v2f64:
- case MVT::v4f32:
- case MVT::v2i64:
- case MVT::v4i32:
- case MVT::v8i16:
- case MVT::v16i8:
+ case EVT::v2f64:
+ case EVT::v4f32:
+ case EVT::v2i64:
+ case EVT::v4i32:
+ case EVT::v8i16:
+ case EVT::v16i8:
ArgRegClass = &SPU::VECREGRegClass;
break;
}
@@ -1108,7 +1108,7 @@
for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
- SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8);
+ SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], EVT::v16i8);
SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0);
Chain = Store.getOperand(0);
MemOps.push_back(Store);
@@ -1117,7 +1117,7 @@
ArgOffset += StackSlotSize;
}
if (!MemOps.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOps[0], MemOps.size());
}
@@ -1135,7 +1135,7 @@
(Addr << 14 >> 14) != Addr)
return 0; // Top 14 bits have to be sext of immediate.
- return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
+ return DAG.getConstant((int)C->getZExtValue() >> 2, EVT::i32).getNode();
}
SDValue
@@ -1154,7 +1154,7 @@
const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
// Handy pointer type
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Accumulate how many bytes are to be pushed on the stack, including the
// linkage area, and parameter passing area. According to the SPU ABI,
@@ -1164,7 +1164,7 @@
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
// passing.
- SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
+ SDValue StackPtr = DAG.getRegister(SPU::R1, EVT::i32);
// Figure out which arguments are going to go in registers, and which in
// memory.
@@ -1186,11 +1186,11 @@
switch (Arg.getValueType().getSimpleVT()) {
default: llvm_unreachable("Unexpected ValueType for argument!");
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- case MVT::i64:
- case MVT::i128:
+ case EVT::i8:
+ case EVT::i16:
+ case EVT::i32:
+ case EVT::i64:
+ case EVT::i128:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
@@ -1198,8 +1198,8 @@
ArgOffset += StackSlotSize;
}
break;
- case MVT::f32:
- case MVT::f64:
+ case EVT::f32:
+ case EVT::f64:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
@@ -1207,12 +1207,12 @@
ArgOffset += StackSlotSize;
}
break;
- case MVT::v2i64:
- case MVT::v2f64:
- case MVT::v4f32:
- case MVT::v4i32:
- case MVT::v8i16:
- case MVT::v16i8:
+ case EVT::v2i64:
+ case EVT::v2f64:
+ case EVT::v4f32:
+ case EVT::v4i32:
+ case EVT::v8i16:
+ case EVT::v16i8:
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
@@ -1230,7 +1230,7 @@
if (!MemOpChains.empty()) {
// Adjust the stack pointer for the stack arguments.
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains[0], MemOpChains.size());
}
@@ -1251,7 +1251,7 @@
// node so that legalize doesn't hack it.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
GlobalValue *GV = G->getGlobal();
- MVT CalleeVT = Callee.getValueType();
+ EVT CalleeVT = Callee.getValueType();
SDValue Zero = DAG.getConstant(0, PtrVT);
SDValue GA = DAG.getTargetGlobalAddress(GV, CalleeVT);
@@ -1275,7 +1275,7 @@
Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero);
}
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
- MVT CalleeVT = Callee.getValueType();
+ EVT CalleeVT = Callee.getValueType();
SDValue Zero = DAG.getConstant(0, PtrVT);
SDValue ExtSym = DAG.getTargetExternalSymbol(S->getSymbol(),
Callee.getValueType());
@@ -1303,7 +1303,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
@@ -1319,43 +1319,43 @@
// If the call has results, copy the values out of the ret val registers.
switch (Ins[0].VT.getSimpleVT()) {
default: llvm_unreachable("Unexpected ret value!");
- case MVT::Other: break;
- case MVT::i32:
- if (Ins.size() > 1 && Ins[1].VT == MVT::i32) {
+ case EVT::Other: break;
+ case EVT::i32:
+ if (Ins.size() > 1 && Ins[1].VT == EVT::i32) {
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
- MVT::i32, InFlag).getValue(1);
+ EVT::i32, InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32,
Chain.getValue(2)).getValue(1);
InVals.push_back(Chain.getValue(0));
} else {
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
}
break;
- case MVT::i64:
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64,
+ case EVT::i64:
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i64,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case MVT::i128:
- Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128,
+ case EVT::i128:
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i128,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case MVT::f32:
- case MVT::f64:
+ case EVT::f32:
+ case EVT::f64:
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
break;
- case MVT::v2f64:
- case MVT::v2i64:
- case MVT::v4f32:
- case MVT::v4i32:
- case MVT::v8i16:
- case MVT::v16i8:
+ case EVT::v2f64:
+ case EVT::v2i64:
+ case EVT::v4f32:
+ case EVT::v4i32:
+ case EVT::v8i16:
+ case EVT::v16i8:
Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
InFlag).getValue(1);
InVals.push_back(Chain.getValue(0));
@@ -1395,9 +1395,9 @@
}
if (Flag.getNode())
- return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
else
- return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain);
}
@@ -1431,10 +1431,10 @@
/// and the value fits into an unsigned 18-bit constant, and if so, return the
/// constant
SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType) {
+ EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getZExtValue();
- if (ValueType == MVT::i64) {
+ if (ValueType == EVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
@@ -1453,10 +1453,10 @@
/// and the value fits into a signed 16-bit constant, and if so, return the
/// constant
SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType) {
+ EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSExtValue();
- if (ValueType == MVT::i64) {
+ if (ValueType == EVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
@@ -1476,10 +1476,10 @@
/// and the value fits into a signed 10-bit constant, and if so, return the
/// constant
SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType) {
+ EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int64_t Value = CN->getSExtValue();
- if (ValueType == MVT::i64) {
+ if (ValueType == EVT::i64) {
uint64_t UValue = CN->getZExtValue();
uint32_t upper = uint32_t(UValue >> 32);
uint32_t lower = uint32_t(UValue);
@@ -1502,14 +1502,14 @@
/// constant vectors. Thus, we test to see if the upper and lower bytes are the
/// same value.
SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType) {
+ EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
int Value = (int) CN->getZExtValue();
- if (ValueType == MVT::i16
+ if (ValueType == EVT::i16
&& Value <= 0xffff /* truncated from uint64_t */
&& ((short) Value >> 8) == ((short) Value & 0xff))
return DAG.getTargetConstant(Value & 0xff, ValueType);
- else if (ValueType == MVT::i8
+ else if (ValueType == EVT::i8
&& (Value & 0xff) == Value)
return DAG.getTargetConstant(Value, ValueType);
}
@@ -1521,12 +1521,12 @@
/// and the value fits into a signed 16-bit constant, and if so, return the
/// constant
SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType) {
+ EVT ValueType) {
if (ConstantSDNode *CN = getVecImm(N)) {
uint64_t Value = CN->getZExtValue();
- if ((ValueType == MVT::i32
+ if ((ValueType == EVT::i32
&& ((unsigned) Value & 0xffff0000) == (unsigned) Value)
- || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
+ || (ValueType == EVT::i64 && (Value & 0xffff0000) == Value))
return DAG.getTargetConstant(Value >> 16, ValueType);
}
@@ -1536,7 +1536,7 @@
/// get_v4i32_imm - Catch-all for general 32-bit constant vectors
SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
- return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32);
+ return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i32);
}
return SDValue();
@@ -1545,7 +1545,7 @@
/// get_v4i32_imm - Catch-all for general 64-bit constant vectors
SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
if (ConstantSDNode *CN = getVecImm(N)) {
- return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
+ return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i64);
}
return SDValue();
@@ -1554,8 +1554,8 @@
//! Lower a BUILD_VECTOR instruction creatively:
static SDValue
LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = Op.getValueType();
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(Op.getNode());
assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerBUILD_VECTOR");
@@ -1580,40 +1580,40 @@
std::string msg;
raw_string_ostream Msg(msg);
Msg << "CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = "
- << VT.getMVTString();
+ << VT.getEVTString();
llvm_report_error(Msg.str());
/*NOTREACHED*/
}
- case MVT::v4f32: {
+ case EVT::v4f32: {
uint32_t Value32 = uint32_t(SplatBits);
assert(SplatBitSize == 32
&& "LowerBUILD_VECTOR: Unexpected floating point vector element.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDValue T = DAG.getConstant(Value32, MVT::i32);
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
+ SDValue T = DAG.getConstant(Value32, EVT::i32);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4f32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, T,T,T,T));
break;
}
- case MVT::v2f64: {
+ case EVT::v2f64: {
uint64_t f64val = uint64_t(SplatBits);
assert(SplatBitSize == 64
&& "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
- SDValue T = DAG.getConstant(f64val, MVT::i64);
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64,
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
+ SDValue T = DAG.getConstant(f64val, EVT::i64);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T));
break;
}
- case MVT::v16i8: {
+ case EVT::v16i8: {
// 8-bit constants have to be expanded to 16-bits
unsigned short Value16 = SplatBits /* | (SplatBits << 8) */;
SmallVector<SDValue, 8> Ops;
- Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
+ Ops.assign(8, DAG.getConstant(Value16, EVT::i16));
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v8i16, &Ops[0], Ops.size()));
}
- case MVT::v8i16: {
+ case EVT::v8i16: {
unsigned short Value16 = SplatBits;
SDValue T = DAG.getConstant(Value16, EltVT);
SmallVector<SDValue, 8> Ops;
@@ -1621,15 +1621,15 @@
Ops.assign(8, T);
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
}
- case MVT::v4i32: {
+ case EVT::v4i32: {
SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
}
- case MVT::v2i32: {
+ case EVT::v2i32: {
SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T);
}
- case MVT::v2i64: {
+ case EVT::v2i64: {
return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
}
}
@@ -1640,16 +1640,16 @@
/*!
*/
SDValue
-SPU::LowerV2I64Splat(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
+SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
DebugLoc dl) {
uint32_t upper = uint32_t(SplatVal >> 32);
uint32_t lower = uint32_t(SplatVal);
if (upper == lower) {
// Magic constant that can be matched by IL, ILA, et. al.
- SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
+ SDValue Val = DAG.getTargetConstant(upper, EVT::i32);
return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
Val, Val, Val, Val));
} else {
bool upper_special, lower_special;
@@ -1664,8 +1664,8 @@
// Both upper and lower are special, lower to a constant pool load:
if (lower_special && upper_special) {
- SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
+ SDValue SplatValCN = DAG.getConstant(SplatVal, EVT::i64);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64,
SplatValCN, SplatValCN);
}
@@ -1676,17 +1676,17 @@
// Create lower vector if not a special pattern
if (!lower_special) {
- SDValue LO32C = DAG.getConstant(lower, MVT::i32);
+ SDValue LO32C = DAG.getConstant(lower, EVT::i32);
LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
LO32C, LO32C, LO32C, LO32C));
}
// Create upper vector if not a special pattern
if (!upper_special) {
- SDValue HI32C = DAG.getConstant(upper, MVT::i32);
+ SDValue HI32C = DAG.getConstant(upper, EVT::i32);
HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
HI32C, HI32C, HI32C, HI32C));
}
@@ -1720,11 +1720,11 @@
val |= i * 4 + j + ((i & 1) * 16);
}
- ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(val, EVT::i32));
}
return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32,
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
&ShufBytes[0], ShufBytes.size()));
}
}
@@ -1753,8 +1753,8 @@
// If we have a single element being moved from V1 to V2, this can be handled
// using the C*[DX] compute mask instructions, but the vector elements have
// to be monotonically increasing with one exception element.
- MVT VecVT = V1.getValueType();
- MVT EltVT = VecVT.getVectorElementType();
+ EVT VecVT = V1.getValueType();
+ EVT EltVT = VecVT.getVectorElementType();
unsigned EltsFromV2 = 0;
unsigned V2Elt = 0;
unsigned V2EltIdx0 = 0;
@@ -1765,13 +1765,13 @@
bool monotonic = true;
bool rotate = true;
- if (EltVT == MVT::i8) {
+ if (EltVT == EVT::i8) {
V2EltIdx0 = 16;
- } else if (EltVT == MVT::i16) {
+ } else if (EltVT == EVT::i16) {
V2EltIdx0 = 8;
- } else if (EltVT == MVT::i32 || EltVT == MVT::f32) {
+ } else if (EltVT == EVT::i32 || EltVT == EVT::f32) {
V2EltIdx0 = 4;
- } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
+ } else if (EltVT == EVT::i64 || EltVT == EVT::f64) {
V2EltIdx0 = 2;
} else
llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
@@ -1819,14 +1819,14 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Initialize temporary register to 0
SDValue InitTempReg =
DAG.getCopyToReg(DAG.getEntryNode(), dl, VReg, DAG.getConstant(0, PtrVT));
// Copy register's contents as index in SHUFFLE_MASK:
SDValue ShufMaskOp =
- DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v4i32,
- DAG.getTargetConstant(V2Elt, MVT::i32),
+ DAG.getNode(SPUISD::SHUFFLE_MASK, dl, EVT::v4i32,
+ DAG.getTargetConstant(V2Elt, EVT::i32),
DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT));
// Use shuffle mask in SHUFB synthetic instruction:
return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
@@ -1835,7 +1835,7 @@
int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
- V1, DAG.getConstant(rotamt, MVT::i16));
+ V1, DAG.getConstant(rotamt, EVT::i16));
} else {
// Convert the SHUFFLE_VECTOR mask's input element units to the
// actual bytes.
@@ -1846,10 +1846,10 @@
unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i);
for (unsigned j = 0; j < BytesPerElement; ++j)
- ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
+ ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,EVT::i8));
}
- SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v16i8,
&ResultMask[0], ResultMask.size());
return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask);
}
@@ -1865,19 +1865,19 @@
ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
SmallVector<SDValue, 16> ConstVecValues;
- MVT VT;
+ EVT VT;
size_t n_copies;
// Create a constant vector:
switch (Op.getValueType().getSimpleVT()) {
default: llvm_unreachable("Unexpected constant value type in "
"LowerSCALAR_TO_VECTOR");
- case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
- case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
- case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
- case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
- case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
- case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
+ case EVT::v16i8: n_copies = 16; VT = EVT::i8; break;
+ case EVT::v8i16: n_copies = 8; VT = EVT::i16; break;
+ case EVT::v4i32: n_copies = 4; VT = EVT::i32; break;
+ case EVT::v4f32: n_copies = 4; VT = EVT::f32; break;
+ case EVT::v2i64: n_copies = 2; VT = EVT::i64; break;
+ case EVT::v2f64: n_copies = 2; VT = EVT::f64; break;
}
SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
@@ -1890,12 +1890,12 @@
// Otherwise, copy the value from one register to another:
switch (Op0.getValueType().getSimpleVT()) {
default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- case MVT::i64:
- case MVT::f32:
- case MVT::f64:
+ case EVT::i8:
+ case EVT::i16:
+ case EVT::i32:
+ case EVT::i64:
+ case EVT::f32:
+ case EVT::f64:
return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
}
}
@@ -1904,7 +1904,7 @@
}
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue N = Op.getOperand(0);
SDValue Elt = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
@@ -1915,16 +1915,16 @@
int EltNo = (int) C->getZExtValue();
// sanity checks:
- if (VT == MVT::i8 && EltNo >= 16)
+ if (VT == EVT::i8 && EltNo >= 16)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
- else if (VT == MVT::i16 && EltNo >= 8)
+ else if (VT == EVT::i16 && EltNo >= 8)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
- else if (VT == MVT::i32 && EltNo >= 4)
+ else if (VT == EVT::i32 && EltNo >= 4)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
- else if (VT == MVT::i64 && EltNo >= 2)
+ else if (VT == EVT::i64 && EltNo >= 2)
llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
- if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
+ if (EltNo == 0 && (VT == EVT::i32 || VT == EVT::i64)) {
// i32 and i64: Element 0 is the preferred slot
return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
}
@@ -1936,21 +1936,21 @@
switch (VT.getSimpleVT()) {
default:
assert(false && "Invalid value type!");
- case MVT::i8: {
+ case EVT::i8: {
prefslot_begin = prefslot_end = 3;
break;
}
- case MVT::i16: {
+ case EVT::i16: {
prefslot_begin = 2; prefslot_end = 3;
break;
}
- case MVT::i32:
- case MVT::f32: {
+ case EVT::i32:
+ case EVT::f32: {
prefslot_begin = 0; prefslot_end = 3;
break;
}
- case MVT::i64:
- case MVT::f64: {
+ case EVT::i64:
+ case EVT::f64: {
prefslot_begin = 0; prefslot_end = 7;
break;
}
@@ -1982,11 +1982,11 @@
(ShufBytes[bidx+1] << 16) |
(ShufBytes[bidx+2] << 8) |
ShufBytes[bidx+3]);
- ShufMask[i] = DAG.getConstant(bits, MVT::i32);
+ ShufMask[i] = DAG.getConstant(bits, EVT::i32);
}
SDValue ShufMaskVec =
- DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
&ShufMask[0], sizeof(ShufMask)/sizeof(ShufMask[0]));
retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
@@ -1995,15 +1995,15 @@
} else {
// Variable index: Rotate the requested element into slot 0, then replicate
// slot 0 across the vector
- MVT VecVT = N.getValueType();
+ EVT VecVT = N.getValueType();
if (!VecVT.isSimple() || !VecVT.isVector() || !VecVT.is128BitVector()) {
llvm_report_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit"
"vector type!");
}
// Make life easier by making sure the index is zero-extended to i32
- if (Elt.getValueType() != MVT::i32)
- Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
+ if (Elt.getValueType() != EVT::i32)
+ Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Elt);
// Scale the index to a bit/byte shift quantity
APInt scaleFactor =
@@ -2013,8 +2013,8 @@
if (scaleShift > 0) {
// Scale the shift factor:
- Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
- DAG.getConstant(scaleShift, MVT::i32));
+ Elt = DAG.getNode(ISD::SHL, dl, EVT::i32, Elt,
+ DAG.getConstant(scaleShift, EVT::i32));
}
vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt);
@@ -2028,30 +2028,30 @@
llvm_report_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
"type");
/*NOTREACHED*/
- case MVT::i8: {
- SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ case EVT::i8: {
+ SDValue factor = DAG.getConstant(0x00000000, EVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
factor, factor, factor, factor);
break;
}
- case MVT::i16: {
- SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ case EVT::i16: {
+ SDValue factor = DAG.getConstant(0x00010001, EVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
factor, factor, factor, factor);
break;
}
- case MVT::i32:
- case MVT::f32: {
- SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ case EVT::i32:
+ case EVT::f32: {
+ SDValue factor = DAG.getConstant(0x00010203, EVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
factor, factor, factor, factor);
break;
}
- case MVT::i64:
- case MVT::f64: {
- SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
- SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ case EVT::i64:
+ case EVT::f64: {
+ SDValue loFactor = DAG.getConstant(0x00010203, EVT::i32);
+ SDValue hiFactor = DAG.getConstant(0x04050607, EVT::i32);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
loFactor, hiFactor, loFactor, hiFactor);
break;
}
@@ -2070,12 +2070,12 @@
SDValue ValOp = Op.getOperand(1);
SDValue IdxOp = Op.getOperand(2);
DebugLoc dl = Op.getDebugLoc();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
- MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $sp ($1) because it's always 16-byte aligned and it's available:
SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
@@ -2086,7 +2086,7 @@
DAG.getNode(SPUISD::SHUFB, dl, VT,
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
VecOp,
- DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask));
+ DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4i32, ShufMask));
return result;
}
@@ -2096,9 +2096,9 @@
{
SDValue N0 = Op.getOperand(0); // Everything has at least one operand
DebugLoc dl = Op.getDebugLoc();
- MVT ShiftVT = TLI.getShiftAmountTy();
+ EVT ShiftVT = TLI.getShiftAmountTy();
- assert(Op.getValueType() == MVT::i8);
+ assert(Op.getValueType() == EVT::i8);
switch (Opc) {
default:
llvm_unreachable("Unhandled i8 math operator");
@@ -2108,10 +2108,10 @@
// 8-bit addition: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
- DAG.getNode(Opc, dl, MVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
+ DAG.getNode(Opc, dl, EVT::i16, N0, N1));
}
@@ -2119,17 +2119,17 @@
// 8-bit subtraction: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
- DAG.getNode(Opc, dl, MVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
+ DAG.getNode(Opc, dl, EVT::i16, N0, N1));
}
case ISD::ROTR:
case ISD::ROTL: {
SDValue N1 = Op.getOperand(1);
- MVT N1VT = N1.getValueType();
+ EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = N1.getValueType().bitsLT(ShiftVT)
? ISD::ZERO_EXTEND
@@ -2139,20 +2139,20 @@
// Replicate lower 8-bits into upper 8:
SDValue ExpandArg =
- DAG.getNode(ISD::OR, dl, MVT::i16, N0,
- DAG.getNode(ISD::SHL, dl, MVT::i16,
- N0, DAG.getConstant(8, MVT::i32)));
+ DAG.getNode(ISD::OR, dl, EVT::i16, N0,
+ DAG.getNode(ISD::SHL, dl, EVT::i16,
+ N0, DAG.getConstant(8, EVT::i32)));
// Truncate back down to i8
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
- DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
+ DAG.getNode(Opc, dl, EVT::i16, ExpandArg, N1));
}
case ISD::SRL:
case ISD::SHL: {
SDValue N1 = Op.getOperand(1);
- MVT N1VT = N1.getValueType();
+ EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
+ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = ISD::ZERO_EXTEND;
@@ -2162,14 +2162,14 @@
N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
}
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
- DAG.getNode(Opc, dl, MVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
+ DAG.getNode(Opc, dl, EVT::i16, N0, N1));
}
case ISD::SRA: {
SDValue N1 = Op.getOperand(1);
- MVT N1VT = N1.getValueType();
+ EVT N1VT = N1.getValueType();
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
if (!N1VT.bitsEq(ShiftVT)) {
unsigned N1Opc = ISD::SIGN_EXTEND;
@@ -2178,16 +2178,16 @@
N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
}
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
- DAG.getNode(Opc, dl, MVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
+ DAG.getNode(Opc, dl, EVT::i16, N0, N1));
}
case ISD::MUL: {
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
- DAG.getNode(Opc, dl, MVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8,
+ DAG.getNode(Opc, dl, EVT::i16, N0, N1));
break;
}
}
@@ -2200,7 +2200,7 @@
LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
SDValue ConstVec;
SDValue Arg;
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
ConstVec = Op.getOperand(0);
@@ -2230,7 +2230,7 @@
HasAnyUndefs, minSplatBits)
&& minSplatBits <= SplatBitSize) {
uint64_t SplatBits = APSplatBits.getZExtValue();
- SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
+ SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, EVT::i8);
SmallVector<SDValue, 16> tcVec;
tcVec.assign(16, tc);
@@ -2251,33 +2251,33 @@
ones per byte, which then have to be accumulated.
*/
static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
- MVT VT = Op.getValueType();
- MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
+ EVT VT = Op.getValueType();
+ EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
switch (VT.getSimpleVT()) {
default:
assert(false && "Invalid value type!");
- case MVT::i8: {
+ case EVT::i8: {
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, MVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, EVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i8, CNTB, Elt0);
}
- case MVT::i16: {
+ case EVT::i16: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, MVT::i16);
- SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
- SDValue Shift1 = DAG.getConstant(8, MVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, EVT::i16);
+ SDValue Mask0 = DAG.getConstant(0x0f, EVT::i16);
+ SDValue Shift1 = DAG.getConstant(8, EVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
@@ -2285,22 +2285,22 @@
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, CNTB, Elt0);
SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
- SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
+ SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i16);
- return DAG.getNode(ISD::AND, dl, MVT::i16,
- DAG.getNode(ISD::ADD, dl, MVT::i16,
- DAG.getNode(ISD::SRL, dl, MVT::i16,
+ return DAG.getNode(ISD::AND, dl, EVT::i16,
+ DAG.getNode(ISD::ADD, dl, EVT::i16,
+ DAG.getNode(ISD::SRL, dl, EVT::i16,
Tmp1, Shift1),
Tmp1),
Mask0);
}
- case MVT::i32: {
+ case EVT::i32: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
@@ -2308,10 +2308,10 @@
unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
SDValue N = Op.getOperand(0);
- SDValue Elt0 = DAG.getConstant(0, MVT::i32);
- SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
- SDValue Shift1 = DAG.getConstant(16, MVT::i32);
- SDValue Shift2 = DAG.getConstant(8, MVT::i32);
+ SDValue Elt0 = DAG.getConstant(0, EVT::i32);
+ SDValue Mask0 = DAG.getConstant(0xff, EVT::i32);
+ SDValue Shift1 = DAG.getConstant(16, EVT::i32);
+ SDValue Shift2 = DAG.getConstant(8, EVT::i32);
SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
@@ -2319,35 +2319,35 @@
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32, CNTB, Elt0);
SDValue CNTB_rescopy =
DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
SDValue Comp1 =
- DAG.getNode(ISD::SRL, dl, MVT::i32,
- DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
+ DAG.getNode(ISD::SRL, dl, EVT::i32,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32),
Shift1);
SDValue Sum1 =
- DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
- DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
+ DAG.getNode(ISD::ADD, dl, EVT::i32, Comp1,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32));
SDValue Sum1_rescopy =
DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1);
SDValue Comp2 =
- DAG.getNode(ISD::SRL, dl, MVT::i32,
- DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
+ DAG.getNode(ISD::SRL, dl, EVT::i32,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32),
Shift2);
SDValue Sum2 =
- DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
- DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
+ DAG.getNode(ISD::ADD, dl, EVT::i32, Comp2,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32));
- return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
+ return DAG.getNode(ISD::AND, dl, EVT::i32, Sum2, Mask0);
}
- case MVT::i64:
+ case EVT::i64:
break;
}
@@ -2361,12 +2361,12 @@
*/
static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
SPUTargetLowering &TLI) {
- MVT OpVT = Op.getValueType();
+ EVT OpVT = Op.getValueType();
SDValue Op0 = Op.getOperand(0);
- MVT Op0VT = Op0.getValueType();
+ EVT Op0VT = Op0.getValueType();
- if ((OpVT == MVT::i32 && Op0VT == MVT::f64)
- || OpVT == MVT::i64) {
+ if ((OpVT == EVT::i32 && Op0VT == EVT::f64)
+ || OpVT == EVT::i64) {
// Convert f32 / f64 to i32 / i64 via libcall.
RTLIB::Libcall LC =
(Op.getOpcode() == ISD::FP_TO_SINT)
@@ -2387,12 +2387,12 @@
*/
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
SPUTargetLowering &TLI) {
- MVT OpVT = Op.getValueType();
+ EVT OpVT = Op.getValueType();
SDValue Op0 = Op.getOperand(0);
- MVT Op0VT = Op0.getValueType();
+ EVT Op0VT = Op0.getValueType();
- if ((OpVT == MVT::f64 && Op0VT == MVT::i32)
- || Op0VT == MVT::i64) {
+ if ((OpVT == EVT::f64 && Op0VT == EVT::i32)
+ || Op0VT == EVT::i64) {
// Convert i32, i64 to f64 via libcall:
RTLIB::Libcall LC =
(Op.getOpcode() == ISD::SINT_TO_FP)
@@ -2408,7 +2408,7 @@
//! Lower ISD::SETCC
/*!
- This handles MVT::f64 (double floating point) condition lowering
+ This handles EVT::f64 (double floating point) condition lowering
*/
static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
@@ -2418,25 +2418,25 @@
SDValue lhs = Op.getOperand(0);
SDValue rhs = Op.getOperand(1);
- MVT lhsVT = lhs.getValueType();
- assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n");
+ EVT lhsVT = lhs.getValueType();
+ assert(lhsVT == EVT::f64 && "LowerSETCC: type other than EVT::64\n");
- MVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType());
+ EVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType());
APInt ccResultOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
- MVT IntVT(MVT::i64);
+ EVT IntVT(EVT::i64);
// Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
// selected to a NOP:
SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs);
SDValue lhsHi32 =
- DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
+ DAG.getNode(ISD::TRUNCATE, dl, EVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT,
- i64lhs, DAG.getConstant(32, MVT::i32)));
+ i64lhs, DAG.getConstant(32, EVT::i32)));
SDValue lhsHi32abs =
- DAG.getNode(ISD::AND, dl, MVT::i32,
- lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
+ DAG.getNode(ISD::AND, dl, EVT::i32,
+ lhsHi32, DAG.getConstant(0x7fffffff, EVT::i32));
SDValue lhsLo32 =
- DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
+ DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, i64lhs);
// SETO and SETUO only use the lhs operand:
if (CC->get() == ISD::SETO) {
@@ -2453,33 +2453,33 @@
return DAG.getNode(ISD::AND, dl, ccResultVT,
DAG.getSetCC(dl, ccResultVT,
lhsHi32abs,
- DAG.getConstant(0x7ff00000, MVT::i32),
+ DAG.getConstant(0x7ff00000, EVT::i32),
ISD::SETGE),
DAG.getSetCC(dl, ccResultVT,
lhsLo32,
- DAG.getConstant(0, MVT::i32),
+ DAG.getConstant(0, EVT::i32),
ISD::SETGT));
}
SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
SDValue rhsHi32 =
- DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
+ DAG.getNode(ISD::TRUNCATE, dl, EVT::i32,
DAG.getNode(ISD::SRL, dl, IntVT,
- i64rhs, DAG.getConstant(32, MVT::i32)));
+ i64rhs, DAG.getConstant(32, EVT::i32)));
// If a value is negative, subtract from the sign magnitude constant:
SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT);
// Convert the sign-magnitude representation into 2's complement:
SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
- lhsHi32, DAG.getConstant(31, MVT::i32));
+ lhsHi32, DAG.getConstant(31, EVT::i32));
SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs);
SDValue lhsSelect =
DAG.getNode(ISD::SELECT, dl, IntVT,
lhsSelectMask, lhsSignMag2TC, i64lhs);
SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
- rhsHi32, DAG.getConstant(31, MVT::i32));
+ rhsHi32, DAG.getConstant(31, EVT::i32));
SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs);
SDValue rhsSelect =
DAG.getNode(ISD::SELECT, dl, IntVT,
@@ -2517,10 +2517,10 @@
if ((CC->get() & 0x8) == 0) {
// Ordered comparison:
SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT,
- lhs, DAG.getConstantFP(0.0, MVT::f64),
+ lhs, DAG.getConstantFP(0.0, EVT::f64),
ISD::SETO);
SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT,
- rhs, DAG.getConstantFP(0.0, MVT::f64),
+ rhs, DAG.getConstantFP(0.0, EVT::f64),
ISD::SETO);
SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN);
@@ -2544,7 +2544,7 @@
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue lhs = Op.getOperand(0);
SDValue rhs = Op.getOperand(1);
SDValue trueval = Op.getOperand(2);
@@ -2573,25 +2573,25 @@
static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
{
// Type to truncate to
- MVT VT = Op.getValueType();
- MVT::SimpleValueType simpleVT = VT.getSimpleVT();
- MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
+ EVT VT = Op.getValueType();
+ EVT::SimpleValueType simpleVT = VT.getSimpleVT();
+ EVT VecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
DebugLoc dl = Op.getDebugLoc();
// Type to truncate from
SDValue Op0 = Op.getOperand(0);
- MVT Op0VT = Op0.getValueType();
+ EVT Op0VT = Op0.getValueType();
- if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
+ if (Op0VT.getSimpleVT() == EVT::i128 && simpleVT == EVT::i64) {
// Create shuffle mask, least significant doubleword of quadword
unsigned maskHigh = 0x08090a0b;
unsigned maskLow = 0x0c0d0e0f;
// Use a shuffle to perform the truncation
- SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
- DAG.getConstant(maskHigh, MVT::i32),
- DAG.getConstant(maskLow, MVT::i32),
- DAG.getConstant(maskHigh, MVT::i32),
- DAG.getConstant(maskLow, MVT::i32));
+ SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ DAG.getConstant(maskHigh, EVT::i32),
+ DAG.getConstant(maskLow, EVT::i32),
+ DAG.getConstant(maskHigh, EVT::i32),
+ DAG.getConstant(maskLow, EVT::i32));
SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT,
Op0, Op0, shufMask);
@@ -2611,7 +2611,7 @@
SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
{
unsigned Opc = (unsigned) Op.getOpcode();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
switch (Opc) {
default: {
@@ -2647,7 +2647,7 @@
case ISD::SRL:
case ISD::SHL:
case ISD::SRA: {
- if (VT == MVT::i8)
+ if (VT == EVT::i8)
return LowerI8Math(Op, DAG, Opc, *this);
break;
}
@@ -2680,7 +2680,7 @@
// Vector and i8 multiply:
case ISD::MUL:
- if (VT == MVT::i8)
+ if (VT == EVT::i8)
return LowerI8Math(Op, DAG, Opc, *this);
case ISD::CTPOP:
@@ -2705,7 +2705,7 @@
{
#if 0
unsigned Opc = (unsigned) N->getOpcode();
- MVT OpVT = N->getValueType(0);
+ EVT OpVT = N->getValueType(0);
switch (Opc) {
default: {
@@ -2735,8 +2735,8 @@
const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
SelectionDAG &DAG = DCI.DAG;
SDValue Op0 = N->getOperand(0); // everything has at least one operand
- MVT NodeVT = N->getValueType(0); // The node's value type
- MVT Op0VT = Op0.getValueType(); // The first operand's result
+ EVT NodeVT = N->getValueType(0); // The node's value type
+ EVT Op0VT = Op0.getValueType(); // The first operand's result
SDValue Result; // Initially, empty result
DebugLoc dl = N->getDebugLoc();
@@ -2938,20 +2938,20 @@
std::pair<unsigned, const TargetRegisterClass*>
SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const
+ EVT VT) const
{
if (Constraint.size() == 1) {
// GCC RS6000 Constraint Letters
switch (Constraint[0]) {
case 'b': // R1-R31
case 'r': // R0-R31
- if (VT == MVT::i64)
+ if (VT == EVT::i64)
return std::make_pair(0U, SPU::R64CRegisterClass);
return std::make_pair(0U, SPU::R32CRegisterClass);
case 'f':
- if (VT == MVT::f32)
+ if (VT == EVT::f32)
return std::make_pair(0U, SPU::R32FPRegisterClass);
- else if (VT == MVT::f64)
+ else if (VT == EVT::f64)
return std::make_pair(0U, SPU::R64FPRegisterClass);
break;
case 'v':
@@ -3006,10 +3006,10 @@
return 1;
case ISD::SETCC: {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
- if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
- VT = MVT::i32;
+ if (VT != EVT::i8 && VT != EVT::i16 && VT != EVT::i32) {
+ VT = EVT::i32;
}
return VT.getSizeInBits();
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Mon Aug 10 17:56:29 2009
@@ -64,22 +64,22 @@
//! Utility functions specific to CellSPU:
namespace SPU {
SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
- MVT ValueType);
+ EVT ValueType);
SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
const SPUTargetMachine &TM);
- //! Simplify a MVT::v2i64 constant splat to CellSPU-ready form
- SDValue LowerV2I64Splat(MVT OpVT, SelectionDAG &DAG, uint64_t splat,
+ //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
+ SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
DebugLoc dl);
}
@@ -109,7 +109,7 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - Return the ValueType for ISD::SETCC
- virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const;
+ virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const;
//! Custom lowering hooks
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
@@ -134,7 +134,7 @@
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
bool hasMemory,
Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Mon Aug 10 17:56:29 2009
@@ -144,7 +144,7 @@
def lo16 : PatLeaf<(imm), [{
// lo16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
- if (N->getValueType(0) == MVT::i32) {
+ if (N->getValueType(0) == EVT::i32) {
uint32_t val = N->getZExtValue();
return ((val & 0x0000ffff) == val);
}
@@ -155,10 +155,10 @@
def hi16 : PatLeaf<(imm), [{
// hi16 predicate - returns true if the immediate has all zeros in the
// low order bits and is a 32-bit constant:
- if (N->getValueType(0) == MVT::i32) {
+ if (N->getValueType(0) == EVT::i32) {
uint32_t val = uint32_t(N->getZExtValue());
return ((val & 0xffff0000) == val);
- } else if (N->getValueType(0) == MVT::i64) {
+ } else if (N->getValueType(0) == EVT::i64) {
uint64_t val = N->getZExtValue();
return ((val & 0xffff0000ULL) == val);
}
@@ -208,7 +208,7 @@
// Does the SFP constant only have upp 16 bits set?
def hi16_f32 : PatLeaf<(fpimm), [{
- if (N->getValueType(0) == MVT::f32) {
+ if (N->getValueType(0) == EVT::f32) {
uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
return ((val & 0xffff0000) == val);
}
@@ -218,7 +218,7 @@
// Does the SFP constant fit into 18 bits?
def fpimm18 : PatLeaf<(fpimm), [{
- if (N->getValueType(0) == MVT::f32) {
+ if (N->getValueType(0) == EVT::f32) {
uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
return ((Value & ((1 << 19) - 1)) == Value);
}
@@ -238,7 +238,7 @@
// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
+ return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8);
}]>;
// v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
@@ -246,14 +246,14 @@
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0;
}], v16i8SExt8Imm_xform>;
// v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
+ return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8);
}]>;
// v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
@@ -261,114 +261,114 @@
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8U8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0;
}], v16i8U8Imm_xform>;
// v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
+ return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16);
}]>;
// v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16).getNode() != 0;
}], v8i16SExt8Imm_xform>;
// v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16);
}]>;
// v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0;
}], v8i16SExt10Imm_xform>;
// v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
// immediate constant load for v8i16 vectors.
def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16);
}]>;
// v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v8i16Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0;
}], v8i16Uns10Imm_xform>;
// v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v8i16 vectors.
def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
+ return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16);
}]>;
// v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16).getNode() != 0;
}], v8i16Uns16Imm_xform>;
// v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
// immediate constant load for v4i32 vectors.
def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32);
}]>;
// v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0;
}], v4i32SExt10Imm_xform>;
// v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
// immediate constant load for v4i32 vectors.
def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32);
}]>;
// v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v4i32Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0;
}], v4i32Uns10Imm_xform>;
// v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v4i32 vectors.
def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
+ return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32);
}]>;
// v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32).getNode() != 0;
}], v4i32SExt16Imm_xform>;
// v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
// immediate constant load for v4i32 vectors.
def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
+ return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32);
}]>;
// v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
// works in conjunction with its transform function.
def v4i32Uns18Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
+ return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32).getNode() != 0;
}], v4i32Uns18Imm_xform>;
// ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
// load.
def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
+ return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32);
}]>;
/// immILHUvec: Predicate test for a ILHU constant vector.
def immILHUvec: PatLeaf<(build_vector), [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
+ return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32).getNode() != 0;
}], ILHUvec_get_imm>;
// Catch-all for any other i32 vector constants
@@ -383,42 +383,42 @@
// v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
// immediate constant load for v2i64 vectors.
def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64);
}]>;
// v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v2i64SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64).getNode() != 0;
}], v2i64SExt10Imm_xform>;
// v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
// immediate constant load for v2i64 vectors.
def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
+ return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64);
}]>;
// v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v2i64SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64).getNode() != 0;
}], v2i64SExt16Imm_xform>;
// v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
// immediate constant load for v2i64 vectors.
def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
- return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
+ return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64);
}]>;
// v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
// works in conjunction with its transform function.
def v2i64Uns18Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
+ return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64).getNode() != 0;
}], v2i64Uns18Imm_xform>;
/// immILHUvec: Predicate test for a ILHU constant vector.
def immILHUvec_i64: PatLeaf<(build_vector), [{
- return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
+ return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i64).getNode() != 0;
}], ILHUvec_get_imm>;
// Catch-all for any other i32 vector constants
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Mon Aug 10 17:56:29 2009
@@ -78,8 +78,8 @@
SDValue &Base, SDValue &Disp) {
// Try to match frame address first.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
- Disp = CurDAG->getTargetConstant(0, MVT::i16);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16);
+ Disp = CurDAG->getTargetConstant(0, EVT::i16);
return true;
}
@@ -92,11 +92,11 @@
if (((CVal << 48) >> 48) == CVal) {
SDValue N0 = Addr.getOperand(0);
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0))
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16);
else
Base = N0;
- Disp = CurDAG->getTargetConstant(CVal, MVT::i16);
+ Disp = CurDAG->getTargetConstant(CVal, EVT::i16);
return true;
}
}
@@ -105,18 +105,18 @@
SDValue N0 = Addr.getOperand(0);
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
Base = CurDAG->getTargetGlobalAddress(G->getGlobal(),
- MVT::i16, G->getOffset());
- Disp = CurDAG->getTargetConstant(0, MVT::i16);
+ EVT::i16, G->getOffset());
+ Disp = CurDAG->getTargetConstant(0, EVT::i16);
return true;
} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) {
- Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16);
- Disp = CurDAG->getTargetConstant(0, MVT::i16);
+ Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), EVT::i16);
+ Disp = CurDAG->getTargetConstant(0, EVT::i16);
}
break;
};
Base = Addr;
- Disp = CurDAG->getTargetConstant(0, MVT::i16);
+ Disp = CurDAG->getTargetConstant(0, EVT::i16);
return true;
}
@@ -168,14 +168,14 @@
switch (Node->getOpcode()) {
default: break;
case ISD::FrameIndex: {
- assert(Op.getValueType() == MVT::i16);
+ assert(Op.getValueType() == EVT::i16);
int FI = cast<FrameIndexSDNode>(Node)->getIndex();
- SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i16);
if (Node->hasOneUse())
- return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
- TFI, CurDAG->getTargetConstant(0, MVT::i16));
- return CurDAG->getTargetNode(MSP430::ADD16ri, dl, MVT::i16,
- TFI, CurDAG->getTargetConstant(0, MVT::i16));
+ return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, EVT::i16,
+ TFI, CurDAG->getTargetConstant(0, EVT::i16));
+ return CurDAG->getTargetNode(MSP430::ADD16ri, dl, EVT::i16,
+ TFI, CurDAG->getTargetConstant(0, EVT::i16));
}
}
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Mon Aug 10 17:56:29 2009
@@ -42,8 +42,8 @@
Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
- addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
- addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
+ addRegisterClass(EVT::i8, MSP430::GR8RegisterClass);
+ addRegisterClass(EVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
computeRegisterProperties();
@@ -55,75 +55,75 @@
// Even if we have only 1 bit shift here, we can perform
// shifts of the whole bitwidth 1 bit per step.
- setShiftAmountType(MVT::i8);
+ setShiftAmountType(EVT::i8);
setStackPointerRegisterToSaveRestore(MSP430::SPW);
setBooleanContents(ZeroOrOneBooleanContent);
setSchedulingPreference(SchedulingForLatency);
- setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
+ setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand);
// We don't have any truncstores
- setTruncStoreAction(MVT::i16, MVT::i8, Expand);
+ setTruncStoreAction(EVT::i16, EVT::i8, Expand);
- setOperationAction(ISD::SRA, MVT::i8, Custom);
- setOperationAction(ISD::SHL, MVT::i8, Custom);
- setOperationAction(ISD::SRL, MVT::i8, Custom);
- setOperationAction(ISD::SRA, MVT::i16, Custom);
- setOperationAction(ISD::SHL, MVT::i16, Custom);
- setOperationAction(ISD::SRL, MVT::i16, Custom);
- setOperationAction(ISD::ROTL, MVT::i8, Expand);
- setOperationAction(ISD::ROTR, MVT::i8, Expand);
- setOperationAction(ISD::ROTL, MVT::i16, Expand);
- setOperationAction(ISD::ROTR, MVT::i16, Expand);
- setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
- setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
- setOperationAction(ISD::BR_JT, MVT::Other, Expand);
- setOperationAction(ISD::BRIND, MVT::Other, Expand);
- setOperationAction(ISD::BR_CC, MVT::i8, Custom);
- setOperationAction(ISD::BR_CC, MVT::i16, Custom);
- setOperationAction(ISD::BRCOND, MVT::Other, Expand);
- setOperationAction(ISD::SETCC, MVT::i8, Expand);
- setOperationAction(ISD::SETCC, MVT::i16, Expand);
- setOperationAction(ISD::SELECT, MVT::i8, Expand);
- setOperationAction(ISD::SELECT, MVT::i16, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
- setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
- setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
-
- setOperationAction(ISD::CTTZ, MVT::i8, Expand);
- setOperationAction(ISD::CTTZ, MVT::i16, Expand);
- setOperationAction(ISD::CTLZ, MVT::i8, Expand);
- setOperationAction(ISD::CTLZ, MVT::i16, Expand);
- setOperationAction(ISD::CTPOP, MVT::i8, Expand);
- setOperationAction(ISD::CTPOP, MVT::i16, Expand);
-
- setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
- setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
- setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
- setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
- setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
- setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
+ setOperationAction(ISD::SRA, EVT::i8, Custom);
+ setOperationAction(ISD::SHL, EVT::i8, Custom);
+ setOperationAction(ISD::SRL, EVT::i8, Custom);
+ setOperationAction(ISD::SRA, EVT::i16, Custom);
+ setOperationAction(ISD::SHL, EVT::i16, Custom);
+ setOperationAction(ISD::SRL, EVT::i16, Custom);
+ setOperationAction(ISD::ROTL, EVT::i8, Expand);
+ setOperationAction(ISD::ROTR, EVT::i8, Expand);
+ setOperationAction(ISD::ROTL, EVT::i16, Expand);
+ setOperationAction(ISD::ROTR, EVT::i16, Expand);
+ setOperationAction(ISD::GlobalAddress, EVT::i16, Custom);
+ setOperationAction(ISD::ExternalSymbol, EVT::i16, Custom);
+ setOperationAction(ISD::BR_JT, EVT::Other, Expand);
+ setOperationAction(ISD::BRIND, EVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, EVT::i8, Custom);
+ setOperationAction(ISD::BR_CC, EVT::i16, Custom);
+ setOperationAction(ISD::BRCOND, EVT::Other, Expand);
+ setOperationAction(ISD::SETCC, EVT::i8, Expand);
+ setOperationAction(ISD::SETCC, EVT::i16, Expand);
+ setOperationAction(ISD::SELECT, EVT::i8, Expand);
+ setOperationAction(ISD::SELECT, EVT::i16, Expand);
+ setOperationAction(ISD::SELECT_CC, EVT::i8, Custom);
+ setOperationAction(ISD::SELECT_CC, EVT::i16, Custom);
+ setOperationAction(ISD::SIGN_EXTEND, EVT::i16, Custom);
+
+ setOperationAction(ISD::CTTZ, EVT::i8, Expand);
+ setOperationAction(ISD::CTTZ, EVT::i16, Expand);
+ setOperationAction(ISD::CTLZ, EVT::i8, Expand);
+ setOperationAction(ISD::CTLZ, EVT::i16, Expand);
+ setOperationAction(ISD::CTPOP, EVT::i8, Expand);
+ setOperationAction(ISD::CTPOP, EVT::i16, Expand);
+
+ setOperationAction(ISD::SHL_PARTS, EVT::i8, Expand);
+ setOperationAction(ISD::SHL_PARTS, EVT::i16, Expand);
+ setOperationAction(ISD::SRL_PARTS, EVT::i8, Expand);
+ setOperationAction(ISD::SRL_PARTS, EVT::i16, Expand);
+ setOperationAction(ISD::SRA_PARTS, EVT::i8, Expand);
+ setOperationAction(ISD::SRA_PARTS, EVT::i16, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
// FIXME: Implement efficiently multiplication by a constant
- setOperationAction(ISD::MUL, MVT::i16, Expand);
- setOperationAction(ISD::MULHS, MVT::i16, Expand);
- setOperationAction(ISD::MULHU, MVT::i16, Expand);
- setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
- setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
-
- setOperationAction(ISD::UDIV, MVT::i16, Expand);
- setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
- setOperationAction(ISD::UREM, MVT::i16, Expand);
- setOperationAction(ISD::SDIV, MVT::i16, Expand);
- setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
- setOperationAction(ISD::SREM, MVT::i16, Expand);
+ setOperationAction(ISD::MUL, EVT::i16, Expand);
+ setOperationAction(ISD::MULHS, EVT::i16, Expand);
+ setOperationAction(ISD::MULHU, EVT::i16, Expand);
+ setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand);
+ setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand);
+
+ setOperationAction(ISD::UDIV, EVT::i16, Expand);
+ setOperationAction(ISD::UDIVREM, EVT::i16, Expand);
+ setOperationAction(ISD::UREM, EVT::i16, Expand);
+ setOperationAction(ISD::SDIV, EVT::i16, Expand);
+ setOperationAction(ISD::SDIVREM, EVT::i16, Expand);
+ setOperationAction(ISD::SREM, EVT::i16, Expand);
}
SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
@@ -220,7 +220,7 @@
CCValAssign &VA = ArgLocs[i];
if (VA.isRegLoc()) {
// Arguments passed in registers
- MVT RegVT = VA.getLocVT();
+ EVT RegVT = VA.getLocVT();
switch (RegVT.getSimpleVT()) {
default:
{
@@ -230,7 +230,7 @@
#endif
llvm_unreachable(0);
}
- case MVT::i16:
+ case EVT::i16:
unsigned VReg =
RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
@@ -266,7 +266,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
- SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
+ SDValue FIN = DAG.getFrameIndex(FI, EVT::i16);
InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
PseudoSourceValue::getFixedStack(FI), 0));
}
@@ -315,10 +315,10 @@
}
if (Flag.getNode())
- return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
+ return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain, Flag);
// Return Void
- return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
+ return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain);
}
/// LowerCCCCallTo - functions arguments are copied from virtual regs to
@@ -395,7 +395,7 @@
// Transform all store nodes into one single node because all store nodes are
// independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain and
@@ -412,12 +412,12 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i16);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i16);
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -479,7 +479,7 @@
SelectionDAG &DAG) {
unsigned Opc = Op.getOpcode();
SDNode* N = Op.getNode();
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = N->getDebugLoc();
// We currently only lower shifts of constant argument.
@@ -564,7 +564,7 @@
break;
}
- return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
+ return DAG.getNode(MSP430ISD::CMP, dl, EVT::Flag, LHS, RHS);
}
@@ -581,7 +581,7 @@
return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
Chain,
- Dest, DAG.getConstant(TargetCC, MVT::i8),
+ Dest, DAG.getConstant(TargetCC, EVT::i8),
Flag);
}
@@ -596,11 +596,11 @@
unsigned TargetCC = MSP430::COND_INVALID;
SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
- SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
+ SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag);
SmallVector<SDValue, 4> Ops;
Ops.push_back(TrueV);
Ops.push_back(FalseV);
- Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
+ Ops.push_back(DAG.getConstant(TargetCC, EVT::i8));
Ops.push_back(Flag);
return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
@@ -609,10 +609,10 @@
SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
SelectionDAG &DAG) {
SDValue Val = Op.getOperand(0);
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
- assert(VT == MVT::i16 && "Only support i16 for now!");
+ assert(VT == EVT::i16 && "Only support i16 for now!");
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Aug 10 17:56:29 2009
@@ -95,7 +95,7 @@
// getI32Imm - Return a target constant with the specified
// value, of type i32.
inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i32);
+ return CurDAG->getTargetConstant(Imm, EVT::i32);
}
@@ -142,8 +142,8 @@
{
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
- Offset = CurDAG->getTargetConstant(0, MVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
+ Offset = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -151,7 +151,7 @@
if (TM.getRelocationModel() == Reloc::PIC_) {
if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
(Addr.getOpcode() == ISD::TargetJumpTable)){
- Base = CurDAG->getRegister(Mips::GP, MVT::i32);
+ Base = CurDAG->getRegister(Mips::GP, EVT::i32);
Offset = Addr;
return true;
}
@@ -169,19 +169,19 @@
// If the first operand is a FI, get the TargetFI Node
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
(Addr.getOperand(0))) {
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32);
} else {
Base = Addr.getOperand(0);
}
- Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
+ Offset = CurDAG->getTargetConstant(CN->getZExtValue(), EVT::i32);
return true;
}
}
}
Base = Addr;
- Offset = CurDAG->getTargetConstant(0, MVT::i32);
+ Offset = CurDAG->getTargetConstant(0, EVT::i32);
return true;
}
@@ -243,12 +243,12 @@
SDValue LHS = Node->getOperand(0);
SDValue RHS = Node->getOperand(1);
- MVT VT = LHS.getValueType();
+ EVT VT = LHS.getValueType();
SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, dl, VT, Ops, 2);
SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT,
SDValue(Carry,0), RHS);
- return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
+ return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, EVT::Flag,
LHS, SDValue(AddCarry,0));
}
@@ -266,13 +266,13 @@
else
Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
- SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32,
- MVT::Flag, InFlag);
+ SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32,
+ EVT::Flag, InFlag);
InFlag = SDValue(Lo,1);
- SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
+ SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag);
if (!N.getValue(0).use_empty())
ReplaceUses(N.getValue(0), SDValue(Lo,0));
@@ -292,14 +292,14 @@
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl,
- MVT::Flag, MulOp1, MulOp2);
+ EVT::Flag, MulOp1, MulOp2);
SDValue InFlag = SDValue(MulNode, 0);
if (MulOp == ISD::MUL)
- return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32, InFlag);
else
- return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag);
}
/// Div/Rem operations
@@ -318,10 +318,10 @@
Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
MOp = Mips::MFHI;
}
- SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag);
+ return CurDAG->getTargetNode(MOp, dl, EVT::i32, InFlag);
}
// Get target GOT address.
@@ -337,19 +337,19 @@
//bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
SDValue Chain = Node->getOperand(0);
SDValue Callee = Node->getOperand(1);
- SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
+ SDValue T9Reg = CurDAG->getRegister(Mips::T9, EVT::i32);
SDValue InFlag(0, 0);
if ( (isa<GlobalAddressSDNode>(Callee)) ||
(isa<ExternalSymbolSDNode>(Callee)) )
{
/// Direct call for global addresses and external symbols
- SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
+ SDValue GPReg = CurDAG->getRegister(Mips::GP, EVT::i32);
// Use load to get GOT target
SDValue Ops[] = { Callee, GPReg, Chain };
- SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32,
- MVT::Other, Ops, 3), 0);
+ SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, EVT::i32,
+ EVT::Other, Ops, 3), 0);
Chain = Load.getValue(1);
// Call target must be on T9
@@ -359,8 +359,8 @@
Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag);
// Emit Jump and Link Register
- SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other,
- MVT::Flag, T9Reg, Chain);
+ SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, EVT::Other,
+ EVT::Flag, T9Reg, Chain);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
ReplaceUses(SDValue(Node, 0), Chain);
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Aug 10 17:56:29 2009
@@ -65,108 +65,108 @@
setUsesGlobalOffsetTable(true);
// Set up the register classes
- addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
- addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
+ addRegisterClass(EVT::i32, Mips::CPURegsRegisterClass);
+ addRegisterClass(EVT::f32, Mips::FGR32RegisterClass);
// When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat())
if (!Subtarget->isFP64bit())
- addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
+ addRegisterClass(EVT::f64, Mips::AFGR64RegisterClass);
// Legal fp constants
addLegalFPImmediate(APFloat(+0.0f));
// Load extented operations for i1 types must be promoted
- setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
- setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote);
+ setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote);
// MIPS doesn't have extending float->double load/store
- setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
- setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand);
+ setTruncStoreAction(EVT::f64, EVT::f32, Expand);
// Used by legalize types to correctly generate the setcc result.
// Without this, every float setcc comes with a AND/OR with the result,
// we don't want this, since the fpcmp result goes to a flag register,
// which is used implicitly by brcond and select operations.
- AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
+ AddPromotedToType(ISD::SETCC, EVT::i1, EVT::i32);
// Mips Custom Operations
- setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
- setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
- setOperationAction(ISD::JumpTable, MVT::i32, Custom);
- setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
- setOperationAction(ISD::SELECT, MVT::f32, Custom);
- setOperationAction(ISD::SELECT, MVT::f64, Custom);
- setOperationAction(ISD::SELECT, MVT::i32, Custom);
- setOperationAction(ISD::SETCC, MVT::f32, Custom);
- setOperationAction(ISD::SETCC, MVT::f64, Custom);
- setOperationAction(ISD::BRCOND, MVT::Other, Custom);
- setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
- setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
+ setOperationAction(ISD::GlobalAddress, EVT::i32, Custom);
+ setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom);
+ setOperationAction(ISD::JumpTable, EVT::i32, Custom);
+ setOperationAction(ISD::ConstantPool, EVT::i32, Custom);
+ setOperationAction(ISD::SELECT, EVT::f32, Custom);
+ setOperationAction(ISD::SELECT, EVT::f64, Custom);
+ setOperationAction(ISD::SELECT, EVT::i32, Custom);
+ setOperationAction(ISD::SETCC, EVT::f32, Custom);
+ setOperationAction(ISD::SETCC, EVT::f64, Custom);
+ setOperationAction(ISD::BRCOND, EVT::Other, Custom);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom);
// We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
// with operands comming from setcc fp comparions. This is necessary since
// the result from these setcc are in a flag registers (FCR31).
- setOperationAction(ISD::AND, MVT::i32, Custom);
- setOperationAction(ISD::OR, MVT::i32, Custom);
+ setOperationAction(ISD::AND, EVT::i32, Custom);
+ setOperationAction(ISD::OR, EVT::i32, Custom);
// Operations not directly supported by Mips.
- setOperationAction(ISD::BR_JT, MVT::Other, Expand);
- setOperationAction(ISD::BR_CC, MVT::Other, Expand);
- setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
- setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
- setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- setOperationAction(ISD::CTPOP, MVT::i32, Expand);
- setOperationAction(ISD::CTTZ, MVT::i32, Expand);
- setOperationAction(ISD::ROTL, MVT::i32, Expand);
- setOperationAction(ISD::ROTR, MVT::i32, Expand);
- setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- setOperationAction(ISD::FSIN, MVT::f32, Expand);
- setOperationAction(ISD::FCOS, MVT::f32, Expand);
- setOperationAction(ISD::FPOWI, MVT::f32, Expand);
- setOperationAction(ISD::FPOW, MVT::f32, Expand);
- setOperationAction(ISD::FLOG, MVT::f32, Expand);
- setOperationAction(ISD::FLOG2, MVT::f32, Expand);
- setOperationAction(ISD::FLOG10, MVT::f32, Expand);
- setOperationAction(ISD::FEXP, MVT::f32, Expand);
+ setOperationAction(ISD::BR_JT, EVT::Other, Expand);
+ setOperationAction(ISD::BR_CC, EVT::Other, Expand);
+ setOperationAction(ISD::SELECT_CC, EVT::Other, Expand);
+ setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand);
+ setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand);
+ setOperationAction(ISD::CTPOP, EVT::i32, Expand);
+ setOperationAction(ISD::CTTZ, EVT::i32, Expand);
+ setOperationAction(ISD::ROTL, EVT::i32, Expand);
+ setOperationAction(ISD::ROTR, EVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand);
+ setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand);
+ setOperationAction(ISD::FSIN, EVT::f32, Expand);
+ setOperationAction(ISD::FCOS, EVT::f32, Expand);
+ setOperationAction(ISD::FPOWI, EVT::f32, Expand);
+ setOperationAction(ISD::FPOW, EVT::f32, Expand);
+ setOperationAction(ISD::FLOG, EVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, EVT::f32, Expand);
+ setOperationAction(ISD::FLOG10, EVT::f32, Expand);
+ setOperationAction(ISD::FEXP, EVT::f32, Expand);
// We don't have line number support yet.
- setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
- setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, EVT::Other, Expand);
// Use the default for now
- setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
- setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
- setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::STACKSAVE, EVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand);
+ setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand);
if (Subtarget->isSingleFloat())
- setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
+ setOperationAction(ISD::SELECT_CC, EVT::f64, Expand);
if (!Subtarget->hasSEInReg()) {
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand);
}
if (!Subtarget->hasBitCount())
- setOperationAction(ISD::CTLZ, MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ, EVT::i32, Expand);
if (!Subtarget->hasSwap())
- setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, EVT::i32, Expand);
setStackPointerRegisterToSaveRestore(Mips::SP);
computeRegisterProperties();
}
-MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(MVT VT) const {
- return MVT::i32;
+EVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
+ return EVT::i32;
}
/// getFunctionAlignment - Return the Log2 alignment of this function.
@@ -358,22 +358,22 @@
SDValue Src = Op.getOperand(0);
// Set the condition register
- SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
+ SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, EVT::i32);
CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
- CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
+ CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, EVT::i32);
- SDValue Cst = DAG.getConstant(3, MVT::i32);
- SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
- Cst = DAG.getConstant(2, MVT::i32);
- SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
+ SDValue Cst = DAG.getConstant(3, EVT::i32);
+ SDValue Or = DAG.getNode(ISD::OR, dl, EVT::i32, CondReg, Cst);
+ Cst = DAG.getConstant(2, EVT::i32);
+ SDValue Xor = DAG.getNode(ISD::XOR, dl, EVT::i32, Or, Cst);
SDValue InFlag(0, 0);
CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
// Emit the round instruction and bit convert to integer
- SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
+ SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, EVT::f32,
Src, CondReg.getValue(1));
- SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc);
+ SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Trunc);
return BitCvt;
}
@@ -385,11 +385,11 @@
DebugLoc dl = Op.getDebugLoc();
// Get a reference from Mips stack pointer
- SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
+ SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, EVT::i32);
// Subtract the dynamic size from the actual stack size to
// obtain the new stack size.
- SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
+ SDValue Sub = DAG.getNode(ISD::SUB, dl, EVT::i32, StackPointer, Size);
// The Sub result contains the new stack start address, so it
// must be placed in the stack pointer register.
@@ -411,15 +411,15 @@
if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
return Op;
- SDValue True = DAG.getConstant(1, MVT::i32);
- SDValue False = DAG.getConstant(0, MVT::i32);
+ SDValue True = DAG.getConstant(1, EVT::i32);
+ SDValue False = DAG.getConstant(0, EVT::i32);
SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
LHS, True, False, LHS.getOperand(2));
SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
RHS, True, False, RHS.getOperand(2));
- return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
+ return DAG.getNode(Op.getOpcode(), dl, EVT::i32, LSEL, RSEL);
}
SDValue MipsTargetLowering::
@@ -438,7 +438,7 @@
SDValue CCNode = CondRes.getOperand(2);
Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
- SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
+ SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), EVT::i32);
return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Dest, CondRes);
@@ -457,7 +457,7 @@
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
- DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
+ DAG.getConstant(FPCondCCodeToFCC(CC), EVT::i32));
}
SDValue MipsTargetLowering::
@@ -491,23 +491,23 @@
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
// %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, GA);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, GA);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
} else { // Abicall relocations, TODO: make this cleaner.
- SDValue ResNode = DAG.getLoad(MVT::i32, dl,
+ SDValue ResNode = DAG.getLoad(EVT::i32, dl,
DAG.getEntryNode(), GA, NULL, 0);
// On functions and global targets not internal linked only
// a load from got/GP is necessary for PIC to work.
if (!GV->hasLocalLinkage() || isa<Function>(GV))
return ResNode;
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
- return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, EVT::i32, ResNode, Lo);
}
llvm_unreachable("Dont know how to handle GlobalAddress");
@@ -529,19 +529,19 @@
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
- MVT PtrVT = Op.getValueType();
+ EVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
- SDVTList VTs = DAG.getVTList(MVT::i32);
+ SDVTList VTs = DAG.getVTList(EVT::i32);
SDValue Ops[] = { JTI };
HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1);
} else // Emit Load from Global Pointer
- HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
+ HiPart = DAG.getLoad(EVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
- ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, JTI);
+ ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
return ResNode;
}
@@ -552,7 +552,7 @@
SDValue ResNode;
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
- SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
+ SDValue CP = DAG.getTargetConstantPool(C, EVT::i32, N->getAlignment());
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
@@ -562,13 +562,13 @@
// hacking it. This feature should come soon so we can uncomment the
// stuff below.
//if (IsInSmallSection(C->getType())) {
- // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
- // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
- // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
+ // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, EVT::i32, CP);
+ // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(EVT::i32);
+ // ResNode = DAG.getNode(ISD::ADD, EVT::i32, GOT, GPRelNode);
//} else { // %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
- SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
- ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, CP);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, CP);
+ ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo);
//}
return ResNode;
@@ -593,8 +593,8 @@
// go to stack.
//===----------------------------------------------------------------------===//
-static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
+static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
static const unsigned IntRegsSize=4, FloatRegsSize=2;
@@ -614,8 +614,8 @@
bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
// Promote i8 and i16
- if (LocVT == MVT::i8 || LocVT == MVT::i16) {
- LocVT = MVT::i32;
+ if (LocVT == EVT::i8 || LocVT == EVT::i16) {
+ LocVT = EVT::i32;
if (ArgFlags.isSExt())
LocInfo = CCValAssign::SExt;
else if (ArgFlags.isZExt())
@@ -624,20 +624,20 @@
LocInfo = CCValAssign::AExt;
}
- if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
+ if (ValVT == EVT::i32 || (ValVT == EVT::f32 && IntRegUsed)) {
Reg = State.AllocateReg(IntRegs, IntRegsSize);
IntRegUsed = true;
- LocVT = MVT::i32;
+ LocVT = EVT::i32;
}
if (ValVT.isFloatingPoint() && !IntRegUsed) {
- if (ValVT == MVT::f32)
+ if (ValVT == EVT::f32)
Reg = State.AllocateReg(F32Regs, FloatRegsSize);
else
Reg = State.AllocateReg(F64Regs, FloatRegsSize);
}
- if (ValVT == MVT::f64 && IntRegUsed) {
+ if (ValVT == EVT::f64 && IntRegUsed) {
if (UnallocIntReg != IntRegsSize) {
// If we hit register A3 as the first not allocated, we must
// mark it as allocated (shadow) and use the stack instead.
@@ -646,7 +646,7 @@
for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
State.AllocateReg(UnallocIntReg);
}
- LocVT = MVT::i32;
+ LocVT = EVT::i32;
}
if (!Reg) {
@@ -686,7 +686,7 @@
// To meet O32 ABI, Mips must always allocate 16 bytes on
// the stack (even if less than 4 are used as arguments)
if (Subtarget->isABI_O32()) {
- int VTsize = MVT(MVT::i32).getSizeInBits()/8;
+ int VTsize = EVT(EVT::i32).getSizeInBits()/8;
MFI->CreateFixedObject(VTsize, (VTsize*3));
CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
} else
@@ -715,13 +715,13 @@
default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
if (Subtarget->isABI_O32() && VA.isRegLoc()) {
- if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg);
- if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
- Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
+ if (VA.getValVT() == EVT::f32 && VA.getLocVT() == EVT::i32)
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Arg);
+ if (VA.getValVT() == EVT::f64 && VA.getLocVT() == EVT::i32) {
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, Arg);
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg,
DAG.getConstant(0, getPointerTy()));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg,
DAG.getConstant(1, getPointerTy()));
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
@@ -768,7 +768,7 @@
// Transform all store nodes into one single node because all store
// nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -794,7 +794,7 @@
// = Chain, Callee, Reg#1, Reg#2, ...
//
// Returns a chain & a flag for retval copy to use.
- SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
@@ -838,9 +838,9 @@
// Reload GP value.
FI = MipsFI->getGPFI();
SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
- SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
+ SDValue GPLoad = DAG.getLoad(EVT::i32, dl, Chain, FIN, NULL, 0);
Chain = GPLoad.getValue(1);
- Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
+ Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, EVT::i32),
GPLoad, SDValue(0,0));
InFlag = Chain.getValue(1);
}
@@ -919,14 +919,14 @@
// Arguments stored on registers
if (VA.isRegLoc()) {
- MVT RegVT = VA.getLocVT();
+ EVT RegVT = VA.getLocVT();
TargetRegisterClass *RC = 0;
- if (RegVT == MVT::i32)
+ if (RegVT == EVT::i32)
RC = Mips::CPURegsRegisterClass;
- else if (RegVT == MVT::f32)
+ else if (RegVT == EVT::f32)
RC = Mips::FGR32RegisterClass;
- else if (RegVT == MVT::f64) {
+ else if (RegVT == EVT::f64) {
if (!Subtarget->isSingleFloat())
RC = Mips::AFGR64RegisterClass;
} else
@@ -954,15 +954,15 @@
// Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
if (Subtarget->isABI_O32()) {
- if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
- ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
- if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
+ if (RegVT == EVT::i32 && VA.getValVT() == EVT::f32)
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue);
+ if (RegVT == EVT::i32 && VA.getValVT() == EVT::f64) {
unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
VA.getLocReg()+1, RC);
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
- SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
- SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2);
- ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
+ SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue);
+ SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue2);
+ ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::f64, Lo, Hi);
}
}
@@ -1021,11 +1021,11 @@
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
unsigned Reg = MipsFI->getSRetReturnReg();
if (!Reg) {
- Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
+ Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i32));
MipsFI->setSRetReturnReg(Reg);
}
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Copy, Chain);
}
return Chain;
@@ -1094,11 +1094,11 @@
// Return on Mips is always a "jr $ra"
if (Flag.getNode())
- return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
- Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
+ return DAG.getNode(MipsISD::Ret, dl, EVT::Other,
+ Chain, DAG.getRegister(Mips::RA, EVT::i32), Flag);
else // Return Void
- return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
- Chain, DAG.getRegister(Mips::RA, MVT::i32));
+ return DAG.getNode(MipsISD::Ret, dl, EVT::Other,
+ Chain, DAG.getRegister(Mips::RA, EVT::i32));
}
//===----------------------------------------------------------------------===//
@@ -1135,16 +1135,16 @@
/// return a list of registers that can be used to satisfy the constraint.
/// This should only be used for C_RegisterClass constraints.
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
+getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
{
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
return std::make_pair(0U, Mips::CPURegsRegisterClass);
case 'f':
- if (VT == MVT::f32)
+ if (VT == EVT::f32)
return std::make_pair(0U, Mips::FGR32RegisterClass);
- if (VT == MVT::f64)
+ if (VT == EVT::f64)
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
return std::make_pair(0U, Mips::AFGR64RegisterClass);
}
@@ -1157,7 +1157,7 @@
/// pointer.
std::vector<unsigned> MipsTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const
+ EVT VT) const
{
if (Constraint.size() != 1)
return std::vector<unsigned>();
@@ -1174,7 +1174,7 @@
Mips::T8, 0);
case 'f':
- if (VT == MVT::f32) {
+ if (VT == EVT::f32) {
if (Subtarget->isSingleFloat())
return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
@@ -1187,7 +1187,7 @@
Mips::F28, Mips::F30, 0);
}
- if (VT == MVT::f64)
+ if (VT == EVT::f64)
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Mon Aug 10 17:56:29 2009
@@ -80,7 +80,7 @@
virtual const char *getTargetNodeName(unsigned Opcode) const;
/// getSetCCResultType - get the ISD::SETCC result ValueType
- MVT::SimpleValueType getSetCCResultType(MVT VT) const;
+ EVT::SimpleValueType getSetCCResultType(EVT VT) const;
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
@@ -137,11 +137,11 @@
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const;
+ EVT VT) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
};
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=78610&r1=78609&r2=78610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Aug 10 17:56:29 2009
@@ -96,7 +96,7 @@
// Node immediate fits as 16-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{
- if (N->getValueType(0) == MVT::i32)
+ if (N->getValueType(0) == EVT::i32)
return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
else
return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
@@ -107,7 +107,7 @@
// immediate are caught.
// e.g. addiu, sltiu
def immZExt16 : PatLeaf<(imm), [{
- if (N->getValueType(0) == MVT::i32)
+ if (N->getValueType(0) == EVT::i32)
return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
else
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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