[llvm-commits] [llvm] r78468 - in /llvm/trunk/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMISelDAGToDAG.cpp ARMInstrFormats.td ARMInstrInfo.td ARMInstrNEON.td
Bob Wilson
bob.wilson at apple.com
Sat Aug 8 21:35:57 PDT 2009
I don't know about the performance implications, but VLD1/VST1 will
store the values differently in memory than VLDM/VSTM. It depends on
the element size and endianness. As long as we're consistent, and the
spilled values never need to be interpreted by the debugger or any
other tool, maybe it doesn't matter.
I took a quick look to compare the performance implications a few
weeks ago, but I didn't hunt long enough to find anything very
informative. It would be good to know.... I'll dig around some more
later if no one else knows.
On Aug 8, 2009, at 6:52 PM, Evan Cheng wrote:
> Is it better than using VLD1 with alignment specification? Would that
> require dynamic stack re-alignment?
>
> Evan
>
> On Aug 8, 2009, at 6:35 AM, Anton Korobeynikov wrote:
>
>> Author: asl
>> Date: Sat Aug 8 08:35:48 2009
>> New Revision: 78468
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=78468&view=rev
>> Log:
>> Use VLDM / VSTM to spill/reload 128-bit Neon registers
>>
>> Modified:
>> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=78468&r1=78467&r2=78468&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Aug 8
>> 08:35:48 2009
>> @@ -655,11 +655,15 @@
>> AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
>> .addReg(SrcReg, getKillRegState(isKill))
>> .addFrameIndex(FI).addImm(0));
>> - } else {
>> - assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
>> + } else if (RC == ARM::SPRRegisterClass) {
>> AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
>> .addReg(SrcReg, getKillRegState(isKill))
>> .addFrameIndex(FI).addImm(0));
>> + } else {
>> + assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
>> + // FIXME: Neon instructions should support predicates
>> + BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg,
>> getKillRegState(isKill))
>> + .addFrameIndex(FI).addImm(0);
>> }
>> }
>>
>> @@ -676,10 +680,13 @@
>> } else if (RC == ARM::DPRRegisterClass || RC ==
>> ARM::DPR_VFP2RegisterClass) {
>> AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
>> .addFrameIndex(FI).addImm(0));
>> - } else {
>> - assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
>> + } else if (RC == ARM::SPRRegisterClass) {
>> AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
>> .addFrameIndex(FI).addImm(0));
>> + } else {
>> + assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
>> + // FIXME: Neon instructions should support predicates
>> + BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex
>> (FI).addImm(0);
>> }
>> }
>>
>> @@ -928,6 +935,8 @@
>> NumBits = 8;
>> break;
>> }
>> + case ARMII::AddrMode4:
>> + break;
>> case ARMII::AddrMode5: {
>> ImmIdx = FrameRegIdx+1;
>> InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm
>> ());
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=78468&r1=78467&r2=78468&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Sat Aug 8
>> 08:35:48 2009
>> @@ -78,6 +78,8 @@
>> SDValue &Offset, SDValue &Opc);
>> bool SelectAddrMode3Offset(SDValue Op, SDValue N,
>> SDValue &Offset, SDValue &Opc);
>> + bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
>> + SDValue &Mode);
>> bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
>> SDValue &Offset);
>> bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue
>> &Update,
>> @@ -383,6 +385,12 @@
>> return true;
>> }
>>
>> +bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
>> + SDValue &Addr, SDValue
>> &Mode) {
>> + Addr = N;
>> + Mode = CurDAG->getTargetConstant(0, MVT::i32);
>> + return true;
>> +}
>>
>> bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
>> SDValue &Base, SDValue
>> &Offset) {
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=78468&r1=78467&r2=78468&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Sat Aug 8 08:35:48
>> 2009
>> @@ -1199,6 +1199,10 @@
>> : NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, asm, "",
>> pattern> {
>> }
>>
>> +class NI4<dag oops, dag iops, InstrItinClass itin, string asm,
>> list<dag> pattern>
>> + : NeonI<oops, iops, AddrMode4, IndexModeNone, itin, asm, "",
>> pattern> {
>> +}
>> +
>> class NLdSt<dag oops, dag iops, InstrItinClass itin,
>> string asm, list<dag> pattern>
>> : NeonI<oops, iops, AddrMode6, IndexModeNone, itin, asm, "",
>> pattern> {
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=78468&r1=78467&r2=78468&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sat Aug 8 08:35:48
>> 2009
>> @@ -298,7 +298,7 @@
>> // addrmode4 := reg, <mode|W>
>> //
>> def addrmode4 : Operand<i32>,
>> - ComplexPattern<i32, 2, "", []> {
>> + ComplexPattern<i32, 2, "SelectAddrMode4", []> {
>> let PrintMethod = "printAddrMode4Operand";
>> let MIOperandInfo = (ops GPR, i32imm);
>> }
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78468&r1=78467&r2=78468&view=diff
>>
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =
>> =====================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Sat Aug 8 08:35:48
>> 2009
>> @@ -138,10 +138,10 @@
>> */
>>
>> // Use vldmia to load a Q register as a D register pair.
>> -def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
>> +def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
>> NoItinerary,
>> "vldmia $addr, ${dst:dregpair}",
>> - [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
>> + [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
>> let Inst{27-25} = 0b110;
>> let Inst{24} = 0; // P bit
>> let Inst{23} = 1; // U bit
>> @@ -150,10 +150,10 @@
>> }
>>
>> // Use vstmia to store a Q register as a D register pair.
>> -def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
>> +def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
>> NoItinerary,
>> "vstmia $addr, ${src:dregpair}",
>> - [(store (v2f64 QPR:$src), GPR:$addr)]> {
>> + [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
>> let Inst{27-25} = 0b110;
>> let Inst{24} = 0; // P bit
>> let Inst{23} = 1; // U bit
>> @@ -161,7 +161,6 @@
>> let Inst{11-9} = 0b101;
>> }
>>
>> -
>> // VLD1 : Vector Load (multiple single elements)
>> class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
>> : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
>>
>>
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