[llvm-commits] [llvm] r78514 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrNEON.td ARMInstrThumb.td ARMInstrThumb2.td AsmPrinter/ARMAsmPrinter.cpp
Anton Korobeynikov
asl at math.spbu.ru
Sat Aug 8 16:10:41 PDT 2009
Author: asl
Date: Sat Aug 8 18:10:41 2009
New Revision: 78514
URL: http://llvm.org/viewvc/llvm-project?rev=78514&view=rev
Log:
Use subclassing to print lane-like immediates (w/o hash) eliminating
'no_hash' modifier. Hopefully this will make Daniel happy :)
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=78514&r1=78513&r2=78514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sat Aug 8 18:10:41 2009
@@ -327,6 +327,10 @@
let MIOperandInfo = (ops GPR, i32imm);
}
+def lane_cst : Operand<i32> {
+ let PrintMethod = "printLaneOperand";
+}
+
//===----------------------------------------------------------------------===//
include "ARMInstrFormats.td"
@@ -577,10 +581,10 @@
[]>;
def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
- (ins i32imm:$label, i32imm:$id, pred:$p),
+ (ins i32imm:$label, lane_cst:$id, pred:$p),
Pseudo, IIC_iLoad,
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
- "(${label}_${id:no_hash}-(",
+ "(${label}_${id}-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #${:private}PCRELV${:uid}")),
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=78514&r1=78513&r2=78514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Sat Aug 8 18:10:41 2009
@@ -1618,28 +1618,28 @@
// VMOV : Vector Get Lane (move scalar to ARM core register)
def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
- NoItinerary, "vmov", ".s8\t$dst, $src[${lane:no_hash}]",
+ (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
- (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
- NoItinerary, "vmov", ".s16\t$dst, $src[${lane:no_hash}]",
+ (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
- NoItinerary, "vmov", ".u8\t$dst, $src[${lane:no_hash}]",
+ (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
imm:$lane))]>;
def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
- (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
- NoItinerary, "vmov", ".u16\t$dst, $src[${lane:no_hash}]",
+ (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
[(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
imm:$lane))]>;
def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
- NoItinerary, "vmov", ".32\t$dst, $src[${lane:no_hash}]",
+ (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
+ NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
[(set GPR:$dst, (extractelt (v2i32 DPR:$src),
imm:$lane))]>;
// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
@@ -1675,18 +1675,18 @@
let Constraints = "$src1 = $dst" in {
def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, i32imm:$lane),
- NoItinerary, "vmov", ".8\t$dst[${lane:no_hash}], $src2",
+ (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, i32imm:$lane),
- NoItinerary, "vmov", ".16\t$dst[${lane:no_hash}], $src2",
+ (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
[(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
GPR:$src2, imm:$lane))]>;
def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, i32imm:$lane),
- NoItinerary, "vmov", ".32\t$dst[${lane:no_hash}], $src2",
+ (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
+ NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
[(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
GPR:$src2, imm:$lane))]>;
}
@@ -1769,8 +1769,8 @@
class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
- (outs DPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
- !strconcat(OpcodeStr, "\t$dst, $src[${lane:no_hash}]"), "",
+ (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
+ !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
// vector_shuffle requires that the source and destination types match, so
@@ -1778,8 +1778,8 @@
class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
ValueType ResTy, ValueType OpTy>
: N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
- (outs QPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
- !strconcat(OpcodeStr, "\t$dst, $src[${lane:no_hash}]"), "",
+ (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
+ !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
[(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=78514&r1=78513&r2=78514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Sat Aug 8 18:10:41 2009
@@ -614,8 +614,8 @@
def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
"adr $dst, #$label", []>;
-def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id), IIC_iALU,
- "adr $dst, #${label}_${id:no_hash}", []>;
+def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, lane_cst:$id), IIC_iALU,
+ "adr $dst, #${label}_${id}", []>;
//===----------------------------------------------------------------------===//
// TLS Instructions
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=78514&r1=78513&r2=78514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sat Aug 8 18:10:41 2009
@@ -429,8 +429,8 @@
"adr$p.w $dst, #$label", []>;
def t2LEApcrelJT : T2XI<(outs GPR:$dst),
- (ins i32imm:$label, i32imm:$id, pred:$p), IIC_iALU,
- "adr$p.w $dst, #${label}_${id:no_hash}", []>;
+ (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALU,
+ "adr$p.w $dst, #${label}_${id}", []>;
// ADD r, sp, {so_imm|i12}
Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=78514&r1=78513&r2=78514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Sat Aug 8 18:10:41 2009
@@ -162,6 +162,7 @@
void printJTBlockOperand(const MachineInstr *MI, int OpNum);
void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
void printTBAddrMode(const MachineInstr *MI, int OpNum);
+ void printLaneOperand(const MachineInstr *MI, int OpNum);
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode);
@@ -358,10 +359,7 @@
break;
}
case MachineOperand::MO_Immediate: {
- if (!Modifier || strcmp(Modifier, "no_hash") != 0)
- O << '#';
-
- O << MO.getImm();
+ O << '#' << MO.getImm();
break;
}
case MachineOperand::MO_MachineBasicBlock:
@@ -1011,13 +1009,16 @@
O << ']';
}
+void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) {
+ O << MI->getOperand(OpNum).getImm();
+}
bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode){
// Does this asm operand have a single letter operand modifier?
if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
+
switch (ExtraCode[0]) {
default: return true; // Unknown modifier.
case 'a': // Print as a memory address.
@@ -1027,7 +1028,7 @@
}
// Fallthrough
case 'c': // Don't print "#" before an immediate operand.
- printOperand(MI, OpNum, "no_hash");
+ printLaneOperand(MI, OpNum);
return false;
case 'P': // Print a VFP double precision register.
printOperand(MI, OpNum);
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