[llvm-commits] [llvm] r78419 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp test/CodeGen/ARM/vdup.ll

[Bob Wilson]

On Aug 7, 2009, at 4:10 PM, Anton Korobeynikov wrote:

> Bob,
>
>> I don't understand why you can't do this with the existing splat_lane
>> pattern.  It would be good to match the (scalar_to_vector SPR)
>> independently as a subreg access.
>>  Once you've got that, it seems like
>> it ought to be possible to legalize it to use the splat_lane shuffle.
>> Am I missing something here?
> We need to translate the SPR register into DPR register + lane. The
> register number is not known until regalloc, that's why we cannot use
> the existing pattern (we just don't know the resulting lane).
> Translating (scalar_to_vector SPR) into insert_subreg is also not so
> good idea since we need to insert into pre-specified location and this
> might be not a no-op.

Ah ha!  That's what I was missing (the part about not knowing the lane  
number until after reg alloc).  Thanks for explaining.


>
> In any case all current matching code is pretty fragile. As Chris
> mentioned - it needs to be redone during lowering phase. Then
> everything will be much clear and such 'specialized' pattern will just
> go away.

Yes, I'm appreciating having some help on this stuff.