[llvm-commits] [llvm] r78217 - in /llvm/trunk: lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86RegisterInfo.cpp test/CodeGen/X86/coalesce-esp.ll test/CodeGen/X86/ins_subreg_coalesce-3.ll test/CodeGen/X86/stack-color-with-reg.ll
Dan Gohman
gohman at apple.com
Wed Aug 5 10:40:27 PDT 2009
Author: djg
Date: Wed Aug 5 12:40:24 2009
New Revision: 78217
URL: http://llvm.org/viewvc/llvm-project?rev=78217&view=rev
Log:
Enable the new no-SP register classes by default. This is to address
PR4572. A few tests have some minor code regressions due to different
coalescing.
Modified:
llvm/trunk/lib/Target/X86/X86Instr64bit.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/test/CodeGen/X86/coalesce-esp.ll
llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-3.ll
llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll
Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=78217&r1=78216&r2=78217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Aug 5 12:40:24 2009
@@ -32,13 +32,13 @@
def lea64mem : Operand<i64> {
let PrintMethod = "printlea64mem";
- let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
+ let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
}
def lea64_32mem : Operand<i32> {
let PrintMethod = "printlea64_32mem";
let AsmOperandLowerMethod = "lower_lea64_32mem";
- let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+ let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=78217&r1=78216&r2=78217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Aug 5 12:40:24 2009
@@ -196,7 +196,7 @@
def lea32mem : Operand<i32> {
let PrintMethod = "printlea32mem";
- let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+ let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
}
def SSECC : Operand<i8> {
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=78217&r1=78216&r2=78217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Aug 5 12:40:24 2009
@@ -42,11 +42,6 @@
#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
-static cl::opt<bool>
-StrictIndexRegclass("strict-index-regclass",
- cl::desc("Use a special register class to avoid letting SP "
- "be used as an index"));
-
X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
const TargetInstrInfo &tii)
: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
@@ -274,15 +269,9 @@
return &X86::GR64RegClass;
return &X86::GR32RegClass;
case 1: // Normal GRPs except the stack pointer (for encoding reasons).
- if (!StrictIndexRegclass) {
- if (TM.getSubtarget<X86Subtarget>().is64Bit())
- return &X86::GR64RegClass;
- return &X86::GR32RegClass;
- } else {
- if (TM.getSubtarget<X86Subtarget>().is64Bit())
- return &X86::GR64_NOSPRegClass;
- return &X86::GR32_NOSPRegClass;
- }
+ if (TM.getSubtarget<X86Subtarget>().is64Bit())
+ return &X86::GR64_NOSPRegClass;
+ return &X86::GR32_NOSPRegClass;
}
}
Modified: llvm/trunk/test/CodeGen/X86/coalesce-esp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalesce-esp.ll?rev=78217&r1=78216&r2=78217&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/coalesce-esp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/coalesce-esp.ll Wed Aug 5 12:40:24 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -strict-index-regclass | grep {movl %esp, %eax}
+; RUN: llvm-as < %s | llc | grep {movl %esp, %eax}
; PR4572
; Don't coalesce with %esp if it would end up putting %esp in
Modified: llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-3.ll?rev=78217&r1=78216&r2=78217&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ins_subreg_coalesce-3.ll Wed Aug 5 12:40:24 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 10
+; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 11
%struct.COMPOSITE = type { i8, i16, i16 }
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
Modified: llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll?rev=78217&r1=78216&r2=78217&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/stack-color-with-reg.ll Wed Aug 5 12:40:24 2009
@@ -1,7 +1,7 @@
; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
; RUN: grep stackcoloring %t | grep "loads eliminated"
; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5
-; RUN: grep asm-printer %t | grep 180
+; RUN: grep asm-printer %t | grep 182
type { [62 x %struct.Bitvec*] } ; type %0
type { i8* } ; type %1
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