[llvm-commits] [llvm] r77740 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/2009-04-17-tls-fast.ll test/CodeGen/X86/tls1-pic.ll test/CodeGen/X86/tls2-pic.ll test/CodeGen/X86/tls3-pic.ll test/CodeGen/X86/tls4-pic.ll utils/TableGen/AsmWriterEmitter.cpp

[David Greene]

Jakob Stoklund Olesen wrote:

> As I am reading David's patch, there must be a tab in the instruction  
> definition before a tab is emitted. From X86InstrInfo.td:
> 
> def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
>                  "mov{l}\t{$src, $dst|$dst, $src}", []>;
> 
> There is only one tab. It should be changed to:
> 
> def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
>                  "mov{l}\t{$src,\t$dst|$dst,\t$src}", []>;

Correct.  And some parameters also need to get set to non-zero in
X86TargetAsmInfo.

> Let me just point out that not all assembler syntax fits the mnemonic 
> +operands syntax. These are some random blackfin assembler instructions:
> 
> p3 = (p3+p2)<<2 ;
> r3.h = ashift r0.l by r7.l ;
> prefetch [ p0 ++ ] ;
> (r1, r0) = search r2 (LT) || r2 = [p0++];
> a1=r7.h*r4.h (m), a0+=r7.l*r4.l (fu) ;
> r1=pack(r1.h,r0.h) || [i0++]=r0 || r2.l=w[i2++] ;
> 
> Yes, that is one instruction per line. As you can see, it would be bad  
> to insert any tabs in that syntax. It is important that targets can  
> "opt out" of any imposed formatting.

Absolutely.  I've very aware that not all ISAs have this syntax.
Traditionally, Cray Asm (derived from CDC Asm) looks like expressions
and statements, somewhat like your blackfin example. That's why the
padding only happens if tabs are in the string AND the padding
parameters are nonzero in [Arch]TargetAsmInfo.

In your case, though, I would argue that tabs could be inserted before
'=' and you'd get a nice formatting.  Then for things like "prefetch"
you could put a tab after the mnemonic.

                              -Dave