[llvm-commits] [llvm] r77584 - /llvm/trunk/lib/Target/X86/README.txt

[Evan Cheng]

On Jul 30, 2009, at 2:10 PM, Chris Lattner wrote:

>
> On Jul 30, 2009, at 10:36 AM, Evan Cheng wrote:
>
>>>> information
>>>> +carried over to machine instructions. Asm printer (or JIT) can use
>>>> this
>>>> +information to add the "lock" prefix.
>>>
>>> Maybe just make "lock" be an operand that can be 0/1, like the
>>> predicate bit on arm?
>>>
>>
>> That's possible but currently we don't have a way to toggling it
>> during isel.
>
> isel would just select it with the bit set to 0 in the "add" case, and
> bit set to 1 in the custom lowered case, isn't that enough?

I am not sure what you mean. TableGen generated code has to know to  
toggle the bit based on the input pattern. This is done at isel time.  
Currently the way predicate operand works is the later pass would  
modify the node.

Evan

>
> -Chris
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