[llvm-commits] [llvm] r77622 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/Thumb2/pic-load.ll

Thu Jul 30 15:33:35 PDT 2009

On Jul 30, 2009, at 2:35 PM, David Goodwin wrote:

> That is true. I thought that there might be a context where only one
> address mode would be available for matching, but perhaps that can't
> happen. I can remove the code in imm8 if you like. But it probably
> doesn't matter because frame index elimination recognizes both address
> modes and will switch the opcode as necessary to match the immediate.

Yes, please do. Thanks.

Evan

>
> David
>
> On Jul 30, 2009, at 1:33 PM, Evan Cheng wrote:
>
>> Hi David,
>>
>> Given your change, then it's possible both [R + imm12] and [R - imm8]
>> can match a frameindex address. Is that what we want? Don't we want  
>> to
>> canonicalize on one?
>>
>> Evan
>>
>> On Jul 30, 2009, at 11:56 AM, David Goodwin wrote:
>>
>>> Author: david_goodwin
>>> Date: Thu Jul 30 13:56:48 2009
>>> New Revision: 77622
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=77622&view=rev
>>> Log:
>>> Cleanup and include code selection for some frame index cases.
>>>
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>>  llvm/trunk/test/CodeGen/Thumb2/pic-load.ll
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=77622&r1=77621&r2=77622&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Jul 30
>>> 13:56:48 2009
>>> @@ -598,7 +598,7 @@
>>> // Match simple R + imm12 operands.
>>>
>>> // Match frame index...
>>> -  if (N.getOpcode() != ISD::ADD) {
>>> +  if ((N.getOpcode() != ISD::ADD) && (N.getOpcode() != ISD::SUB)) {
>>>   if (N.getOpcode() == ISD::FrameIndex) {
>>>     int FI = cast<FrameIndexSDNode>(N)->getIndex();
>>>     Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
>>> @@ -610,8 +610,15 @@
>>>
>>> if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand
>>> (1))) {
>>>   int RHSC = (int)RHS->getZExtValue();
>>> -    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
>>> +    if (N.getOpcode() == ISD::SUB)
>>> +      RHSC = -RHSC;
>>> +
>>> +    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
>>>     Base   = N.getOperand(0);
>>> +      if (Base.getOpcode() == ISD::FrameIndex) {
>>> +        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
>>> +        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
>>> +      }
>>>     OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
>>>     return true;
>>>   }
>>> @@ -622,20 +629,31 @@
>>>
>>> bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
>>>                                          SDValue &Base, SDValue
>>> &OffImm) {
>>> -  if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
>>> -    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand
>>> (1))) {
>>> -      int RHSC = (int)RHS->getSExtValue();
>>> -      if (N.getOpcode() == ISD::SUB)
>>> -        RHSC = -RHSC;
>>> +  // Match simple R - imm8 operands.
>>>
>>> -      if ((RHSC >= -255) && (RHSC <= 0)) { // 8 bits (always
>>> negative)
>>> -        Base   = N.getOperand(0);
>>> -        OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
>>> -        return true;
>>> +  // Match frame index...
>>> +  if ((N.getOpcode() != ISD::ADD) && (N.getOpcode() != ISD::SUB)) {
>>> +    if (N.getOpcode() == ISD::FrameIndex) {
>>> +      int FI = cast<FrameIndexSDNode>(N)->getIndex();
>>> +      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
>>> +      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
>>> +      return true;
>>> +    }
>>> +    return false;
>>> +  }
>>> +
>>> +  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand
>>> (1))) {
>>> +    int RHSC = (int)RHS->getSExtValue();
>>> +    if (N.getOpcode() == ISD::SUB)
>>> +      RHSC = -RHSC;
>>> +
>>> +    if ((RHSC >= -255) && (RHSC <= 0)) { // 8 bits (always  
>>> negative)
>>> +      Base   = N.getOperand(0);
>>> +      if (Base.getOpcode() == ISD::FrameIndex) {
>>> +        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
>>> +        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
>>>     }
>>> -    } else if (N.getOpcode() == ISD::SUB) {
>>> -      Base   = N;
>>> -      OffImm = CurDAG->getTargetConstant(0, MVT::i32);
>>> +      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
>>>     return true;
>>>   }
>>> }
>>> @@ -706,9 +724,24 @@
>>>   return true;
>>> }
>>>
>>> +  // Leave (R +/- imm) for other address modes... unless they can't
>>> +  // handle them
>>> +  if (dyn_cast<ConstantSDNode>(N.getOperand(1)) != NULL) {
>>> +    SDValue OffImm;
>>> +    if (SelectT2AddrModeImm12(Op, N, Base, OffImm) ||
>>> +        SelectT2AddrModeImm8 (Op, N, Base, OffImm))
>>> +      return false;
>>> +  }
>>> +
>>> // Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
>>> -  if (N.getOpcode() != ISD::ADD)
>>> -    return false;
>>> +  if (N.getOpcode() == ISD::SUB) {
>>> +    Base = N;
>>> +    OffReg = CurDAG->getRegister(0, MVT::i32);
>>> +    ShImm  = CurDAG->getTargetConstant(0, MVT::i32);
>>> +    return true;
>>> +  }
>>> +
>>> +  assert(N.getOpcode() == ISD::ADD);
>>>
>>> // Look for (R + R) or (R + (R << [1,2,3])).
>>> unsigned ShAmt = 0;
>>> @@ -736,10 +769,6 @@
>>>   } else {
>>>     ShOpcVal = ARM_AM::no_shift;
>>>   }
>>> -  } else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
>>> -             SelectT2AddrModeImm8 (Op, N, Base, ShImm)) {
>>> -    // Don't match if it's possible to match to one of the r +/-
>>> imm cases.
>>> -    return false;
>>> }
>>>
>>> ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
>>>
>>> Modified: llvm/trunk/test/CodeGen/Thumb2/pic-load.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/pic-load.ll?rev=77622&r1=77621&r2=77622&view=diff
>>>
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> =
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/test/CodeGen/Thumb2/pic-load.ll (original)
>>> +++ llvm/trunk/test/CodeGen/Thumb2/pic-load.ll Thu Jul 30 13:56:48
>>> 2009
>>> @@ -8,7 +8,7 @@
>>> define hidden arm_apcscc i32 @atexit(void ()* %func) nounwind {
>>> entry:
>>> ; CHECK: atexit:
>>> -; CHECK: add.w r1, r1, pc
>>> +; CHECK: add.w r0, r0, pc
>>> 	%r = alloca %struct.one_atexit_routine, align 4		; <
>>> %struct.one_atexit_routine*> [#uses=3]
>>> 	%0 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 0,
>>> i32 0		; <void ()**> [#uses=1]
>>> 	store void ()* %func, void ()** %0, align 4
>>>
>>>
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