[llvm-commits] [llvm] r77305 - in /llvm/trunk: lib/Target/ARM/Thumb1RegisterInfo.cpp test/CodeGen/Thumb/2009-07-27-PEIAssert.ll

[Evan Cheng]

Author: evancheng
Date: Tue Jul 28 02:38:35 2009
New Revision: 77305

URL: http://llvm.org/viewvc/llvm-project?rev=77305&view=rev
Log:
tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.

Added:
    llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll
Modified:
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=77305&r1=77304&r2=77305&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Tue Jul 28 02:38:35 2009
@@ -505,9 +505,14 @@
       // r0 = -imm (this is then translated into a series of instructons)
       // r0 = add r0, sp
       emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
+
       MI.setDesc(TII.get(ARM::tADDhirr));
       MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
       MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
+      if (Opcode == ARM::tADDi3) {
+        MachineInstrBuilder MIB(&MI);
+        AddDefaultPred(MIB);
+      }
     }
     return;
   } else {

Added: llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll?rev=77305&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll Tue Jul 28 02:38:35 2009
@@ -0,0 +1,26 @@
+; RUN: llvm-as < %s | llc -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim
+
+	%struct.LinkList = type { i32, %struct.LinkList* }
+	%struct.List = type { i32, i32* }
+ at llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @main to i8*)], section "llvm.metadata"		; <[1 x i8*]*> [#uses=0]
+
+define arm_apcscc i32 @main() nounwind {
+entry:
+	%ll = alloca %struct.LinkList*, align 4		; <%struct.LinkList**> [#uses=1]
+	%0 = call arm_apcscc  i32 @ReadList(%struct.LinkList** %ll, %struct.List** null) nounwind		; <i32> [#uses=1]
+	switch i32 %0, label %bb5 [
+		i32 7, label %bb4
+		i32 42, label %bb3
+	]
+
+bb3:		; preds = %entry
+	ret i32 1
+
+bb4:		; preds = %entry
+	ret i32 0
+
+bb5:		; preds = %entry
+	ret i32 1
+}
+
+declare arm_apcscc i32 @ReadList(%struct.LinkList** nocapture, %struct.List** nocapture) nounwind