[llvm-commits] [llvm-gcc-4.2] r76781 [4/5] - in /llvm-gcc-4.2/trunk: ./ gcc/ gcc/config/ gcc/config/arm/ gcc/config/rs6000/ gcc/cp/ gcc/doc/ gcc/testsuite/g++.apple/ gcc/testsuite/g++.dg/abi/ gcc/testsuite/gcc.apple/ gcc/testsuite/gcc.target/arm/ gcc/testsuite/gcc.target/arm/neon/ gcc/testsuite/obj-c++.dg/ gcc/testsuite/objc.dg/
Bob Wilson
bob.wilson at apple.com
Wed Jul 22 13:36:46 PDT 2009
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhadds8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhadds8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhadds8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhadds8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhadds8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhaddu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhaddu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhaddu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vhsubu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dupf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupf32 (void)
+{
+ float32x4_t out_float32x4_t;
+
+ out_float32x4_t = vld1q_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dupp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp16 (void)
+{
+ poly16x8_t out_poly16x8_t;
+
+ out_poly16x8_t = vld1q_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dupp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+
+ out_poly8x16_t = vld1q_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dups16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups16 (void)
+{
+ int16x8_t out_int16x8_t;
+
+ out_int16x8_t = vld1q_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dups32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups32 (void)
+{
+ int32x4_t out_int32x4_t;
+
+ out_int32x4_t = vld1q_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dups64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups64 (void)
+{
+ int64x2_t out_int64x2_t;
+
+ out_int64x2_t = vld1q_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dups8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups8 (void)
+{
+ int8x16_t out_int8x16_t;
+
+ out_int8x16_t = vld1q_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dupu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+
+ out_uint16x8_t = vld1q_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dupu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+
+ out_uint32x4_t = vld1q_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dupu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+
+ out_uint64x2_t = vld1q_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_dupu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+
+ out_uint8x16_t = vld1q_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanef32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+
+ out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep16 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ poly16x8_t arg1_poly16x8_t;
+
+ out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_lanep8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ poly8x16_t arg1_poly8x16_t;
+
+ out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_lanes64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_lanes8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_laneu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg1_uint64x2_t;
+
+ out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Q_laneu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qf32 (void)
+{
+ float32x4_t out_float32x4_t;
+
+ out_float32x4_t = vld1q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp16 (void)
+{
+ poly16x8_t out_poly16x8_t;
+
+ out_poly16x8_t = vld1q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+
+ out_poly8x16_t = vld1q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs16 (void)
+{
+ int16x8_t out_int16x8_t;
+
+ out_int16x8_t = vld1q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs32 (void)
+{
+ int32x4_t out_int32x4_t;
+
+ out_int32x4_t = vld1q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs64 (void)
+{
+ int64x2_t out_int64x2_t;
+
+ out_int64x2_t = vld1q_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs8 (void)
+{
+ int8x16_t out_int8x16_t;
+
+ out_int8x16_t = vld1q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+
+ out_uint16x8_t = vld1q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+
+ out_uint32x4_t = vld1q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+
+ out_uint64x2_t = vld1q_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1Qu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+
+ out_uint8x16_t = vld1q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dupf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupf32 (void)
+{
+ float32x2_t out_float32x2_t;
+
+ out_float32x2_t = vld1_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dupp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp16 (void)
+{
+ poly16x4_t out_poly16x4_t;
+
+ out_poly16x4_t = vld1_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dupp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+
+ out_poly8x8_t = vld1_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dups16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups16 (void)
+{
+ int16x4_t out_int16x4_t;
+
+ out_int16x4_t = vld1_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dups32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups32 (void)
+{
+ int32x2_t out_int32x2_t;
+
+ out_int32x2_t = vld1_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dups64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups64 (void)
+{
+ int64x1_t out_int64x1_t;
+
+ out_int64x1_t = vld1_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dups8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups8 (void)
+{
+ int8x8_t out_int8x8_t;
+
+ out_int8x8_t = vld1_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dupu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+
+ out_uint16x4_t = vld1_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dupu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+
+ out_uint32x2_t = vld1_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dupu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+
+ out_uint64x1_t = vld1_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_dupu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+
+ out_uint8x8_t = vld1_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanef32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep16 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ poly16x4_t arg1_poly16x4_t;
+
+ out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_lanep8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ poly8x8_t arg1_poly8x8_t;
+
+ out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_lanes64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_lanes8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_laneu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg1_uint64x1_t;
+
+ out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1_laneu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1f32 (void)
+{
+ float32x2_t out_float32x2_t;
+
+ out_float32x2_t = vld1_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1p16 (void)
+{
+ poly16x4_t out_poly16x4_t;
+
+ out_poly16x4_t = vld1_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1p8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+
+ out_poly8x8_t = vld1_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s16 (void)
+{
+ int16x4_t out_int16x4_t;
+
+ out_int16x4_t = vld1_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s32 (void)
+{
+ int32x2_t out_int32x2_t;
+
+ out_int32x2_t = vld1_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s64 (void)
+{
+ int64x1_t out_int64x1_t;
+
+ out_int64x1_t = vld1_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s8 (void)
+{
+ int8x8_t out_int8x8_t;
+
+ out_int8x8_t = vld1_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+
+ out_uint16x4_t = vld1_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+
+ out_uint32x2_t = vld1_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+
+ out_uint64x1_t = vld1_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld1u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld1u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+
+ out_uint8x8_t = vld1_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Q_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanef32 (void)
+{
+ float32x4x2_t out_float32x4x2_t;
+ float32x4x2_t arg1_float32x4x2_t;
+
+ out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Q_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanep16 (void)
+{
+ poly16x8x2_t out_poly16x8x2_t;
+ poly16x8x2_t arg1_poly16x8x2_t;
+
+ out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Q_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes16 (void)
+{
+ int16x8x2_t out_int16x8x2_t;
+ int16x8x2_t arg1_int16x8x2_t;
+
+ out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Q_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes32 (void)
+{
+ int32x4x2_t out_int32x4x2_t;
+ int32x4x2_t arg1_int32x4x2_t;
+
+ out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Q_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu16 (void)
+{
+ uint16x8x2_t out_uint16x8x2_t;
+ uint16x8x2_t arg1_uint16x8x2_t;
+
+ out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Q_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu32 (void)
+{
+ uint32x4x2_t out_uint32x4x2_t;
+ uint32x4x2_t arg1_uint32x4x2_t;
+
+ out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qf32 (void)
+{
+ float32x4x2_t out_float32x4x2_t;
+
+ out_float32x4x2_t = vld2q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp16 (void)
+{
+ poly16x8x2_t out_poly16x8x2_t;
+
+ out_poly16x8x2_t = vld2q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp8 (void)
+{
+ poly8x16x2_t out_poly8x16x2_t;
+
+ out_poly8x16x2_t = vld2q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs16 (void)
+{
+ int16x8x2_t out_int16x8x2_t;
+
+ out_int16x8x2_t = vld2q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs32 (void)
+{
+ int32x4x2_t out_int32x4x2_t;
+
+ out_int32x4x2_t = vld2q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs8 (void)
+{
+ int8x16x2_t out_int8x16x2_t;
+
+ out_int8x16x2_t = vld2q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu16 (void)
+{
+ uint16x8x2_t out_uint16x8x2_t;
+
+ out_uint16x8x2_t = vld2q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu32 (void)
+{
+ uint32x4x2_t out_uint32x4x2_t;
+
+ out_uint32x4x2_t = vld2q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2Qu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu8 (void)
+{
+ uint8x16x2_t out_uint8x16x2_t;
+
+ out_uint8x16x2_t = vld2q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dupf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupf32 (void)
+{
+ float32x2x2_t out_float32x2x2_t;
+
+ out_float32x2x2_t = vld2_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dupp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp16 (void)
+{
+ poly16x4x2_t out_poly16x4x2_t;
+
+ out_poly16x4x2_t = vld2_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dupp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp8 (void)
+{
+ poly8x8x2_t out_poly8x8x2_t;
+
+ out_poly8x8x2_t = vld2_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dups16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups16 (void)
+{
+ int16x4x2_t out_int16x4x2_t;
+
+ out_int16x4x2_t = vld2_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dups32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups32 (void)
+{
+ int32x2x2_t out_int32x2x2_t;
+
+ out_int32x2x2_t = vld2_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dups64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups64 (void)
+{
+ int64x1x2_t out_int64x1x2_t;
+
+ out_int64x1x2_t = vld2_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dups8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups8 (void)
+{
+ int8x8x2_t out_int8x8x2_t;
+
+ out_int8x8x2_t = vld2_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dupu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu16 (void)
+{
+ uint16x4x2_t out_uint16x4x2_t;
+
+ out_uint16x4x2_t = vld2_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dupu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu32 (void)
+{
+ uint32x2x2_t out_uint32x2x2_t;
+
+ out_uint32x2x2_t = vld2_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dupu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu64 (void)
+{
+ uint64x1x2_t out_uint64x1x2_t;
+
+ out_uint64x1x2_t = vld2_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_dupu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu8 (void)
+{
+ uint8x8x2_t out_uint8x8x2_t;
+
+ out_uint8x8x2_t = vld2_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanef32 (void)
+{
+ float32x2x2_t out_float32x2x2_t;
+ float32x2x2_t arg1_float32x2x2_t;
+
+ out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep16 (void)
+{
+ poly16x4x2_t out_poly16x4x2_t;
+ poly16x4x2_t arg1_poly16x4x2_t;
+
+ out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_lanep8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep8 (void)
+{
+ poly8x8x2_t out_poly8x8x2_t;
+ poly8x8x2_t arg1_poly8x8x2_t;
+
+ out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes16 (void)
+{
+ int16x4x2_t out_int16x4x2_t;
+ int16x4x2_t arg1_int16x4x2_t;
+
+ out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes32 (void)
+{
+ int32x2x2_t out_int32x2x2_t;
+ int32x2x2_t arg1_int32x2x2_t;
+
+ out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_lanes8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes8 (void)
+{
+ int8x8x2_t out_int8x8x2_t;
+ int8x8x2_t arg1_int8x8x2_t;
+
+ out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu16 (void)
+{
+ uint16x4x2_t out_uint16x4x2_t;
+ uint16x4x2_t arg1_uint16x4x2_t;
+
+ out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu32 (void)
+{
+ uint32x2x2_t out_uint32x2x2_t;
+ uint32x2x2_t arg1_uint32x2x2_t;
+
+ out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2_laneu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu8 (void)
+{
+ uint8x8x2_t out_uint8x8x2_t;
+ uint8x8x2_t arg1_uint8x8x2_t;
+
+ out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2f32 (void)
+{
+ float32x2x2_t out_float32x2x2_t;
+
+ out_float32x2x2_t = vld2_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2p16 (void)
+{
+ poly16x4x2_t out_poly16x4x2_t;
+
+ out_poly16x4x2_t = vld2_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2p8 (void)
+{
+ poly8x8x2_t out_poly8x8x2_t;
+
+ out_poly8x8x2_t = vld2_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s16 (void)
+{
+ int16x4x2_t out_int16x4x2_t;
+
+ out_int16x4x2_t = vld2_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s32 (void)
+{
+ int32x2x2_t out_int32x2x2_t;
+
+ out_int32x2x2_t = vld2_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s64 (void)
+{
+ int64x1x2_t out_int64x1x2_t;
+
+ out_int64x1x2_t = vld2_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s8 (void)
+{
+ int8x8x2_t out_int8x8x2_t;
+
+ out_int8x8x2_t = vld2_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u16 (void)
+{
+ uint16x4x2_t out_uint16x4x2_t;
+
+ out_uint16x4x2_t = vld2_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u32 (void)
+{
+ uint32x2x2_t out_uint32x2x2_t;
+
+ out_uint32x2x2_t = vld2_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u64 (void)
+{
+ uint64x1x2_t out_uint64x1x2_t;
+
+ out_uint64x1x2_t = vld2_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld2u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld2u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u8 (void)
+{
+ uint8x8x2_t out_uint8x8x2_t;
+
+ out_uint8x8x2_t = vld2_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Q_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanef32 (void)
+{
+ float32x4x3_t out_float32x4x3_t;
+ float32x4x3_t arg1_float32x4x3_t;
+
+ out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Q_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanep16 (void)
+{
+ poly16x8x3_t out_poly16x8x3_t;
+ poly16x8x3_t arg1_poly16x8x3_t;
+
+ out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Q_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes16 (void)
+{
+ int16x8x3_t out_int16x8x3_t;
+ int16x8x3_t arg1_int16x8x3_t;
+
+ out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Q_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes32 (void)
+{
+ int32x4x3_t out_int32x4x3_t;
+ int32x4x3_t arg1_int32x4x3_t;
+
+ out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Q_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu16 (void)
+{
+ uint16x8x3_t out_uint16x8x3_t;
+ uint16x8x3_t arg1_uint16x8x3_t;
+
+ out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Q_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu32 (void)
+{
+ uint32x4x3_t out_uint32x4x3_t;
+ uint32x4x3_t arg1_uint32x4x3_t;
+
+ out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qf32 (void)
+{
+ float32x4x3_t out_float32x4x3_t;
+
+ out_float32x4x3_t = vld3q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp16 (void)
+{
+ poly16x8x3_t out_poly16x8x3_t;
+
+ out_poly16x8x3_t = vld3q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp8 (void)
+{
+ poly8x16x3_t out_poly8x16x3_t;
+
+ out_poly8x16x3_t = vld3q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs16 (void)
+{
+ int16x8x3_t out_int16x8x3_t;
+
+ out_int16x8x3_t = vld3q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs32 (void)
+{
+ int32x4x3_t out_int32x4x3_t;
+
+ out_int32x4x3_t = vld3q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs8 (void)
+{
+ int8x16x3_t out_int8x16x3_t;
+
+ out_int8x16x3_t = vld3q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu16 (void)
+{
+ uint16x8x3_t out_uint16x8x3_t;
+
+ out_uint16x8x3_t = vld3q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu32 (void)
+{
+ uint32x4x3_t out_uint32x4x3_t;
+
+ out_uint32x4x3_t = vld3q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3Qu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu8 (void)
+{
+ uint8x16x3_t out_uint8x16x3_t;
+
+ out_uint8x16x3_t = vld3q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dupf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupf32 (void)
+{
+ float32x2x3_t out_float32x2x3_t;
+
+ out_float32x2x3_t = vld3_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dupp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp16 (void)
+{
+ poly16x4x3_t out_poly16x4x3_t;
+
+ out_poly16x4x3_t = vld3_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dupp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp8 (void)
+{
+ poly8x8x3_t out_poly8x8x3_t;
+
+ out_poly8x8x3_t = vld3_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dups16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups16 (void)
+{
+ int16x4x3_t out_int16x4x3_t;
+
+ out_int16x4x3_t = vld3_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dups32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups32 (void)
+{
+ int32x2x3_t out_int32x2x3_t;
+
+ out_int32x2x3_t = vld3_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dups64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups64 (void)
+{
+ int64x1x3_t out_int64x1x3_t;
+
+ out_int64x1x3_t = vld3_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dups8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups8 (void)
+{
+ int8x8x3_t out_int8x8x3_t;
+
+ out_int8x8x3_t = vld3_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dupu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu16 (void)
+{
+ uint16x4x3_t out_uint16x4x3_t;
+
+ out_uint16x4x3_t = vld3_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dupu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu32 (void)
+{
+ uint32x2x3_t out_uint32x2x3_t;
+
+ out_uint32x2x3_t = vld3_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dupu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu64 (void)
+{
+ uint64x1x3_t out_uint64x1x3_t;
+
+ out_uint64x1x3_t = vld3_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_dupu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu8 (void)
+{
+ uint8x8x3_t out_uint8x8x3_t;
+
+ out_uint8x8x3_t = vld3_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanef32 (void)
+{
+ float32x2x3_t out_float32x2x3_t;
+ float32x2x3_t arg1_float32x2x3_t;
+
+ out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep16 (void)
+{
+ poly16x4x3_t out_poly16x4x3_t;
+ poly16x4x3_t arg1_poly16x4x3_t;
+
+ out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_lanep8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep8 (void)
+{
+ poly8x8x3_t out_poly8x8x3_t;
+ poly8x8x3_t arg1_poly8x8x3_t;
+
+ out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes16 (void)
+{
+ int16x4x3_t out_int16x4x3_t;
+ int16x4x3_t arg1_int16x4x3_t;
+
+ out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes32 (void)
+{
+ int32x2x3_t out_int32x2x3_t;
+ int32x2x3_t arg1_int32x2x3_t;
+
+ out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_lanes8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes8 (void)
+{
+ int8x8x3_t out_int8x8x3_t;
+ int8x8x3_t arg1_int8x8x3_t;
+
+ out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu16 (void)
+{
+ uint16x4x3_t out_uint16x4x3_t;
+ uint16x4x3_t arg1_uint16x4x3_t;
+
+ out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu32 (void)
+{
+ uint32x2x3_t out_uint32x2x3_t;
+ uint32x2x3_t arg1_uint32x2x3_t;
+
+ out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3_laneu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu8 (void)
+{
+ uint8x8x3_t out_uint8x8x3_t;
+ uint8x8x3_t arg1_uint8x8x3_t;
+
+ out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3f32 (void)
+{
+ float32x2x3_t out_float32x2x3_t;
+
+ out_float32x2x3_t = vld3_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3p16 (void)
+{
+ poly16x4x3_t out_poly16x4x3_t;
+
+ out_poly16x4x3_t = vld3_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3p8 (void)
+{
+ poly8x8x3_t out_poly8x8x3_t;
+
+ out_poly8x8x3_t = vld3_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s16 (void)
+{
+ int16x4x3_t out_int16x4x3_t;
+
+ out_int16x4x3_t = vld3_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s32 (void)
+{
+ int32x2x3_t out_int32x2x3_t;
+
+ out_int32x2x3_t = vld3_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s64 (void)
+{
+ int64x1x3_t out_int64x1x3_t;
+
+ out_int64x1x3_t = vld3_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s8 (void)
+{
+ int8x8x3_t out_int8x8x3_t;
+
+ out_int8x8x3_t = vld3_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u16 (void)
+{
+ uint16x4x3_t out_uint16x4x3_t;
+
+ out_uint16x4x3_t = vld3_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u32 (void)
+{
+ uint32x2x3_t out_uint32x2x3_t;
+
+ out_uint32x2x3_t = vld3_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u64 (void)
+{
+ uint64x1x3_t out_uint64x1x3_t;
+
+ out_uint64x1x3_t = vld3_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld3u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld3u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u8 (void)
+{
+ uint8x8x3_t out_uint8x8x3_t;
+
+ out_uint8x8x3_t = vld3_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Q_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanef32 (void)
+{
+ float32x4x4_t out_float32x4x4_t;
+ float32x4x4_t arg1_float32x4x4_t;
+
+ out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Q_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanep16 (void)
+{
+ poly16x8x4_t out_poly16x8x4_t;
+ poly16x8x4_t arg1_poly16x8x4_t;
+
+ out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Q_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes16 (void)
+{
+ int16x8x4_t out_int16x8x4_t;
+ int16x8x4_t arg1_int16x8x4_t;
+
+ out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Q_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes32 (void)
+{
+ int32x4x4_t out_int32x4x4_t;
+ int32x4x4_t arg1_int32x4x4_t;
+
+ out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Q_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu16 (void)
+{
+ uint16x8x4_t out_uint16x8x4_t;
+ uint16x8x4_t arg1_uint16x8x4_t;
+
+ out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Q_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu32 (void)
+{
+ uint32x4x4_t out_uint32x4x4_t;
+ uint32x4x4_t arg1_uint32x4x4_t;
+
+ out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qf32 (void)
+{
+ float32x4x4_t out_float32x4x4_t;
+
+ out_float32x4x4_t = vld4q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp16 (void)
+{
+ poly16x8x4_t out_poly16x8x4_t;
+
+ out_poly16x8x4_t = vld4q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp8 (void)
+{
+ poly8x16x4_t out_poly8x16x4_t;
+
+ out_poly8x16x4_t = vld4q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs16 (void)
+{
+ int16x8x4_t out_int16x8x4_t;
+
+ out_int16x8x4_t = vld4q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs32 (void)
+{
+ int32x4x4_t out_int32x4x4_t;
+
+ out_int32x4x4_t = vld4q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs8 (void)
+{
+ int8x16x4_t out_int8x16x4_t;
+
+ out_int8x16x4_t = vld4q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu16 (void)
+{
+ uint16x8x4_t out_uint16x8x4_t;
+
+ out_uint16x8x4_t = vld4q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu32 (void)
+{
+ uint32x4x4_t out_uint32x4x4_t;
+
+ out_uint32x4x4_t = vld4q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4Qu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu8 (void)
+{
+ uint8x16x4_t out_uint8x16x4_t;
+
+ out_uint8x16x4_t = vld4q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dupf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupf32 (void)
+{
+ float32x2x4_t out_float32x2x4_t;
+
+ out_float32x2x4_t = vld4_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dupp16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp16 (void)
+{
+ poly16x4x4_t out_poly16x4x4_t;
+
+ out_poly16x4x4_t = vld4_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dupp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp8 (void)
+{
+ poly8x8x4_t out_poly8x8x4_t;
+
+ out_poly8x8x4_t = vld4_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dups16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups16 (void)
+{
+ int16x4x4_t out_int16x4x4_t;
+
+ out_int16x4x4_t = vld4_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dups32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups32 (void)
+{
+ int32x2x4_t out_int32x2x4_t;
+
+ out_int32x2x4_t = vld4_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dups64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups64 (void)
+{
+ int64x1x4_t out_int64x1x4_t;
+
+ out_int64x1x4_t = vld4_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dups8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups8 (void)
+{
+ int8x8x4_t out_int8x8x4_t;
+
+ out_int8x8x4_t = vld4_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dupu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu16 (void)
+{
+ uint16x4x4_t out_uint16x4x4_t;
+
+ out_uint16x4x4_t = vld4_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dupu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu32 (void)
+{
+ uint32x2x4_t out_uint32x2x4_t;
+
+ out_uint32x2x4_t = vld4_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dupu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu64 (void)
+{
+ uint64x1x4_t out_uint64x1x4_t;
+
+ out_uint64x1x4_t = vld4_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_dupu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu8 (void)
+{
+ uint8x8x4_t out_uint8x8x4_t;
+
+ out_uint8x8x4_t = vld4_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanef32 (void)
+{
+ float32x2x4_t out_float32x2x4_t;
+ float32x2x4_t arg1_float32x2x4_t;
+
+ out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_lanep16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep16 (void)
+{
+ poly16x4x4_t out_poly16x4x4_t;
+ poly16x4x4_t arg1_poly16x4x4_t;
+
+ out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_lanep8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep8 (void)
+{
+ poly8x8x4_t out_poly8x8x4_t;
+ poly8x8x4_t arg1_poly8x8x4_t;
+
+ out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes16 (void)
+{
+ int16x4x4_t out_int16x4x4_t;
+ int16x4x4_t arg1_int16x4x4_t;
+
+ out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes32 (void)
+{
+ int32x2x4_t out_int32x2x4_t;
+ int32x2x4_t arg1_int32x2x4_t;
+
+ out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_lanes8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes8 (void)
+{
+ int8x8x4_t out_int8x8x4_t;
+ int8x8x4_t arg1_int8x8x4_t;
+
+ out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu16 (void)
+{
+ uint16x4x4_t out_uint16x4x4_t;
+ uint16x4x4_t arg1_uint16x4x4_t;
+
+ out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu32 (void)
+{
+ uint32x2x4_t out_uint32x2x4_t;
+ uint32x2x4_t arg1_uint32x2x4_t;
+
+ out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4_laneu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu8 (void)
+{
+ uint8x8x4_t out_uint8x8x4_t;
+ uint8x8x4_t arg1_uint8x8x4_t;
+
+ out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4f32 (void)
+{
+ float32x2x4_t out_float32x2x4_t;
+
+ out_float32x2x4_t = vld4_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4p16 (void)
+{
+ poly16x4x4_t out_poly16x4x4_t;
+
+ out_poly16x4x4_t = vld4_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4p8 (void)
+{
+ poly8x8x4_t out_poly8x8x4_t;
+
+ out_poly8x8x4_t = vld4_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s16 (void)
+{
+ int16x4x4_t out_int16x4x4_t;
+
+ out_int16x4x4_t = vld4_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s32 (void)
+{
+ int32x2x4_t out_int32x2x4_t;
+
+ out_int32x2x4_t = vld4_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s64 (void)
+{
+ int64x1x4_t out_int64x1x4_t;
+
+ out_int64x1x4_t = vld4_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s8 (void)
+{
+ int8x8x4_t out_int8x8x4_t;
+
+ out_int8x8x4_t = vld4_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u16 (void)
+{
+ uint16x4x4_t out_uint16x4x4_t;
+
+ out_uint16x4x4_t = vld4_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u32 (void)
+{
+ uint32x2x4_t out_uint32x2x4_t;
+
+ out_uint32x2x4_t = vld4_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u64 (void)
+{
+ uint64x1x4_t out_uint64x1x4_t;
+
+ out_uint64x1x4_t = vld4_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vld4u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vld4u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u8 (void)
+{
+ uint8x8x4_t out_uint8x8x4_t;
+
+ out_uint8x8x4_t = vld4_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+
+ out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmaxu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+
+ out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmins16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmins32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmins8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmins8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vminu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vminu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanef32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32_t arg2_float32_t;
+
+ out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+ int16_t arg2_int16_t;
+
+ out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+ int32_t arg2_int32_t;
+
+ out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+ uint16_t arg2_uint16_t;
+
+ out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQ_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+ uint32_t arg2_uint32_t;
+
+ out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32x4_t arg2_float32x4_t;
+
+ out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+ int16x8_t arg2_int16x8_t;
+
+ out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+ int32x4_t arg2_int32x4_t;
+
+ out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+ int8x16_t arg2_int8x16_t;
+
+ out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+ uint16x8_t arg2_uint16x8_t;
+
+ out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+ uint32x4_t arg2_uint32x4_t;
+
+ out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+ uint8x16_t arg2_uint8x16_t;
+
+ out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanef32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32_t arg2_float32_t;
+
+ out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16_t arg2_int16_t;
+
+ out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32_t arg2_int32_t;
+
+ out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16_t arg2_uint16_t;
+
+ out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmla_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32_t arg2_uint32_t;
+
+ out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlaf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16_t arg2_int16_t;
+
+ out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32_t arg2_int32_t;
+
+ out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16_t arg2_uint16_t;
+
+ out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlal_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32_t arg2_uint32_t;
+
+ out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlals16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlals32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlals8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlals8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals8 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int8x8_t arg1_int8x8_t;
+ int8x8_t arg2_int8x8_t;
+
+ out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlalu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlalu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlalu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint8x8_t arg1_uint8x8_t;
+ uint8x8_t arg2_uint8x8_t;
+
+ out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlas16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlas32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlas8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlas8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+ int8x8_t arg2_int8x8_t;
+
+ out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlau16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlau32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlau8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlau8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+ uint8x8_t arg2_uint8x8_t;
+
+ out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanef32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32_t arg2_float32_t;
+
+ out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+ int16_t arg2_int16_t;
+
+ out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+ int32_t arg2_int32_t;
+
+ out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+ uint16_t arg2_uint16_t;
+
+ out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQ_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+ uint32_t arg2_uint32_t;
+
+ out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32x4_t arg2_float32x4_t;
+
+ out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+ int16x8_t arg2_int16x8_t;
+
+ out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+ int32x4_t arg2_int32x4_t;
+
+ out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+ int8x16_t arg2_int8x16_t;
+
+ out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+ uint16x8_t arg2_uint16x8_t;
+
+ out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+ uint32x4_t arg2_uint32x4_t;
+
+ out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+ uint8x16_t arg2_uint8x16_t;
+
+ out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanef32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32_t arg2_float32_t;
+
+ out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16_t arg2_int16_t;
+
+ out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32_t arg2_int32_t;
+
+ out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16_t arg2_uint16_t;
+
+ out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmls_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32_t arg2_uint32_t;
+
+ out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16_t arg2_int16_t;
+
+ out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32_t arg2_int32_t;
+
+ out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16_t arg2_uint16_t;
+
+ out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsl_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32_t arg2_uint32_t;
+
+ out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsls8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls8 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int8x8_t arg1_int8x8_t;
+ int8x8_t arg2_int8x8_t;
+
+ out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlslu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlslu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlslu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint8x8_t arg1_uint8x8_t;
+ uint8x8_t arg2_uint8x8_t;
+
+ out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlss16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlss32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlss8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlss8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+ int8x8_t arg2_int8x8_t;
+
+ out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+ uint16x4_t arg2_uint16x4_t;
+
+ out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+ uint32x2_t arg2_uint32x2_t;
+
+ out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmlsu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+ uint8x8_t arg2_uint8x8_t;
+
+ out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32_t arg0_float32_t;
+
+ out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_np16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np16 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ poly16_t arg0_poly16_t;
+
+ out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_np8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ poly8_t arg0_poly8_t;
+
+ out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16_t arg0_int16_t;
+
+ out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32_t arg0_int32_t;
+
+ out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64_t arg0_int64_t;
+
+ out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_ns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8_t arg0_int8_t;
+
+ out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16_t arg0_uint16_t;
+
+ out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32_t arg0_uint32_t;
+
+ out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_nu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64_t arg0_uint64_t;
+
+ out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovQ_nu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8_t arg0_uint8_t;
+
+ out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32_t arg0_float32_t;
+
+ out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_np16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_np16 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ poly16_t arg0_poly16_t;
+
+ out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_np8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_np8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ poly8_t arg0_poly8_t;
+
+ out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16_t arg0_int16_t;
+
+ out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32_t arg0_int32_t;
+
+ out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64_t arg0_int64_t;
+
+ out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_ns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8_t arg0_int8_t;
+
+ out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16_t arg0_uint16_t;
+
+ out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32_t arg0_uint32_t;
+
+ out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_nu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64_t arg0_uint64_t;
+
+ out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmov_nu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8_t arg0_uint8_t;
+
+ out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovls8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls8 (void)
+{
+ int16x8_t out_int16x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovlu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovlu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovlu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns16 (void)
+{
+ int8x8_t out_int8x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns32 (void)
+{
+ int16x4_t out_int16x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns64 (void)
+{
+ int32x2_t out_int32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovnu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu16 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovnu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu32 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmovnu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanef32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32_t arg1_float32_t;
+
+ out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16_t arg1_int16_t;
+
+ out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32_t arg1_int32_t;
+
+ out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16_t arg1_uint16_t;
+
+ out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQ_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32_t arg1_uint32_t;
+
+ out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+
+ out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQp8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ poly8x16_t arg0_poly8x16_t;
+ poly8x16_t arg1_poly8x16_t;
+
+ out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_lanef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanef32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_nf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32_t arg1_float32_t;
+
+ out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16_t arg1_int16_t;
+
+ out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32_t arg1_int32_t;
+
+ out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16_t arg1_uint16_t;
+
+ out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmul_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32_t arg1_uint32_t;
+
+ out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_laneu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_laneu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16_t arg1_int16_t;
+
+ out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32_t arg1_int32_t;
+
+ out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16_t arg1_uint16_t;
+
+ out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmull_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32_t arg1_uint32_t;
+
+ out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmullp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullp8 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ poly8x8_t arg0_poly8x8_t;
+ poly8x8_t arg1_poly8x8_t;
+
+ out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.p8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulls8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls8 (void)
+{
+ int16x8_t out_int16x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmullu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmullu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmullu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmullu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulp8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ poly8x8_t arg0_poly8x8_t;
+ poly8x8_t arg1_poly8x8_t;
+
+ out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmuls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmuls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmuls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmuls8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmulu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmulu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnQp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQp8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnp8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnp8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ poly8x8_t arg0_poly8x8_t;
+
+ out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vmvnu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vnegs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vnegs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint64x2_t arg1_uint64x2_t;
+
+ out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+ uint64x1_t arg1_uint64x1_t;
+
+ out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vornu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vornu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint64x2_t arg1_uint64x2_t;
+
+ out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorrs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorrs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorru16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorru32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorru64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+ uint64x1_t arg1_uint64x1_t;
+
+ out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vorru8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vorru8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs8 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadals16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals16 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadals32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals32 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadals8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadals8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals8 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu16 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu32 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadalu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu8 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs8 (void)
+{
+ int16x8_t out_int16x8_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls16 (void)
+{
+ int32x2_t out_int32x2_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls32 (void)
+{
+ int64x1_t out_int64x1_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddls8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls8 (void)
+{
+ int16x4_t out_int16x4_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu16 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu32 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddlu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu8 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadds16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadds32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpadds8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpadds8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpaddu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmaxf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmaxs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmaxs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmaxs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmaxu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmaxu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmaxu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpminf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmins16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmins32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpmins8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpmins8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpminu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpminu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vpminu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vpminu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16_t arg1_int16_t;
+
+ out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32_t arg1_int32_t;
+
+ out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulh_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16_t arg1_int16_t;
+
+ out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulh_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32_t arg1_int32_t;
+
+ out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRdmulhs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshls64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshls8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshlu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrn_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns16 (void)
+{
+ int8x8_t out_int8x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrn_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns32 (void)
+{
+ int16x4_t out_int16x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrn_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns64 (void)
+{
+ int32x2_t out_int32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrn_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu16 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrn_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu32 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrn_nu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrun_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns16 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrun_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns32 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqRshrun_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqabsQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqabsQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqabsQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqabss16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqabss32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqabss8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqabss8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint64x2_t arg1_uint64x2_t;
+
+ out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqadds16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqadds32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqadds64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqadds8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqadds8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+ uint64x1_t arg1_uint64x1_t;
+
+ out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqaddu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlal_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlal_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlal_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16_t arg2_int16_t;
+
+ out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlal_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32_t arg2_int32_t;
+
+ out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlals16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlals32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlsl_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16_t arg2_int16_t;
+
+ out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlsl_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32_t arg2_int32_t;
+
+ out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlsls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int16x4_t arg1_int16x4_t;
+ int16x4_t arg2_int16x4_t;
+
+ out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,22 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmlsls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int32x2_t arg1_int32x2_t;
+ int32x2_t arg2_int32x2_t;
+
+ out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16_t arg1_int16_t;
+
+ out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32_t arg1_int32_t;
+
+ out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulh_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulh_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulh_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16_t arg1_int16_t;
+
+ out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulh_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32_t arg1_int32_t;
+
+ out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulhs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmull_lanes16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmull_lanes32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmull_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16_t arg1_int16_t;
+
+ out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmull_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32_t arg1_int32_t;
+
+ out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqdmulls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns16 (void)
+{
+ int8x8_t out_int8x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns32 (void)
+{
+ int16x4_t out_int16x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns64 (void)
+{
+ int32x2_t out_int32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovnu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu16 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovnu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu32 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovnu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovuns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns16 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovuns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns32 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqmovuns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqnegQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqnegQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqnegQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqnegs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqnegs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqnegs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_ns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_nu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQ_nu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+
+ out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_ns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_nu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+
+ out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshl_nu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshls16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshls32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshls64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshls8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshls8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshluQ_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshluQ_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshluQ_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshluQ_ns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ int64x1_t arg0_int64x1_t;
+
+ out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshlu_ns8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrn_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns16 (void)
+{
+ int8x8_t out_int8x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrn_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns32 (void)
+{
+ int16x4_t out_int16x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrn_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns64 (void)
+{
+ int32x2_t out_int32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrn_nu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu16 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrn_nu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu32 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrn_nu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrun_ns16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns16 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrun_ns32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns32 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqshrun_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs16 (void)
+{
+ int16x8_t out_int16x8_t;
+ int16x8_t arg0_int16x8_t;
+ int16x8_t arg1_int16x8_t;
+
+ out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs32 (void)
+{
+ int32x4_t out_int32x4_t;
+ int32x4_t arg0_int32x4_t;
+ int32x4_t arg1_int32x4_t;
+
+ out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs64 (void)
+{
+ int64x2_t out_int64x2_t;
+ int64x2_t arg0_int64x2_t;
+ int64x2_t arg1_int64x2_t;
+
+ out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs8 (void)
+{
+ int8x16_t out_int8x16_t;
+ int8x16_t arg0_int8x16_t;
+ int8x16_t arg1_int8x16_t;
+
+ out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+ uint16x8_t arg1_uint16x8_t;
+
+ out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+ uint32x4_t arg1_uint32x4_t;
+
+ out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+ uint64x2_t arg1_uint64x2_t;
+
+ out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubQu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+ uint8x16_t arg1_uint8x16_t;
+
+ out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubs16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs16 (void)
+{
+ int16x4_t out_int16x4_t;
+ int16x4_t arg0_int16x4_t;
+ int16x4_t arg1_int16x4_t;
+
+ out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubs32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs32 (void)
+{
+ int32x2_t out_int32x2_t;
+ int32x2_t arg0_int32x2_t;
+ int32x2_t arg1_int32x2_t;
+
+ out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubs64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs64 (void)
+{
+ int64x1_t out_int64x1_t;
+ int64x1_t arg0_int64x1_t;
+ int64x1_t arg1_int64x1_t;
+
+ out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubs8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs8 (void)
+{
+ int8x8_t out_int8x8_t;
+ int8x8_t arg0_int8x8_t;
+ int8x8_t arg1_int8x8_t;
+
+ out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubu16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu16 (void)
+{
+ uint16x4_t out_uint16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+ uint16x4_t arg1_uint16x4_t;
+
+ out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+ uint32x2_t arg1_uint32x2_t;
+
+ out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubu64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu64 (void)
+{
+ uint64x1_t out_uint64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+ uint64x1_t arg1_uint64x1_t;
+
+ out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vqsubu8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu8 (void)
+{
+ uint8x8_t out_uint8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+ uint8x8_t arg1_uint8x8_t;
+
+ out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrecpeQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrecpeQu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQu32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrecpef32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpef32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,20 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrecpeu32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeu32 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrecpsQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpsQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+
+ out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,21 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vrecpsf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpsf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+
+ out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p16 (void)
+{
+ float32x4_t out_float32x4_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p8 (void)
+{
+ float32x4_t out_float32x4_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s16 (void)
+{
+ float32x4_t out_float32x4_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s32 (void)
+{
+ float32x4_t out_float32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s64 (void)
+{
+ float32x4_t out_float32x4_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s8 (void)
+{
+ float32x4_t out_float32x4_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u16 (void)
+{
+ float32x4_t out_float32x4_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u32 (void)
+{
+ float32x4_t out_float32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u64 (void)
+{
+ float32x4_t out_float32x4_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u8 (void)
+{
+ float32x4_t out_float32x4_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_f32 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p8 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s16 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s32 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s64 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s8 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u16 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u32 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u64 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u8 (void)
+{
+ poly16x8_t out_poly16x8_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_f32 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p16 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s16 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s32 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s64 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u16 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u32 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u64 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u8 (void)
+{
+ poly8x16_t out_poly8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_f32 (void)
+{
+ int16x8_t out_int16x8_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p16 (void)
+{
+ int16x8_t out_int16x8_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p8 (void)
+{
+ int16x8_t out_int16x8_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s32 (void)
+{
+ int16x8_t out_int16x8_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s64 (void)
+{
+ int16x8_t out_int16x8_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s8 (void)
+{
+ int16x8_t out_int16x8_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u16 (void)
+{
+ int16x8_t out_int16x8_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u32 (void)
+{
+ int16x8_t out_int16x8_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u64 (void)
+{
+ int16x8_t out_int16x8_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u8 (void)
+{
+ int16x8_t out_int16x8_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_f32 (void)
+{
+ int32x4_t out_int32x4_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p16 (void)
+{
+ int32x4_t out_int32x4_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p8 (void)
+{
+ int32x4_t out_int32x4_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s16 (void)
+{
+ int32x4_t out_int32x4_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s64 (void)
+{
+ int32x4_t out_int32x4_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s8 (void)
+{
+ int32x4_t out_int32x4_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u16 (void)
+{
+ int32x4_t out_int32x4_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u32 (void)
+{
+ int32x4_t out_int32x4_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u64 (void)
+{
+ int32x4_t out_int32x4_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u8 (void)
+{
+ int32x4_t out_int32x4_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_f32 (void)
+{
+ int64x2_t out_int64x2_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p16 (void)
+{
+ int64x2_t out_int64x2_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p8 (void)
+{
+ int64x2_t out_int64x2_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s16 (void)
+{
+ int64x2_t out_int64x2_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s32 (void)
+{
+ int64x2_t out_int64x2_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s8 (void)
+{
+ int64x2_t out_int64x2_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u16 (void)
+{
+ int64x2_t out_int64x2_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u32 (void)
+{
+ int64x2_t out_int64x2_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u64 (void)
+{
+ int64x2_t out_int64x2_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u8 (void)
+{
+ int64x2_t out_int64x2_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_f32 (void)
+{
+ int8x16_t out_int8x16_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p16 (void)
+{
+ int8x16_t out_int8x16_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p8 (void)
+{
+ int8x16_t out_int8x16_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s16 (void)
+{
+ int8x16_t out_int8x16_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s32 (void)
+{
+ int8x16_t out_int8x16_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s64 (void)
+{
+ int8x16_t out_int8x16_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u16 (void)
+{
+ int8x16_t out_int8x16_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u32 (void)
+{
+ int8x16_t out_int8x16_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u64 (void)
+{
+ int8x16_t out_int8x16_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u8 (void)
+{
+ int8x16_t out_int8x16_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_f32 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s16 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s32 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s64 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u32 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u64 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u8 (void)
+{
+ uint16x8_t out_uint16x8_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_f32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p8 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s32 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s64 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s8 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u16 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u64 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u8 (void)
+{
+ uint32x4_t out_uint32x4_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_f32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p16 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p8 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s16 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s64 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s8 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u16 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u32 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u8 (void)
+{
+ uint64x2_t out_uint64x2_t;
+ uint8x16_t arg0_uint8x16_t;
+
+ out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_f32 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ float32x4_t arg0_float32x4_t;
+
+ out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p16 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ poly16x8_t arg0_poly16x8_t;
+
+ out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ poly8x16_t arg0_poly8x16_t;
+
+ out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s16 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ int16x8_t arg0_int16x8_t;
+
+ out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s32 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ int32x4_t arg0_int32x4_t;
+
+ out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s64 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s8 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ int8x16_t arg0_int8x16_t;
+
+ out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u16 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint16x8_t arg0_uint16x8_t;
+
+ out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u32 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint32x4_t arg0_uint32x4_t;
+
+ out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u64 (void)
+{
+ uint8x16_t out_uint8x16_t;
+ uint64x2_t arg0_uint64x2_t;
+
+ out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p16 (void)
+{
+ float32x2_t out_float32x2_t;
+ poly16x4_t arg0_poly16x4_t;
+
+ out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p8 (void)
+{
+ float32x2_t out_float32x2_t;
+ poly8x8_t arg0_poly8x8_t;
+
+ out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s16 (void)
+{
+ float32x2_t out_float32x2_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s32 (void)
+{
+ float32x2_t out_float32x2_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s64 (void)
+{
+ float32x2_t out_float32x2_t;
+ int64x1_t arg0_int64x1_t;
+
+ out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s8 (void)
+{
+ float32x2_t out_float32x2_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u16 (void)
+{
+ float32x2_t out_float32x2_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u32 (void)
+{
+ float32x2_t out_float32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u64 (void)
+{
+ float32x2_t out_float32x2_t;
+ uint64x1_t arg0_uint64x1_t;
+
+ out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretf32_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u8 (void)
+{
+ float32x2_t out_float32x2_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_f32 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p8 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ poly8x8_t arg0_poly8x8_t;
+
+ out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s16 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s32 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s64 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ int64x1_t arg0_int64x1_t;
+
+ out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s8 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u16 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u32 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u64 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ uint64x1_t arg0_uint64x1_t;
+
+ out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp16_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u8 (void)
+{
+ poly16x4_t out_poly16x4_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_f32 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p16 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ poly16x4_t arg0_poly16x4_t;
+
+ out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s16 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s32 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s64 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ int64x1_t arg0_int64x1_t;
+
+ out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u16 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u32 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u64 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ uint64x1_t arg0_uint64x1_t;
+
+ out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterpretp8_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u8 (void)
+{
+ poly8x8_t out_poly8x8_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_f32 (void)
+{
+ int16x4_t out_int16x4_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p16 (void)
+{
+ int16x4_t out_int16x4_t;
+ poly16x4_t arg0_poly16x4_t;
+
+ out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p8 (void)
+{
+ int16x4_t out_int16x4_t;
+ poly8x8_t arg0_poly8x8_t;
+
+ out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s32 (void)
+{
+ int16x4_t out_int16x4_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s64 (void)
+{
+ int16x4_t out_int16x4_t;
+ int64x1_t arg0_int64x1_t;
+
+ out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s8 (void)
+{
+ int16x4_t out_int16x4_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u16 (void)
+{
+ int16x4_t out_int16x4_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u32 (void)
+{
+ int16x4_t out_int16x4_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u64 (void)
+{
+ int16x4_t out_int16x4_t;
+ uint64x1_t arg0_uint64x1_t;
+
+ out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets16_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u8 (void)
+{
+ int16x4_t out_int16x4_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_f32 (void)
+{
+ int32x2_t out_int32x2_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p16 (void)
+{
+ int32x2_t out_int32x2_t;
+ poly16x4_t arg0_poly16x4_t;
+
+ out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p8 (void)
+{
+ int32x2_t out_int32x2_t;
+ poly8x8_t arg0_poly8x8_t;
+
+ out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s16 (void)
+{
+ int32x2_t out_int32x2_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_s64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s64 (void)
+{
+ int32x2_t out_int32x2_t;
+ int64x1_t arg0_int64x1_t;
+
+ out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s8 (void)
+{
+ int32x2_t out_int32x2_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u16 (void)
+{
+ int32x2_t out_int32x2_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u32 (void)
+{
+ int32x2_t out_int32x2_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u64 (void)
+{
+ int32x2_t out_int32x2_t;
+ uint64x1_t arg0_uint64x1_t;
+
+ out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets32_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u8 (void)
+{
+ int32x2_t out_int32x2_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_f32 (void)
+{
+ int64x1_t out_int64x1_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p16 (void)
+{
+ int64x1_t out_int64x1_t;
+ poly16x4_t arg0_poly16x4_t;
+
+ out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p8 (void)
+{
+ int64x1_t out_int64x1_t;
+ poly8x8_t arg0_poly8x8_t;
+
+ out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s16 (void)
+{
+ int64x1_t out_int64x1_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s32 (void)
+{
+ int64x1_t out_int64x1_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_s8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s8 (void)
+{
+ int64x1_t out_int64x1_t;
+ int8x8_t arg0_int8x8_t;
+
+ out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_u16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u16 (void)
+{
+ int64x1_t out_int64x1_t;
+ uint16x4_t arg0_uint16x4_t;
+
+ out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_u32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u32 (void)
+{
+ int64x1_t out_int64x1_t;
+ uint32x2_t arg0_uint32x2_t;
+
+ out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u64 (void)
+{
+ int64x1_t out_int64x1_t;
+ uint64x1_t arg0_uint64x1_t;
+
+ out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets64_u8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u8 (void)
+{
+ int64x1_t out_int64x1_t;
+ uint8x8_t arg0_uint8x8_t;
+
+ out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_f32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_f32 (void)
+{
+ int8x8_t out_int8x8_t;
+ float32x2_t arg0_float32x2_t;
+
+ out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_p16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p16 (void)
+{
+ int8x8_t out_int8x8_t;
+ poly16x4_t arg0_poly16x4_t;
+
+ out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_p8' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p8 (void)
+{
+ int8x8_t out_int8x8_t;
+ poly8x8_t arg0_poly8x8_t;
+
+ out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_s16' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s16 (void)
+{
+ int8x8_t out_int8x8_t;
+ int16x4_t arg0_int16x4_t;
+
+ out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c?rev=76781&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c Wed Jul 22 15:36:27 2009
@@ -0,0 +1,19 @@
+/* APPLE LOCAL file v7 merge */
+/* Test the `vreinterprets8_s32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s32 (void)
+{
+ int8x8_t out_int8x8_t;
+ int32x2_t arg0_int32x2_t;
+
+ out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
More information about the llvm-commits
mailing list