[llvm-commits] LLVM Verilog Backend

Dan Gohman gohman at apple.com
Mon Jul 20 13:18:28 PDT 2009


On Jul 18, 2009, at 4:22 AM, Nadav wrote:


> Hello,
>
> My name is Nadav Rotem and I am a PhD student at Haifa University.  
> In my research (in High-level Synthesis), I developed a Verilog  
> backend for LLVM that I would like to contribute to LLVM. The  
> Verilog Backend is documented in an academic paper [1].  An on-line  
> web interface is available [2].
>
> I attached the code to this email. The code compiles with LLVM 2.5;  
> I only included the Backend itself. I did not include the  
> preliminary transformation passes, the driver scripts and the test  
> cases.

Hello,

Are you planning to contribute the transformation passes and/or other
components, or just this backend? Is this backend usable without these
other parts?

Do you have any tests, or any examples, that can be used to demonstrate
this backend?

Thanks,

Dan




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