[llvm-commits] [llvm] r76000 - in /llvm/trunk: lib/Target/SystemZ/SystemZISelDAGToDAG.cpp lib/Target/SystemZ/SystemZInstrInfo.td lib/Target/SystemZ/SystemZOperands.td test/CodeGen/SystemZ/2009-07-04-Shl32.ll

[Anton Korobeynikov]

Author: asl
Date: Thu Jul 16 09:13:24 2009
New Revision: 76000

URL: http://llvm.org/viewvc/llvm-project?rev=76000&view=rev
Log:
32 bit shifts have only 12 bit displacements

Added:
    llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll
Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
    llvm/trunk/lib/Target/SystemZ/SystemZOperands.td

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=76000&r1=75999&r2=76000&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Jul 16 09:13:24 2009
@@ -114,8 +114,11 @@
     #include "SystemZGenDAGISel.inc"
 
   private:
+    bool SelectAddrRI12Only(SDValue Op, SDValue& Addr,
+                            SDValue &Base, SDValue &Disp);
     bool SelectAddrRI12(SDValue Op, SDValue& Addr,
-                        SDValue &Base, SDValue &Disp);
+                        SDValue &Base, SDValue &Disp,
+                        bool is12BitOnly = false);
     bool SelectAddrRI(SDValue Op, SDValue& Addr,
                       SDValue &Base, SDValue &Disp);
     bool SelectAddrRRI12(SDValue Op, SDValue Addr,
@@ -346,8 +349,14 @@
 
 /// Returns true if the address can be represented by a base register plus
 /// an unsigned 12-bit displacement [r+imm].
+bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr,
+                                             SDValue &Base, SDValue &Disp) {
+  return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
+}
+
 bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
-                                         SDValue &Base, SDValue &Disp) {
+                                         SDValue &Base, SDValue &Disp,
+                                         bool is12BitOnly) {
   SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
   bool Done = false;
 
@@ -373,7 +382,8 @@
     return false;
 
   // Check, whether we can match stuff using 20-bit displacements
-  if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
+  if (!Done && !is12BitOnly &&
+      !MatchAddress(Addr, AM20, /* is12Bit */ false))
     if (AM12.Disp == 0 && AM20.Disp != 0)
       return false;
 

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=76000&r1=75999&r2=76000&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Thu Jul 16 09:13:24 2009
@@ -652,7 +652,7 @@
                        [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>;
 
 //===----------------------------------------------------------------------===//
-// Test instructions (like AND but do not produce any result
+// Test instructions (like AND but do not produce any result)
 
 // Integer comparisons
 let Defs = [PSW] in {

Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td?rev=76000&r1=75999&r2=76000&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZOperands.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperands.td Thu Jul 16 09:13:24 2009
@@ -252,7 +252,7 @@
 
 // riaddr := reg + imm
 def riaddr32 : Operand<i32>,
-               ComplexPattern<i32, 2, "SelectAddrRI12", []> {
+               ComplexPattern<i32, 2, "SelectAddrRI12Only", []> {
   let PrintMethod = "printRIAddrOperand";
   let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
 }

Added: llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll?rev=76000&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll Thu Jul 16 09:13:24 2009
@@ -0,0 +1,27 @@
+; RUN: llvm-as < %s | llc
+
+target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
+target triple = "s390x-linux"
+
+define void @compdecomp(i8* nocapture %data, i64 %data_len) nounwind {
+entry:
+	br label %for.body38
+
+for.body38:		; preds = %for.body38, %entry
+	br i1 undef, label %for.cond220, label %for.body38
+
+for.cond220:		; preds = %for.cond220, %for.body38
+	br i1 false, label %for.cond220, label %for.end297
+
+for.end297:		; preds = %for.cond220
+	%tmp334 = load i8* undef		; <i8> [#uses=1]
+	%conv343 = zext i8 %tmp334 to i32		; <i32> [#uses=1]
+	%sub344 = add i32 %conv343, -1		; <i32> [#uses=1]
+	%shl345 = shl i32 1, %sub344		; <i32> [#uses=1]
+	%conv346 = sext i32 %shl345 to i64		; <i64> [#uses=1]
+	br label %for.body356
+
+for.body356:		; preds = %for.body356, %for.end297
+	%mask.1633 = phi i64 [ %conv346, %for.end297 ], [ undef, %for.body356 ]		; <i64> [#uses=0]
+	br label %for.body356
+}