[llvm-commits] [llvm] r75991 - /llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

Anton Korobeynikov asl at math.spbu.ru
Thu Jul 16 07:10:35 PDT 2009


Author: asl
Date: Thu Jul 16 09:10:35 2009
New Revision: 75991

URL: http://llvm.org/viewvc/llvm-project?rev=75991&view=rev
Log:
Typos

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=75991&r1=75990&r2=75991&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Thu Jul 16 09:10:35 2009
@@ -312,7 +312,7 @@
                                            SystemZRRIAddressMode &AM) {
   // Is the base register already occupied?
   if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
-    // If so, check to see if the scale register is set.
+    // If so, check to see if the index register is set.
     if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
       AM.IndexReg = N;
       return false;
@@ -439,7 +439,7 @@
 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
                                 SDValue &Base, SDValue &Disp, SDValue &Index) {
-  SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
+  SystemZRRIAddressMode AM20, AM12;
   bool Done = false;
 
   if (!Addr.hasOneUse()) {





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