[llvm-commits] [llvm] r75957 - /llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td

Anton Korobeynikov asl at math.spbu.ru
Thu Jul 16 06:56:13 PDT 2009


Author: asl
Date: Thu Jul 16 08:56:11 2009
New Revision: 75957

URL: http://llvm.org/viewvc/llvm-project?rev=75957&view=rev
Log:
Fix thinko

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td

Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td?rev=75957&r1=75956&r2=75957&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td Thu Jul 16 08:56:11 2009
@@ -119,26 +119,24 @@
 def PSW : SystemZReg<"psw">;
 
 def subreg_32bit  : PatLeaf<(i32 1)>;
-def subreg_64even : PatLeaf<(i32 2)>;
-def subreg_64odd  : PatLeaf<(i32 3)>;
-def subreg_32even : PatLeaf<(i32 4)>;
-def subreg_32odd  : PatLeaf<(i32 5)>;
+def subreg_even   : PatLeaf<(i32 1)>;
+def subreg_odd    : PatLeaf<(i32 2)>;
 
 def : SubRegSet<1, [R0D, R1D,  R2D,  R3D,  R4D,  R5D,  R6D,  R7D,
                     R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
                    [R0W, R1W,  R2W,  R3W,  R4W,  R5W,  R6W,  R7W,
                     R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
 
-def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
                    [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
 
-def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
                    [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
 
-def : SubRegSet<4, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
                    [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
 
-def : SubRegSet<5, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
                    [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
 
 /// Register classes





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