[llvm-commits] [llvm] r75928 - /llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td

[Anton Korobeynikov]

Author: asl
Date: Thu Jul 16 08:43:40 2009
New Revision: 75928

URL: http://llvm.org/viewvc/llvm-project?rev=75928&view=rev
Log:
Change register allocation order, so R0 will be allocated the last among scratch. This will make address-calculation code much more happy.

Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td

Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td?rev=75928&r1=75927&r2=75928&view=diff

==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td Thu Jul 16 08:43:40 2009
@@ -103,7 +103,7 @@
 /// Register classes
 def GR32 : RegisterClass<"SystemZ", [i32], 32,
    // Volatile registers
-  [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
+  [R1W, R2W, R3W, R4W, R5W, R0W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
    // Frame pointer, sometimes allocable
    R11W,
    // Volatile, but not allocable
@@ -156,7 +156,7 @@
 
 def GR64 : RegisterClass<"SystemZ", [i64], 64,
    // Volatile registers
-  [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
+  [R1D, R2D, R3D, R4D, R5D, R0D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
    // Frame pointer, sometimes allocable
    R11D,
    // Volatile, but not allocable