[llvm-commits] [llvm] r75065 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td
Evan Cheng
evan.cheng at apple.com
Wed Jul 8 15:51:48 PDT 2009
Author: evancheng
Date: Wed Jul 8 17:51:32 2009
New Revision: 75065
URL: http://llvm.org/viewvc/llvm-project?rev=75065&view=rev
Log:
- Add some NEON ld / st instruction static encoding.
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=75065&r1=75064&r2=75065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jul 8 17:51:32 2009
@@ -451,6 +451,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
class AXI3ldh<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
@@ -475,6 +476,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
class AXI3ldsh<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
@@ -499,6 +501,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
class AXI3ldsb<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
@@ -523,6 +526,7 @@
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
// stores
@@ -537,6 +541,7 @@
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
class AXI3sth<dag oops, dag iops, Format f, string asm,
list<dag> pattern>
@@ -561,6 +566,7 @@
let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
// Pre-indexed loads
@@ -575,6 +581,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
class AI3ldshpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
@@ -587,6 +594,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
@@ -599,6 +607,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
// Pre-indexed stores
@@ -613,6 +622,7 @@
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit
+ let Inst{27-25} = 0b000;
}
// Post-indexed loads
@@ -627,6 +637,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
+ let Inst{27-25} = 0b000;
}
class AI3ldshpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
@@ -639,6 +650,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
+ let Inst{27-25} = 0b000;
}
class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern>
@@ -651,6 +663,7 @@
let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
+ let Inst{27-25} = 0b000;
}
// Post-indexed stores
@@ -665,6 +678,7 @@
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit
+ let Inst{27-25} = 0b000;
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=75065&r1=75064&r2=75065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Jul 8 17:51:32 2009
@@ -91,24 +91,44 @@
def VLDMD : NI<(outs),
(ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
"vldm${addr:submode} ${addr:base}, $dst1",
- []>;
+ []> {
+ let Inst{27-25} = 0b110;
+ let Inst{20} = 1;
+ let Inst{11-9} = 0b101;
+}
def VLDMS : NI<(outs),
(ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
"vldm${addr:submode} ${addr:base}, $dst1",
- []>;
+ []> {
+ let Inst{27-25} = 0b110;
+ let Inst{20} = 1;
+ let Inst{11-9} = 0b101;
+}
}
*/
// Use vldmia to load a Q register as a D register pair.
def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
"vldmia $addr, ${dst:dregpair}",
- [(set QPR:$dst, (v2f64 (load GPR:$addr)))]>;
+ [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
+ let Inst{27-25} = 0b110;
+ let Inst{24} = 0; // P bit
+ let Inst{23} = 1; // U bit
+ let Inst{20} = 1;
+ let Inst{11-9} = 0b101;
+}
// Use vstmia to store a Q register as a D register pair.
def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
"vstmia $addr, ${src:dregpair}",
- [(store (v2f64 QPR:$src), GPR:$addr)]>;
+ [(store (v2f64 QPR:$src), GPR:$addr)]> {
+ let Inst{27-25} = 0b110;
+ let Inst{24} = 0; // P bit
+ let Inst{23} = 1; // U bit
+ let Inst{20} = 0;
+ let Inst{11-9} = 0b101;
+}
// VLD1 : Vector Load (multiple single elements)
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