[llvm-commits] [llvm] r74427 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td include/llvm/Intrinsics.td lib/Target/X86/X86ISelLowering.cpp lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp
David Greene
greened at obbligato.org
Mon Jun 29 09:47:30 PDT 2009
Author: greened
Date: Mon Jun 29 11:47:10 2009
New Revision: 74427
URL: http://llvm.org/viewvc/llvm-project?rev=74427&view=rev
Log:
Add more vector ValueTypes for AVX and other extended vector instruction
sets.
Modified:
llvm/trunk/include/llvm/CodeGen/ValueTypes.h
llvm/trunk/include/llvm/CodeGen/ValueTypes.td
llvm/trunk/include/llvm/Intrinsics.td
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/VMCore/ValueTypes.cpp
llvm/trunk/utils/TableGen/CodeGenTarget.cpp
Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=74427&r1=74426&r2=74427&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Mon Jun 29 11:47:10 2009
@@ -52,29 +52,34 @@
v2i8 = 14, // 2 x i8
v4i8 = 15, // 4 x i8
- v2i16 = 16, // 2 x i16
- v8i8 = 17, // 8 x i8
- v4i16 = 18, // 4 x i16
- v2i32 = 19, // 2 x i32
- v1i64 = 20, // 1 x i64
- v16i8 = 21, // 16 x i8
- v8i16 = 22, // 8 x i16
- v3i32 = 23, // 3 x i32
- v4i32 = 24, // 4 x i32
- v2i64 = 25, // 2 x i64
-
- v2f32 = 26, // 2 x f32
- v3f32 = 27, // 3 x f32
- v4f32 = 28, // 4 x f32
- v2f64 = 29, // 2 x f64
-
+ v8i8 = 16, // 8 x i8
+ v16i8 = 17, // 16 x i8
+ v32i8 = 18, // 32 x i8
+ v2i16 = 19, // 2 x i16
+ v4i16 = 20, // 4 x i16
+ v8i16 = 21, // 8 x i16
+ v16i16 = 22, // 16 x i16
+ v2i32 = 23, // 2 x i32
+ v3i32 = 24, // 3 x i32
+ v4i32 = 25, // 4 x i32
+ v8i32 = 26, // 8 x i32
+ v1i64 = 27, // 1 x i64
+ v2i64 = 28, // 2 x i64
+ v4i64 = 29, // 4 x i64
+
+ v2f32 = 30, // 2 x f32
+ v3f32 = 31, // 3 x f32
+ v4f32 = 32, // 4 x f32
+ v8f32 = 33, // 8 x f32
+ v2f64 = 34, // 2 x f64
+ v4f64 = 35, // 4 x f64
+
FIRST_VECTOR_VALUETYPE = v2i8,
- LAST_VECTOR_VALUETYPE = v2f64,
+ LAST_VECTOR_VALUETYPE = v4f64,
- LAST_VALUETYPE = 30, // This always remains at the end of the list.
+ LAST_VALUETYPE = 36, // This always remains at the end of the list.
// This is the current maximum for LAST_VALUETYPE.
- // Affects ValueTypeActions in TargetLowering.h.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
// This value must be a multiple of 32.
MAX_ALLOWED_VALUETYPE = 64,
@@ -179,28 +184,34 @@
if (NumElements == 4) return v4i8;
if (NumElements == 8) return v8i8;
if (NumElements == 16) return v16i8;
+ if (NumElements == 32) return v32i8;
break;
case i16:
if (NumElements == 2) return v2i16;
if (NumElements == 4) return v4i16;
if (NumElements == 8) return v8i16;
+ if (NumElements == 16) return v16i16;
break;
case i32:
if (NumElements == 2) return v2i32;
if (NumElements == 3) return v3i32;
if (NumElements == 4) return v4i32;
+ if (NumElements == 8) return v8i32;
break;
case i64:
if (NumElements == 1) return v1i64;
if (NumElements == 2) return v2i64;
+ if (NumElements == 4) return v4i64;
break;
case f32:
if (NumElements == 2) return v2f32;
if (NumElements == 3) return v3f32;
if (NumElements == 4) return v4f32;
+ if (NumElements == 8) return v8f32;
break;
case f64:
if (NumElements == 2) return v2f64;
+ if (NumElements == 4) return v4f64;
break;
}
return getExtendedVectorVT(VT, NumElements);
@@ -235,15 +246,15 @@
/// isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isFloatingPoint() const {
return isSimple() ?
- ((V >= f32 && V <= ppcf128) || (V >= v2f32 && V <= v2f64)) :
- isExtendedFloatingPoint();
+ ((V >= f32 && V <= ppcf128) ||
+ (V >= v2f32 && V <= v4f64)) : isExtendedFloatingPoint();
}
/// isInteger - Return true if this is an integer, or a vector integer type.
bool isInteger() const {
return isSimple() ?
((V >= FIRST_INTEGER_VALUETYPE && V <= LAST_INTEGER_VALUETYPE) ||
- (V >= v2i8 && V <= v2i64)) : isExtendedInteger();
+ (V >= v2i8 && V <= v4i64)) : isExtendedInteger();
}
/// isVector - Return true if this is a vector value type.
@@ -268,6 +279,13 @@
isExtended128BitVector();
}
+ /// is256BitVector - Return true if this is a 256-bit vector type.
+ inline bool is256BitVector() const {
+ return isSimple() ?
+ (V==v8f32 || V==v4f64 || V==v32i8 || V==v16i16 || V==v8i32 ||
+ V==v4i64) : isExtended256BitVector();
+ }
+
/// isByteSized - Return true if the bit size is a multiple of 8.
bool isByteSized() const {
return (getSizeInBits() & 7) == 0;
@@ -322,19 +340,25 @@
case v2i8 :
case v4i8 :
case v8i8 :
- case v16i8: return i8;
+ case v16i8:
+ case v32i8: return i8;
case v2i16:
case v4i16:
- case v8i16: return i16;
+ case v8i16:
+ case v16i16: return i16;
case v2i32:
case v3i32:
- case v4i32: return i32;
+ case v4i32:
+ case v8i32: return i32;
case v1i64:
- case v2i64: return i64;
+ case v2i64:
+ case v4i64: return i64;
case v2f32:
case v3f32:
- case v4f32: return f32;
- case v2f64: return f64;
+ case v4f32:
+ case v8f32: return f32;
+ case v2f64:
+ case v4f64: return f64;
}
}
@@ -345,13 +369,19 @@
switch (V) {
default:
return getExtendedVectorNumElements();
- case v16i8: return 16;
+ case v32i8: return 32;
+ case v16i8:
+ case v16i16: return 16;
case v8i8 :
- case v8i16: return 8;
+ case v8i16:
+ case v8i32:
+ case v8f32: return 8;
case v4i8:
case v4i16:
case v4i32:
- case v4f32: return 4;
+ case v4i64:
+ case v4f32:
+ case v4f64: return 4;
case v3i32:
case v3f32: return 3;
case v2i8:
@@ -402,6 +432,12 @@
case v2i64:
case v4f32:
case v2f64: return 128;
+ case v32i8:
+ case v16i16:
+ case v8i32:
+ case v4i64:
+ case v8f32:
+ case v4f64: return 256;
}
}
@@ -478,6 +514,7 @@
bool isExtendedVector() const;
bool isExtended64BitVector() const;
bool isExtended128BitVector() const;
+ bool isExtended256BitVector() const;
MVT getExtendedVectorElementType() const;
unsigned getExtendedVectorNumElements() const;
unsigned getExtendedSizeInBits() const;
Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.td?rev=74427&r1=74426&r2=74427&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ValueTypes.td (original)
+++ llvm/trunk/include/llvm/CodeGen/ValueTypes.td Mon Jun 29 11:47:10 2009
@@ -33,25 +33,31 @@
def ppcf128: ValueType<128, 11>; // PPC 128-bit floating point value
def FlagVT : ValueType<0 , 12>; // Condition code or machine flag
def isVoid : ValueType<0 , 13>; // Produces no value
+
def v2i8 : ValueType<16 , 14>; // 2 x i8 vector value
def v4i8 : ValueType<32 , 15>; // 4 x i8 vector value
-def v2i16 : ValueType<32 , 16>; // 2 x i16 vector value
-def v8i8 : ValueType<64 , 17>; // 8 x i8 vector value
-def v4i16 : ValueType<64 , 18>; // 4 x i16 vector value
-def v2i32 : ValueType<64 , 19>; // 2 x i32 vector value
-def v1i64 : ValueType<64 , 20>; // 1 x i64 vector value
-
-def v16i8 : ValueType<128, 21>; // 16 x i8 vector value
-def v8i16 : ValueType<128, 22>; // 8 x i16 vector value
-def v3i32 : ValueType<96 , 23>; // 3 x i32 vector value
-def v4i32 : ValueType<128, 24>; // 4 x i32 vector value
-def v2i64 : ValueType<128, 25>; // 2 x i64 vector value
-
-def v2f32 : ValueType<64, 26>; // 2 x f32 vector value
-def v3f32 : ValueType<96 , 27>; // 3 x f32 vector value
-def v4f32 : ValueType<128, 28>; // 4 x f32 vector value
-def v2f64 : ValueType<128, 29>; // 2 x f64 vector value
-
+def v8i8 : ValueType<64 , 16>; // 8 x i8 vector value
+def v16i8 : ValueType<128, 17>; // 16 x i8 vector value
+def v32i8 : ValueType<256, 18>; // 32 x i8 vector value
+def v2i16 : ValueType<32 , 19>; // 2 x i16 vector value
+def v4i16 : ValueType<64 , 20>; // 4 x i16 vector value
+def v8i16 : ValueType<128, 21>; // 8 x i16 vector value
+def v16i16 : ValueType<256, 22>; // 16 x i16 vector value
+def v2i32 : ValueType<64 , 23>; // 2 x i32 vector value
+def v3i32 : ValueType<96 , 24>; // 3 x i32 vector value
+def v4i32 : ValueType<128, 25>; // 4 x i32 vector value
+def v8i32 : ValueType<256, 26>; // 8 x f32 vector value
+def v1i64 : ValueType<64 , 27>; // 1 x i64 vector value
+def v2i64 : ValueType<128, 28>; // 2 x i64 vector value
+def v4i64 : ValueType<256, 29>; // 4 x f64 vector value
+
+def v2f32 : ValueType<64, 30>; // 2 x f32 vector value
+def v3f32 : ValueType<96 , 31>; // 3 x f32 vector value
+def v4f32 : ValueType<128, 32>; // 4 x f32 vector value
+def v8f32 : ValueType<256, 33>; // 8 x f32 vector value
+def v2f64 : ValueType<128, 34>; // 2 x f64 vector value
+def v4f64 : ValueType<256, 35>; // 4 x f64 vector value
+
// Pseudo valuetype mapped to the current pointer size to any address space.
// Should only be used in TableGen.
def iPTRAny : ValueType<0, 252>;
Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=74427&r1=74426&r2=74427&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Mon Jun 29 11:47:10 2009
@@ -110,22 +110,32 @@
def llvm_empty_ty : LLVMType<OtherVT>; // { }
def llvm_descriptor_ty : LLVMPointerType<llvm_empty_ty>; // { }*
+def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
+def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8
+def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8
+def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
+def llvm_v2i16_ty : LLVMType<v2i16>; // 4 x i16
+def llvm_v4i16_ty : LLVMType<v4i16>; // 4 x i16
def llvm_v8i16_ty : LLVMType<v8i16>; // 8 x i16
-def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
+def llvm_v16i16_ty : LLVMType<v16i16>; // 16 x i16
def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
-def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64
def llvm_v4i32_ty : LLVMType<v4i32>; // 4 x i32
+def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32
+def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64
+def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
+def llvm_v4i64_ty : LLVMType<v4i64>; // 4 x i64
+
def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float
+def llvm_v3f32_ty : LLVMType<v3f32>; // 3 x float
def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float
+def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float
def llvm_v2f64_ty : LLVMType<v2f64>; // 2 x double
-
-// MMX Vector Types
-def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
-def llvm_v4i16_ty : LLVMType<v4i16>; // 4 x i16
+def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double
def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
+
//===----------------------------------------------------------------------===//
// Intrinsic Definitions.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=74427&r1=74426&r2=74427&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 29 11:47:10 2009
@@ -700,6 +700,9 @@
// Do not attempt to custom lower non-power-of-2 vectors
if (!isPowerOf2_32(VT.getVectorNumElements()))
continue;
+ // Do not attempt to custom lower non-128-bit vectors
+ if (!VT.is128BitVector())
+ continue;
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
@@ -718,17 +721,23 @@
}
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
- for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
- setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
- AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
- setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
- AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
- setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
- AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
- setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
- AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
- setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
- AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
+ for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
+ MVT VT = (MVT::SimpleValueType)i;
+
+ // Do not attempt to promote non-128-bit vectors
+ if (!VT.is128BitVector()) {
+ continue;
+ }
+ setOperationAction(ISD::AND, VT, Promote);
+ AddPromotedToType (ISD::AND, VT, MVT::v2i64);
+ setOperationAction(ISD::OR, VT, Promote);
+ AddPromotedToType (ISD::OR, VT, MVT::v2i64);
+ setOperationAction(ISD::XOR, VT, Promote);
+ AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
+ setOperationAction(ISD::LOAD, VT, Promote);
+ AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
+ setOperationAction(ISD::SELECT, VT, Promote);
+ AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
}
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
@@ -775,6 +784,109 @@
setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
}
+ if (!UseSoftFloat && Subtarget->hasAVX()) {
+ setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
+ setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
+ setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
+ setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
+ setOperationAction(ISD::FADD, MVT::v8f32, Legal);
+ setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
+ setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
+ setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
+ setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
+ setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
+ //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
+ //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
+ //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
+ //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
+ //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
+
+ // Operations to consider commented out -v16i16 v32i8
+ //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
+ setOperationAction(ISD::ADD, MVT::v8i32, Custom);
+ setOperationAction(ISD::ADD, MVT::v4i64, Custom);
+ //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
+ //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
+ setOperationAction(ISD::SUB, MVT::v8i32, Custom);
+ setOperationAction(ISD::SUB, MVT::v4i64, Custom);
+ //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
+ setOperationAction(ISD::FADD, MVT::v4f64, Legal);
+ setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
+ setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
+ setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
+ setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
+ setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
+
+ setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
+ // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
+ // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
+ setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
+
+ // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
+ // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
+ // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
+
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
+
+#if 0
+ // Not sure we want to do this since there are no 256-bit integer
+ // operations in AVX
+
+ // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
+ // This includes 256-bit vectors
+ for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
+ MVT VT = (MVT::SimpleValueType)i;
+
+ // Do not attempt to custom lower non-power-of-2 vectors
+ if (!isPowerOf2_32(VT.getVectorNumElements()))
+ continue;
+
+ setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+ setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
+ }
+
+ if (Subtarget->is64Bit()) {
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
+ }
+#endif
+
+#if 0
+ // Not sure we want to do this since there are no 256-bit integer
+ // operations in AVX
+
+ // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
+ // Including 256-bit vectors
+ for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
+ MVT VT = (MVT::SimpleValueType)i;
+
+ if (!VT.is256BitVector()) {
+ continue;
+ }
+ setOperationAction(ISD::AND, VT, Promote);
+ AddPromotedToType (ISD::AND, VT, MVT::v4i64);
+ setOperationAction(ISD::OR, VT, Promote);
+ AddPromotedToType (ISD::OR, VT, MVT::v4i64);
+ setOperationAction(ISD::XOR, VT, Promote);
+ AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
+ setOperationAction(ISD::LOAD, VT, Promote);
+ AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
+ setOperationAction(ISD::SELECT, VT, Promote);
+ AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
+ }
+
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+#endif
+ }
+
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=74427&r1=74426&r2=74427&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ValueTypes.cpp (original)
+++ llvm/trunk/lib/VMCore/ValueTypes.cpp Mon Jun 29 11:47:10 2009
@@ -54,6 +54,10 @@
return isExtendedVector() && getSizeInBits() == 128;
}
+bool MVT::isExtended256BitVector() const {
+ return isExtendedVector() && getSizeInBits() == 256;
+}
+
MVT MVT::getExtendedVectorElementType() const {
assert(isExtended() && "Type is not extended!");
return MVT::getMVT(cast<VectorType>(LLVMTy)->getElementType());
@@ -101,20 +105,26 @@
case MVT::Flag: return "flag";
case MVT::v2i8: return "v2i8";
case MVT::v4i8: return "v4i8";
- case MVT::v2i16: return "v2i16";
case MVT::v8i8: return "v8i8";
- case MVT::v4i16: return "v4i16";
- case MVT::v2i32: return "v2i32";
- case MVT::v1i64: return "v1i64";
case MVT::v16i8: return "v16i8";
+ case MVT::v32i8: return "v32i8";
+ case MVT::v2i16: return "v2i16";
+ case MVT::v4i16: return "v4i16";
case MVT::v8i16: return "v8i16";
+ case MVT::v16i16: return "v16i16";
+ case MVT::v2i32: return "v2i32";
+ case MVT::v3i32: return "v3i32";
case MVT::v4i32: return "v4i32";
+ case MVT::v8i32: return "v8i32";
+ case MVT::v1i64: return "v1i64";
case MVT::v2i64: return "v2i64";
+ case MVT::v4i64: return "v4i64";
case MVT::v2f32: return "v2f32";
+ case MVT::v3f32: return "v3f32";
case MVT::v4f32: return "v4f32";
+ case MVT::v8f32: return "v8f32";
case MVT::v2f64: return "v2f64";
- case MVT::v3i32: return "v3i32";
- case MVT::v3f32: return "v3f32";
+ case MVT::v4f64: return "v4f64";
}
}
@@ -140,21 +150,27 @@
case MVT::ppcf128: return Type::PPC_FP128Ty;
case MVT::v2i8: return VectorType::get(Type::Int8Ty, 2);
case MVT::v4i8: return VectorType::get(Type::Int8Ty, 4);
- case MVT::v2i16: return VectorType::get(Type::Int16Ty, 2);
case MVT::v8i8: return VectorType::get(Type::Int8Ty, 8);
+ case MVT::v16i8: return VectorType::get(Type::Int8Ty, 16);
+ case MVT::v32i8: return VectorType::get(Type::Int8Ty, 32);
+ case MVT::v2i16: return VectorType::get(Type::Int16Ty, 2);
case MVT::v4i16: return VectorType::get(Type::Int16Ty, 4);
+ case MVT::v8i16: return VectorType::get(Type::Int16Ty, 16);
+ case MVT::v16i16: return VectorType::get(Type::Int16Ty, 8);
case MVT::v2i32: return VectorType::get(Type::Int32Ty, 2);
- case MVT::v1i64: return VectorType::get(Type::Int64Ty, 1);
- case MVT::v16i8: return VectorType::get(Type::Int8Ty, 16);
- case MVT::v8i16: return VectorType::get(Type::Int16Ty, 8);
+ case MVT::v3i32: return VectorType::get(Type::Int32Ty, 3);
case MVT::v4i32: return VectorType::get(Type::Int32Ty, 4);
+ case MVT::v8i32: return VectorType::get(Type::Int32Ty, 8);
+ case MVT::v1i64: return VectorType::get(Type::Int64Ty, 1);
case MVT::v2i64: return VectorType::get(Type::Int64Ty, 2);
+ case MVT::v4i64: return VectorType::get(Type::Int64Ty, 4);
case MVT::v2f32: return VectorType::get(Type::FloatTy, 2);
+ case MVT::v3f32: return VectorType::get(Type::FloatTy, 3);
case MVT::v4f32: return VectorType::get(Type::FloatTy, 4);
+ case MVT::v8f32: return VectorType::get(Type::FloatTy, 8);
case MVT::v2f64: return VectorType::get(Type::DoubleTy, 2);
- case MVT::v3i32: return VectorType::get(Type::Int32Ty, 3);
- case MVT::v3f32: return VectorType::get(Type::FloatTy, 3);
- }
+ case MVT::v4f64: return VectorType::get(Type::DoubleTy, 4);
+ }
}
/// getMVT - Return the value type corresponding to the specified type. This
Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=74427&r1=74426&r2=74427&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 29 11:47:10 2009
@@ -53,18 +53,24 @@
case MVT::isVoid:return "MVT::isVoid";
case MVT::v2i8: return "MVT::v2i8";
case MVT::v4i8: return "MVT::v4i8";
- case MVT::v2i16: return "MVT::v2i16";
case MVT::v8i8: return "MVT::v8i8";
- case MVT::v4i16: return "MVT::v4i16";
- case MVT::v2i32: return "MVT::v2i32";
- case MVT::v1i64: return "MVT::v1i64";
case MVT::v16i8: return "MVT::v16i8";
+ case MVT::v32i8: return "MVT::v32i8";
+ case MVT::v2i16: return "MVT::v2i16";
+ case MVT::v4i16: return "MVT::v4i16";
case MVT::v8i16: return "MVT::v8i16";
+ case MVT::v16i16: return "MVT::v16i16";
+ case MVT::v2i32: return "MVT::v2i32";
case MVT::v4i32: return "MVT::v4i32";
+ case MVT::v8i32: return "MVT::v8i32";
+ case MVT::v1i64: return "MVT::v1i64";
case MVT::v2i64: return "MVT::v2i64";
+ case MVT::v4i64: return "MVT::v4i64";
case MVT::v2f32: return "MVT::v2f32";
case MVT::v4f32: return "MVT::v4f32";
+ case MVT::v8f32: return "MVT::v8f32";
case MVT::v2f64: return "MVT::v2f64";
+ case MVT::v4f64: return "MVT::v4f64";
case MVT::v3i32: return "MVT::v3i32";
case MVT::v3f32: return "MVT::v3f32";
case MVT::iPTR: return "TLI.getPointerTy()";
@@ -93,18 +99,24 @@
case MVT::isVoid:return "MVT::isVoid";
case MVT::v2i8: return "MVT::v2i8";
case MVT::v4i8: return "MVT::v4i8";
- case MVT::v2i16: return "MVT::v2i16";
case MVT::v8i8: return "MVT::v8i8";
- case MVT::v4i16: return "MVT::v4i16";
- case MVT::v2i32: return "MVT::v2i32";
- case MVT::v1i64: return "MVT::v1i64";
case MVT::v16i8: return "MVT::v16i8";
+ case MVT::v32i8: return "MVT::v32i8";
+ case MVT::v2i16: return "MVT::v2i16";
+ case MVT::v4i16: return "MVT::v4i16";
case MVT::v8i16: return "MVT::v8i16";
+ case MVT::v16i16: return "MVT::v16i16";
+ case MVT::v2i32: return "MVT::v2i32";
case MVT::v4i32: return "MVT::v4i32";
+ case MVT::v8i32: return "MVT::v8i32";
+ case MVT::v1i64: return "MVT::v1i64";
case MVT::v2i64: return "MVT::v2i64";
+ case MVT::v4i64: return "MVT::v4i64";
case MVT::v2f32: return "MVT::v2f32";
case MVT::v4f32: return "MVT::v4f32";
+ case MVT::v8f32: return "MVT::v8f32";
case MVT::v2f64: return "MVT::v2f64";
+ case MVT::v4f64: return "MVT::v4f64";
case MVT::v3i32: return "MVT::v3i32";
case MVT::v3f32: return "MVT::v3f32";
case MVT::iPTR: return "MVT::iPTR";
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