[llvm-commits] [llvm] r73095 - in /llvm/trunk: include/llvm/Target/TargetMachine.h include/llvm/Target/TargetOptions.h lib/Target/ARM/ARMCallingConv.td lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMRegisterInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/TargetMachine.cpp lib/Target/X86/X86Subtarget.cpp
Evan Cheng
evan.cheng at apple.com
Wed Jun 10 21:43:22 PDT 2009
On Jun 8, 2009, at 3:53 PM, Anton Korobeynikov wrote:
> Author: asl
> Date: Mon Jun 8 17:53:56 2009
> New Revision: 73095
>
> URL: http://llvm.org/viewvc/llvm-project?rev=73095&view=rev
> Log:
> The attached patches implement most of the ARM AAPCS-VFP hard float
> ABI. The missing piece is support for putting "homogeneous aggregates"
> into registers.
>
> Patch by Sandeep Patel!
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetMachine.h
> llvm/trunk/include/llvm/Target/TargetOptions.h
> llvm/trunk/lib/Target/ARM/ARMCallingConv.td
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
> llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> llvm/trunk/lib/Target/TargetMachine.cpp
> llvm/trunk/lib/Target/X86/X86Subtarget.cpp
>
> Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Jun 8
> 17:53:56 2009
> @@ -78,6 +78,14 @@
> };
> }
>
>
> +namespace FloatABI {
> + enum ABIType {
> + Default,
> + Soft,
> + Hard
> + };
> +}
Some comments?
>
> +
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> ///
> /// TargetMachine - Primary interface to the complete machine
> description for
> @@ -88,7 +96,7 @@
> TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
> void operator=(const TargetMachine &); // DO NOT IMPLEMENT
> protected: // Can only create subclasses.
> - TargetMachine() : AsmInfo(0) { }
> + TargetMachine();
>
> /// getSubtargetImpl - virtual method implemented by subclasses
> that returns
> /// a reference to that target's TargetSubtarget-derived member
> variable.
>
> Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon Jun 8
> 17:53:56 2009
> @@ -73,6 +73,14 @@
> /// target FP instructions.
> extern bool UseSoftFloat;
>
> + /// FloatABIType - This setting is set by -float-abi=xxx option
> is specfied
> + /// on the command line. This setting may either be Default,
> Soft, or Hard.
> + /// Default selects the target's default behavior. Soft selects
> the ABI for
> + /// UseSoftFloat, but does not inidcate that FP hardware may not
> be used.
> + /// Such a combination is unfortunately popular (e.g. arm-apple-
> darwin).
> + /// Hard presumes that the normal FP ABI is used.
> + extern FloatABI::ABIType FloatABIType;
Can we add a module note for this?
Evan
>
> +
> /// NoZerosInBSS - By default some codegens place zero-initialized
> data to
> /// .bss section. This flag disables such behaviour (necessary,
> e.g. for
> /// crt*.o compiling).
>
> Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.td?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCallingConv.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.td Mon Jun 8 17:53:56
> 2009
> @@ -17,6 +17,11 @@
> class CCIfAlign<string Align, CCAction A>:
> CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
>
> +/// CCIfFloatABI - Match of the float ABI and the arg. ABIType may
> be "Hard" or
> +/// "Soft".
> +class CCIfFloatABI<string ABIType, CCAction A>:
> + CCIf<!strconcat("llvm::FloatABIType == llvm::FloatABI::",
> ABIType), A>;
> +
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> // ARM APCS Calling Convention
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> @@ -43,9 +48,10 @@
> ]>;
>
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> -// ARM AAPCS (EABI) Calling Convention
> +// ARM AAPCS (EABI) Calling Convention, common parts
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> -def CC_ARM_AAPCS : CallingConv<[
> +
> +def CC_ARM_AAPCS_Common : CallingConv<[
>
> CCIfType<[i8, i16], CCPromoteToType<i32>>,
>
> @@ -53,23 +59,51 @@
> // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad
> register
> // (and the same is true for f64 if VFP is not enabled)
> CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2],
> [R0, R1]>>>,
> - CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
> -
> - CCIfType<[f32], CCBitConvertToType<i32>>,
> CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
> "ArgFlags.getOrigAlign() != 8",
> CCAssignToReg<[R0, R1, R2, R3]>>>,
>
> - CCIfType<[i32], CCAssignToStack<4, 4>>,
> + CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
> CCIfType<[f64], CCAssignToStack<8, 8>>
> ]>;
>
> -def RetCC_ARM_AAPCS : CallingConv<[
> +def RetCC_ARM_AAPCS_Common : CallingConv<[
> + CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>
> + CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
> +]>;
> +
> +//
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> +// ARM AAPCS (EABI) Calling Convention
> +//
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> +
> +def CC_ARM_AAPCS : CallingConv<[
> + CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
> CCIfType<[f32], CCBitConvertToType<i32>>,
> + CCDelegateTo<CC_ARM_AAPCS_Common>
> +]>;
> +
> +def RetCC_ARM_AAPCS : CallingConv<[
> CCIfType<[f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
> + CCIfType<[f32], CCBitConvertToType<i32>>,
> + CCDelegateTo<RetCC_ARM_AAPCS_Common>
> +]>;
>
> - CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
> - CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
> +//
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> +// ARM AAPCS-VFP (EABI) Calling Convention
> +//
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> +
> +def CC_ARM_AAPCS_VFP : CallingConv<[
> + CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
> + CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
> + S9, S10, S11, S12, S13, S14, S15]>>,
> + CCDelegateTo<CC_ARM_AAPCS_Common>
> +]>;
> +
> +def RetCC_ARM_AAPCS_VFP : CallingConv<[
> + CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
> + CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
> + S9, S10, S11, S12, S13, S14, S15]>>,
> + CCDelegateTo<RetCC_ARM_AAPCS_Common>
> ]>;
>
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> @@ -77,11 +111,19 @@
> //
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
>
> def CC_ARM : CallingConv<[
> + CCIfSubtarget<"isAAPCS_ABI()",
> + CCIfSubtarget<"hasVFP2()",
> + CCIfFloatABI<"Hard",
> +
> CCDelegateTo<CC_ARM_AAPCS_VFP>>>>,
> CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo<CC_ARM_AAPCS>>,
> CCDelegateTo<CC_ARM_APCS>
> ]>;
>
> def RetCC_ARM : CallingConv<[
> + CCIfSubtarget<"isAAPCS_ABI()",
> + CCIfSubtarget<"hasVFP2()",
> + CCIfFloatABI<"Hard",
> +
> CCDelegateTo<RetCC_ARM_AAPCS_VFP>>>>,
> CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo<RetCC_ARM_AAPCS>>,
> CCDelegateTo<RetCC_ARM_APCS>
> ]>;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Jun 8
> 17:53:56 2009
> @@ -549,6 +549,10 @@
> switch (N->getOpcode()) {
> default: break;
> case ISD::Constant: {
> + // ARMv6T2 and later should materialize imms via MOV / MOVT pair.
> + if (Subtarget->hasV6T2Ops())
> + break;
> +
> unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
> bool UseCP = true;
> if (Subtarget->isThumb())
> @@ -559,6 +563,7 @@
> UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
> ARM_AM::getSOImmVal(~Val) == -1 && // MVN
> !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
> +
> if (UseCP) {
> SDValue CPIdx =
> CurDAG-
> >getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
> @@ -570,7 +575,7 @@
> CPIdx, CurDAG-
> >getEntryNode());
> else {
> SDValue Ops[] = {
> - CPIdx,
> + CPIdx,
> CurDAG->getRegister(0, MVT::i32),
> CurDAG->getTargetConstant(0, MVT::i32),
> getAL(CurDAG),
> @@ -583,7 +588,7 @@
> ReplaceUses(Op, SDValue(ResNode, 0));
> return NULL;
> }
> -
> +
> // Other cases are autogenerated.
> break;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jun 8
> 17:53:56 2009
> @@ -1101,7 +1101,12 @@
> else
> RC = ARM::GPRRegisterClass;
>
> - if (RegVT == MVT::f64) {
> + if (FloatABIType == FloatABI::Hard) {
> + if (RegVT == MVT::f32)
> + RC = ARM::SPRRegisterClass;
> + else if (RegVT == MVT::f64)
> + RC = ARM::DPRRegisterClass;
> + } else if (RegVT == MVT::f64) {
> // f64 is passed in pairs of GPRs and must be combined.
> RegVT = MVT::i32;
> } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32)))
>
> Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Mon Jun 8 17:53:56
> 2009
> @@ -219,3 +219,18 @@
>
> // Condition code registers.
> def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
> +
> +//
> =
> =
> =
> ----------------------------------------------------------------------=
> ==//
> +// Subregister Set Definitions... now that we have all of the
> pieces, define the
> +// sub registers for each register.
> +//
> +
> +def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
> + D8, D9, D10, D11, D12, D13, D14, D15],
> + [S0, S2, S4, S6, S8, S10, S12, S14,
> + S16, S18, S20, S22, S24, S26, S28, S30]>;
> +
> +def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7,
> + D8, D9, D10, D11, D12, D13, D14, D15],
> + [S1, S3, S5, S7, S9, S11, S13, S15,
> + S17, S19, S21, S23, S25, S27, S29, S31]>;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Jun 8 17:53:56
> 2009
> @@ -14,6 +14,8 @@
> #include "ARMSubtarget.h"
> #include "ARMGenSubtarget.inc"
> #include "llvm/Module.h"
> +#include "llvm/Target/TargetMachine.h"
> +#include "llvm/Target/TargetOptions.h"
> using namespace llvm;
>
> ARMSubtarget::ARMSubtarget(const Module &M, const std::string &FS,
> @@ -28,6 +30,10 @@
> , CPUString("generic")
> , TargetType(isELF) // Default to ELF unless otherwise specified.
> , TargetABI(ARM_ABI_APCS) {
> + // default to soft float ABI
> + if (FloatABIType == FloatABI::Default)
> + FloatABIType = FloatABI::Soft;
> +
> // Determine default and user specified characteristics
>
> // Parse features string.
>
> Modified: llvm/trunk/lib/Target/TargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/TargetMachine.cpp (original)
> +++ llvm/trunk/lib/Target/TargetMachine.cpp Mon Jun 8 17:53:56 2009
> @@ -30,6 +30,7 @@
> bool FiniteOnlyFPMathOption;
> bool HonorSignDependentRoundingFPMathOption;
> bool UseSoftFloat;
> + FloatABI::ABIType FloatABIType;
> bool NoImplicitFloat;
> bool NoZerosInBSS;
> bool ExceptionHandling;
> @@ -84,6 +85,19 @@
> cl::desc("Generate software floating point library calls"),
> cl::location(UseSoftFloat),
> cl::init(false));
> +static cl::opt<llvm::FloatABI::ABIType, true>
> +FloatABIForCalls("float-abi",
> + cl::desc("Choose float ABI type"),
> + cl::location(FloatABIType),
> + cl::init(FloatABI::Default),
> + cl::values(
> + clEnumValN(FloatABI::Default, "default",
> + "Target default float ABI type"),
> + clEnumValN(FloatABI::Soft, "soft",
> + "Soft float ABI (implied by -soft-float)"),
> + clEnumValN(FloatABI::Hard, "hard",
> + "Hard float ABI (uses FP registers)"),
> + clEnumValEnd));
> static cl::opt<bool, true>
> DontPlaceZerosInBSS("nozero-initialized-in-bss",
> cl::desc("Don't place zero-initialized symbols into bss section"),
> @@ -162,6 +176,14 @@
> // TargetMachine Class
> //
>
> +TargetMachine::TargetMachine()
> + : AsmInfo(0) {
> + // Typically it will be subtargets that will adjust FloatABIType
> from Default
> + // to Soft or Hard.
> + if (UseSoftFloat)
> + FloatABIType = FloatABI::Soft;
> +}
> +
> TargetMachine::~TargetMachine() {
> delete AsmInfo;
> }
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=73095&r1=73094&r2=73095&view=diff
>
> =
> =
> =
> =
> =
> =
> =
> =
> ======================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Jun 8 17:53:56
> 2009
> @@ -350,6 +350,10 @@
> , MaxInlineSizeThreshold(128)
> , Is64Bit(is64Bit)
> , TargetType(isELF) { // Default to ELF unless otherwise specified.
> +
> + // default to hard float ABI
> + if (FloatABIType == FloatABI::Default)
> + FloatABIType = FloatABI::Hard;
>
> // Determine default and user specified characteristics
> if (!FS.empty()) {
>
>
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