[llvm-commits] [llvm-gcc-4.2] r73073 - in /llvm-gcc-4.2/trunk/gcc/config/arm: arm-cores.def arm-tune.md arm.c arm.h
Anton Korobeynikov
asl at math.spbu.ru
Mon Jun 8 09:59:02 PDT 2009
Author: asl
Date: Mon Jun 8 11:58:58 2009
New Revision: 73073
URL: http://llvm.org/viewvc/llvm-project?rev=73073&view=rev
Log:
Add helpers to propagate ARMv6t2, ARMv7 stuff to llvm backends.
Modified:
llvm-gcc-4.2/trunk/gcc/config/arm/arm-cores.def
llvm-gcc-4.2/trunk/gcc/config/arm/arm-tune.md
llvm-gcc-4.2/trunk/gcc/config/arm/arm.c
llvm-gcc-4.2/trunk/gcc/config/arm/arm.h
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm-cores.def
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm-cores.def?rev=73073&r1=73072&r2=73073&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/arm-cores.def (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/arm-cores.def Mon Jun 8 11:58:58 2009
@@ -115,3 +115,9 @@
ARM_CORE("arm1176jzf-s", arm1176jzfs, 6ZK, FL_LDSCHED | FL_VFPV2, 9e)
ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e)
ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e)
+/* LLVM LOCAL begin */
+ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, 9e)
+ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, 9e)
+ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e)
+ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e)
+/* LLVM LOCAL end */
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm-tune.md
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm-tune.md?rev=73073&r1=73072&r2=73073&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/arm-tune.md (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/arm-tune.md Mon Jun 8 11:58:58 2009
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from arm-cores.def
(define_attr "tune"
- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore"
+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa8,cortexa9"
(const (symbol_ref "arm_tune")))
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.c?rev=73073&r1=73072&r2=73073&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/arm.c (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.c Mon Jun 8 11:58:58 2009
@@ -538,6 +538,9 @@
#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
Note: ARM6 & 7 derivatives only. */
#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
+/* LLVM LOCAL begin */
+#define FL_THUMB2 (1 << 16) /* Thumb-2. */
+/* LLVM LOCAL end */
#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
@@ -556,6 +559,10 @@
#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
#define FL_FOR_ARCH6Z FL_FOR_ARCH6
#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
+/* LLVM LOCAL begin */
+#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
+#define FL_FOR_ARCH7A (FL_FOR_ARCH6T2)
+/* LLVM LOCAL end */
/* The bits in this mask specify which
instructions we are allowed to generate. */
@@ -621,6 +628,11 @@
interworking clean. */
int arm_cpp_interwork = 0;
+/* LLVM LOCAL begin */
+/* Nonzero if chip supports Thumb 2. */
+int arm_arch_thumb2;
+/* LLVM LOCAL end */
+
/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
must report the mode of the memory reference from PRINT_OPERAND to
PRINT_OPERAND_ADDRESS. */
@@ -717,6 +729,10 @@
/* APPLE LOCAL end ARM custom architectures */
{"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
{"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
+/* LLVM LOCAL begin */
+ {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
+ {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
+/* LLVM LOCAL end */
{"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
{"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
{NULL, arm_none, NULL, 0 , NULL}
@@ -1369,6 +1385,9 @@
arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
arm_arch6 = (insn_flags & FL_ARCH6) != 0;
arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
+ /* LLVM LOCAL begin */
+ arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
+ /* LLVM LOCAL end */
arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=73073&r1=73072&r2=73073&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Mon Jun 8 11:58:58 2009
@@ -54,6 +54,10 @@
builtin_define ("__APCS_32__"); \
if (TARGET_THUMB) \
builtin_define ("__thumb__"); \
+ /* LLVM LOCAL begin */ \
+ if (TARGET_THUMB2) \
+ builtin_define ("__thumb2__"); \
+ /* LLVM LOCAL end */ \
\
if (TARGET_BIG_END) \
{ \
@@ -210,6 +214,15 @@
#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
+/* LLVM LOCAL begin */
+/* Only 16-bit thumb code. */
+#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
+/* Arm or Thumb-2 32-bit code. */
+#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
+/* 32-bit Thumb-2 code. */
+#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
+/* LLVM LOCAL end */
+
/* APPLE LOCAL begin ARM compact switch tables */
/* Use compact switch tables with libgcc handlers. */
#define TARGET_COMPACT_SWITCH_TABLES \
@@ -372,6 +385,11 @@
interworking clean. */
extern int arm_cpp_interwork;
+/* LLVM LOCAL begin */
+/* Nonzero if chip supports Thumb 2. */
+extern int arm_arch_thumb2;
+/* LLVM LOCAL end */
+
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APCS_FRAME)
#endif
@@ -2976,7 +2994,11 @@
case arm1176jzfs: F.setCPU("arm1176jzf-s"); break;\
case mpcorenovfp: F.setCPU("mpcorenovfp"); break;\
case mpcore: F.setCPU("mpcore"); break;\
- default: \
+ case arm1156t2s: F.setCPU("arm1156t2-s"); break; \
+ case arm1156t2fs: F.setCPU("arm1156t2f-s"); break; \
+ case cortexa8: F.setCPU("cortex-a8"); break; \
+ case cortexa9: F.setCPU("cortex-a9"); break; \
+ default: \
F.setCPU("arm7tdmi"); \
break; \
} \
@@ -2986,18 +3008,20 @@
* armv6-apple-darwin, thumbv5-apple-darwin. FIXME: Replace thumb triplets
* with function notes.
*/
-#define LLVM_OVERRIDE_TARGET_ARCH() \
- (TARGET_THUMB \
- ? (arm_arch6 \
- ? "thumbv6" : (arm_arch5e \
- ? "thumbv5e" : (arm_arch5 \
- ? "thumbv5" : (arm_arch4t \
- ? "thumbv4t" : "")))) \
- : (arm_arch6 \
- ? "armv6" : (arm_arch5e \
- ? "armv5e" : (arm_arch5 \
- ? "armv5" : (arm_arch4t \
- ? "armv4t" : "")))))
+#define LLVM_OVERRIDE_TARGET_ARCH() \
+ (TARGET_THUMB \
+ ? (arm_arch_thumb2 \
+ ? "thumbv6t2" : \
+ (arm_arch6 \
+ ? "thumbv6" : (arm_arch5e \
+ ? "thumbv5e" : (arm_arch5 \
+ ? "thumbv5" : (arm_arch4t \
+ ? "thumbv4t" : ""))))) \
+ : (arm_arch6 \
+ ? "armv6" : (arm_arch5e \
+ ? "armv5e" : (arm_arch5 \
+ ? "armv5" : (arm_arch4t \
+ ? "armv4t" : "")))))
#define LLVM_SET_MACHINE_OPTIONS(argvec) \
if (TARGET_SOFT_FLOAT) \
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