[llvm-commits] [llvm] r71078 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Duncan Sands]

Author: baldrick
Date: Wed May  6 06:29:50 2009
New Revision: 71078

URL: http://llvm.org/viewvc/llvm-project?rev=71078&view=rev
Log:
Add generic expansion of SUB when ADD and XOR
are legal.  Based on a patch by Micah Villmow.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=71078&r1=71077&r2=71078&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed May  6 06:29:50 2009
@@ -3268,8 +3268,7 @@
           OpToUse = ISD::UMUL_LOHI;
         }
         if (OpToUse) {
-          Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
-                           0);
+          Result = DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2);
           break;
         }
       }
@@ -3289,16 +3288,21 @@
       }
       if (Node->getOpcode() == ISD::SDIV &&
           TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
-                                     VTs, Tmp1, Tmp2).getNode(),
-                         0);
+        Result = DAG.getNode(ISD::SDIVREM, dl, VTs, Tmp1, Tmp2);
         break;
       }
       if (Node->getOpcode() == ISD::UDIV &&
           TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
-                                     VTs, Tmp1, Tmp2).getNode(),
-                         0);
+        Result = DAG.getNode(ISD::UDIVREM, dl, VTs, Tmp1, Tmp2);
+        break;
+      }
+      if (Node->getOpcode() == ISD::SUB &&
+          TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
+          TLI.isOperationLegalOrCustom(ISD::XOR, VT)) {
+        Tmp2 = DAG.getNode(ISD::XOR, dl, VT, Tmp2,
+               DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
+        Tmp2 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
+        Result = DAG.getNode(ISD::ADD, dl, VT, Tmp1, Tmp2);
         break;
       }