[llvm-commits] [PATCH] Add GR8_H register class to X86 backend

[Jakob Stoklund Olesen]

X86RegisterInfo.td declares these register classes:

def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
}

def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
   let SubRegClassList = [GR8_, GR8_];
}

The SubRegClassList asserts that EXTRACT_SUBREG GR16_, 2 yields a GR8_  
register. This is inconsistent with the actual SubRegSet:

def : SubRegSet<2, [AX, CX, DX, BX],
                    [AH, CH, DH, BH]>;

The SubRegClassList is currently only used by  
ScheduleDAGSDNodesEmit.cpp to determine the register class of virtual  
registers defined by EXTRACT_SUBREG. If these badly classed virtual  
registers survive register coalescing, they cause unnecessary copies  
in the LowerSubregs pass.

The attached patch replaces the GR8_ register class with two register  
classes: GR8_L and GR8_H, corresponding to the low and high halves of  
the GR16_ registers.

The patch passes "make check".

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