[llvm-commits] [llvm] r68666 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Dan Gohman]

Author: djg
Date: Wed Apr  8 21:06:09 2009
New Revision: 68666

URL: http://llvm.org/viewvc/llvm-project?rev=68666&view=rev
Log:
Fix grammaros in comments.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=68666&r1=68665&r2=68666&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr  8 21:06:09 2009
@@ -7264,12 +7264,12 @@
 }
 
 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
-  // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
   return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
 }
 
 bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
-  // x86-64 has implicitly zero-extends 32-bit results in 64-bit registers.
+  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
   return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
 }