[llvm-commits] [llvm] r66922 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/tls13.ll test/CodeGen/X86/tls14.ll

[Rafael Espindola]

> I think I will try the idea of always lowering to (load gs:0) + ADDR
> and then implementing some instruction folding after Select. I assume
> that is possible, right?

The attached patch does that. I like it a lot more. All that was
needed to get performance back was a small change to MatchAddress to
handle a load inside a load.

The only possible issue is that now we produce

movl    $i at NTPOFF, %eax
addl    %gs:0, %eax

Instead of

movl       %gs:0, %eax
leal       i at NTPOFF(%eax), %eax

I don't have enough experience with X86 to know which one is best.

What do you think of the current approach?

Thanks,
-- 
Rafael Avila de Espindola

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