[llvm-commits] [llvm] r68123 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp test/CodeGen/X86/live-out-reg-info.ll

[Bill Wendling]

Author: void
Date: Tue Mar 31 13:18:28 2009
New Revision: 68123

URL: http://llvm.org/viewvc/llvm-project?rev=68123&view=rev
Log:
--- Merging (from foreign repository) r68083 into '.':
A    test/CodeGen/X86/live-out-reg-info.ll
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Fix live-out reg logic to not insert over-aggressive AssertZExt
instructions. This fixes lua.

Added:
    llvm/branches/Apple/Dib/test/CodeGen/X86/live-out-reg-info.ll
Modified:
    llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=68123&r1=68122&r2=68123&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Tue Mar 31 13:18:28 2009
@@ -4587,15 +4587,15 @@
             isSExt = false, FromVT = MVT::i1;  // ASSERT ZEXT 1
           else if (NumSignBits > RegSize-8)
             isSExt = true, FromVT = MVT::i8;   // ASSERT SEXT 8
-          else if (NumZeroBits >= RegSize-9)
+          else if (NumZeroBits >= RegSize-8)
             isSExt = false, FromVT = MVT::i8;  // ASSERT ZEXT 8
           else if (NumSignBits > RegSize-16)
             isSExt = true, FromVT = MVT::i16;  // ASSERT SEXT 16
-          else if (NumZeroBits >= RegSize-17)
+          else if (NumZeroBits >= RegSize-16)
             isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
           else if (NumSignBits > RegSize-32)
             isSExt = true, FromVT = MVT::i32;  // ASSERT SEXT 32
-          else if (NumZeroBits >= RegSize-33)
+          else if (NumZeroBits >= RegSize-32)
             isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
 
           if (FromVT != MVT::Other) {

Added: llvm/branches/Apple/Dib/test/CodeGen/X86/live-out-reg-info.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/live-out-reg-info.ll?rev=68123&view=auto

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/live-out-reg-info.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/live-out-reg-info.ll Tue Mar 31 13:18:28 2009
@@ -0,0 +1,20 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | grep testl
+
+; Make sure dagcombine doesn't eliminate the comparison due
+; to an off-by-one bug with ComputeMaskedBits information.
+
+declare void @qux()
+
+define void @foo(i32 %a) {
+  %t0 = lshr i32 %a, 23
+  br label %next
+next:
+  %t1 = and i32 %t0, 256
+  %t2 = icmp eq i32 %t1, 0
+  br i1 %t2, label %true, label %false
+true:
+  call void @qux()
+  ret void
+false:
+  ret void
+}