[llvm-commits] DAGCombiner Patch: Allow targets to do combinefirst.

[Dan Gohman]

On Mar 25, 2009, at 6:46 AM, Sanjiv.Gupta at microchip.com wrote:
>
> Did you mean that we have a separate regclass posing mem bytes as regs
> and lower things after regalloc is done? We do not even have membyte  
> to
> membyte copy insn. Well, TBH, I did not quite understand it.

Here's a quick sketch of how this might work for an
accumulator-style architecture:

Tell instruction selection that there's an add instruction that
operates from registers, in addition to the one that takes an
operand from memory. Do this for all similar instructions. Run the
optimizer and codegen. Since there's only one physical register, any
time there are two distinct virtual registers being used by a single
instruction, one of them will need to be spilled, and the reload can
be folded into the instruction.

It would be worthwhile to see if anyone has done this kind of thing
before.

Dan