[llvm-commits] [llvm] r67704 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/ test/CodeGen/CellSPU/ test/CodeGen/X86/

Bill Wendling isanbard at gmail.com
Wed Mar 25 13:59:48 PDT 2009


Author: void
Date: Wed Mar 25 15:59:48 2009
New Revision: 67704

URL: http://llvm.org/viewvc/llvm-project?rev=67704&view=rev
Log:
--- Merging (from foreign repository) r67701 into '.':
U    test/CodeGen/X86/20090313-signext.ll
U    test/CodeGen/X86/split-eh-lpad-edges.ll
U    test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
U    test/CodeGen/X86/sext-trunc.ll
U    test/CodeGen/X86/const-select.ll
U    test/CodeGen/CellSPU/stores.ll
U    test/CodeGen/CellSPU/nand.ll
U    test/CodeGen/CellSPU/and_ops.ll
U    test/CodeGen/CellSPU/shift_ops.ll
U    test/CodeGen/CellSPU/or_ops.ll
U    test/CodeGen/CellSPU/eqv.ll
U    test/CodeGen/CellSPU/struct_1.ll
U    lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

Revert 67132. This is breaking some objective-c apps. Also fixes SDISel so it
*does not* force promote return value if the function is not marked signext /
zeroext.

--- Merging (from foreign repository) r67702 into '.':
A    test/CodeGen/X86/sext-ret-val.ll

Add a test case for PR3779: when to promote the function return value.

Added:
    llvm/branches/Apple/Dib/test/CodeGen/X86/sext-ret-val.ll
Modified:
    llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/branches/Apple/Dib/test/CodeGen/CellSPU/and_ops.ll
    llvm/branches/Apple/Dib/test/CodeGen/CellSPU/eqv.ll
    llvm/branches/Apple/Dib/test/CodeGen/CellSPU/nand.ll
    llvm/branches/Apple/Dib/test/CodeGen/CellSPU/or_ops.ll
    llvm/branches/Apple/Dib/test/CodeGen/CellSPU/shift_ops.ll
    llvm/branches/Apple/Dib/test/CodeGen/CellSPU/stores.ll
    llvm/branches/Apple/Dib/test/CodeGen/CellSPU/struct_1.ll
    llvm/branches/Apple/Dib/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
    llvm/branches/Apple/Dib/test/CodeGen/X86/20090313-signext.ll
    llvm/branches/Apple/Dib/test/CodeGen/X86/const-select.ll
    llvm/branches/Apple/Dib/test/CodeGen/X86/sext-trunc.ll
    llvm/branches/Apple/Dib/test/CodeGen/X86/split-eh-lpad-edges.ll

Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Wed Mar 25 15:59:48 2009
@@ -980,9 +980,6 @@
     for (unsigned j = 0, f = NumValues; j != f; ++j) {
       MVT VT = ValueVTs[j];
 
-      unsigned NumParts = TLI.getNumRegisters(VT);
-      MVT PartVT = TLI.getRegisterType(VT);
-      SmallVector<SDValue, 4> Parts(NumParts);
       ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
 
       const Function *F = I.getParent()->getParent();
@@ -991,6 +988,19 @@
       else if (F->paramHasAttr(0, Attribute::ZExt))
         ExtendKind = ISD::ZERO_EXTEND;
 
+      // FIXME: C calling convention requires the return type to be promoted to
+      // at least 32-bit. But this is not necessary for non-C calling
+      // conventions. The frontend should mark functions whose return values
+      // require promoting with signext or zeroext attributes.
+      if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
+        MVT MinVT = TLI.getRegisterType(MVT::i32);
+        if (VT.bitsLT(MinVT))
+          VT = MinVT;
+      }
+
+      unsigned NumParts = TLI.getNumRegisters(VT);
+      MVT PartVT = TLI.getRegisterType(VT);
+      SmallVector<SDValue, 4> Parts(NumParts);
       getCopyToParts(DAG, getCurDebugLoc(),
                      SDValue(RetOp.getNode(), RetOp.getResNo() + j),
                      &Parts[0], NumParts, PartVT, ExtendKind);

Modified: llvm/branches/Apple/Dib/test/CodeGen/CellSPU/and_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/CellSPU/and_ops.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/CellSPU/and_ops.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/CellSPU/and_ops.ll Wed Mar 25 15:59:48 2009
@@ -1,7 +1,7 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep and    %t1.s | count 230
+; RUN: grep and    %t1.s | count 234
 ; RUN: grep andc   %t1.s | count 85
-; RUN: grep andi   %t1.s | count 35
+; RUN: grep andi   %t1.s | count 37
 ; RUN: grep andhi  %t1.s | count 30
 ; RUN: grep andbi  %t1.s | count 4
 

Modified: llvm/branches/Apple/Dib/test/CodeGen/CellSPU/eqv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/CellSPU/eqv.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/CellSPU/eqv.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/CellSPU/eqv.ll Wed Mar 25 15:59:48 2009
@@ -1,5 +1,8 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep eqv  %t1.s | count 18
+; RUN: grep xshw %t1.s | count 6
+; RUN: grep xsbh %t1.s | count 3
+; RUN: grep andi %t1.s | count 3
 
 ; Test the 'eqv' instruction, whose boolean expression is:
 ; (a & b) | (~a & ~b), which simplifies to

Modified: llvm/branches/Apple/Dib/test/CodeGen/CellSPU/nand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/CellSPU/nand.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/CellSPU/nand.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/CellSPU/nand.ll Wed Mar 25 15:59:48 2009
@@ -1,6 +1,8 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep nand   %t1.s | count 90
-; RUN: grep and    %t1.s | count 90
+; RUN: grep and    %t1.s | count 94
+; RUN: grep xsbh   %t1.s | count 2
+; RUN: grep xshw   %t1.s | count 4
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
 

Modified: llvm/branches/Apple/Dib/test/CodeGen/CellSPU/or_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/CellSPU/or_ops.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/CellSPU/or_ops.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/CellSPU/or_ops.ll Wed Mar 25 15:59:48 2009
@@ -1,4 +1,5 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep and    %t1.s | count 2
 ; RUN: grep orc    %t1.s | count 85
 ; RUN: grep ori    %t1.s | count 30
 ; RUN: grep orhi   %t1.s | count 30

Modified: llvm/branches/Apple/Dib/test/CodeGen/CellSPU/shift_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/CellSPU/shift_ops.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/CellSPU/shift_ops.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/CellSPU/shift_ops.ll Wed Mar 25 15:59:48 2009
@@ -3,6 +3,8 @@
 ; RUN: grep {shlhi	}  %t1.s | count 3
 ; RUN: grep {shl	}  %t1.s | count 9
 ; RUN: grep {shli	}  %t1.s | count 3
+; RUN: grep {xshw	}  %t1.s | count 5
+; RUN: grep {and	}  %t1.s | count 5
 ; RUN: grep {andi	}  %t1.s | count 2
 ; RUN: grep {rotmi	}  %t1.s | count 2
 ; RUN: grep {rotqmbyi	}  %t1.s | count 1

Modified: llvm/branches/Apple/Dib/test/CodeGen/CellSPU/stores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/CellSPU/stores.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/CellSPU/stores.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/CellSPU/stores.ll Wed Mar 25 15:59:48 2009
@@ -6,13 +6,13 @@
 ; RUN: grep 771                 %t1.s | count 4
 ; RUN: grep 515                 %t1.s | count 2
 ; RUN: grep 1799                %t1.s | count 2
-; RUN: grep 1543                %t1.s | count 3
-; RUN: grep 1029                %t1.s | count 1
+; RUN: grep 1543                %t1.s | count 5
+; RUN: grep 1029                %t1.s | count 3
 ; RUN: grep {shli.*, 4}         %t1.s | count 4
 ; RUN: grep stqx                %t1.s | count 4
-; RUN: grep ilhu                %t1.s | count 9
-; RUN: grep iohl                %t1.s | count 6
-; RUN: grep shufb               %t1.s | count 13
+; RUN: grep ilhu                %t1.s | count 11
+; RUN: grep iohl                %t1.s | count 8
+; RUN: grep shufb               %t1.s | count 15
 ; RUN: grep frds                %t1.s | count 1
 
 ; ModuleID = 'stores.bc'

Modified: llvm/branches/Apple/Dib/test/CodeGen/CellSPU/struct_1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/CellSPU/struct_1.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/CellSPU/struct_1.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/CellSPU/struct_1.ll Wed Mar 25 15:59:48 2009
@@ -3,6 +3,8 @@
 ; RUN: grep lqa     %t1.s | count 5
 ; RUN: grep lqd     %t1.s | count 11
 ; RUN: grep rotqbyi %t1.s | count 7
+; RUN: grep xshw    %t1.s | count 1
+; RUN: grep andi    %t1.s | count 5
 ; RUN: grep cbd     %t1.s | count 3
 ; RUN: grep chd     %t1.s | count 1
 ; RUN: grep cwd     %t1.s | count 3
@@ -12,6 +14,8 @@
 ; RUN: grep ilhu    %t2.s | count 16
 ; RUN: grep lqd     %t2.s | count 16
 ; RUN: grep rotqbyi %t2.s | count 7
+; RUN: grep xshw    %t2.s | count 1
+; RUN: grep andi    %t2.s | count 5
 ; RUN: grep cbd     %t2.s | count 3
 ; RUN: grep chd     %t2.s | count 1
 ; RUN: grep cwd     %t2.s | count 3

Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll Wed Mar 25 15:59:48 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 | not grep {movsbl}
+; RUN: llvm-as < %s | llc -march=x86 | grep {movsbl}
 
 @X = global i32 0               ; <i32*> [#uses=1]
 

Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/20090313-signext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/20090313-signext.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/20090313-signext.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/20090313-signext.ll Wed Mar 25 15:59:48 2009
@@ -1,6 +1,7 @@
 ; RUN: llvm-as < %s | llc -march=x86-64 -relocation-model=pic > %t
 ; RUN: grep {movswl	%ax, %edi} %t
 ; RUN: grep {movw	(%rax), %ax} %t
+; XFAIL: *
 
 @x = common global i16 0
 

Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/const-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/const-select.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/const-select.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/const-select.ll Wed Mar 25 15:59:48 2009
@@ -10,7 +10,7 @@
 	ret float %iftmp.0.0
 }
 
-; RUN: llvm-as < %s | llc | grep {movb.*(%e.x,%e.x,4), %al}
+; RUN: llvm-as < %s | llc | grep {movsbl.*(%e.x,%e.x,4), %eax}
 define signext i8 @test(i8* nocapture %P, double %F) nounwind readonly {
 entry:
 	%0 = fcmp olt double %F, 4.200000e+01		; <i1> [#uses=1]

Added: llvm/branches/Apple/Dib/test/CodeGen/X86/sext-ret-val.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/sext-ret-val.ll?rev=67704&view=auto

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/sext-ret-val.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/sext-ret-val.ll Wed Mar 25 15:59:48 2009
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep movzbl | count 1
+; rdar://6699246
+
+define signext i8 @t1(i8* %A) nounwind readnone ssp {
+entry:
+        %0 = icmp ne i8* %A, null
+        %1 = zext i1 %0 to i8
+        ret i8 %1
+}
+
+define i8 @t2(i8* %A) nounwind readnone ssp {
+entry:
+        %0 = icmp ne i8* %A, null
+        %1 = zext i1 %0 to i8
+        ret i8 %1
+}

Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/sext-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/sext-trunc.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/sext-trunc.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/sext-trunc.ll Wed Mar 25 15:59:48 2009
@@ -1,6 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 > %t
-; RUN: grep movb %t
-; RUN: not grep movsbl %t
+; RUN: grep movsbl %t
 ; RUN: not grep movz %t
 ; RUN: not grep and %t
 

Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/split-eh-lpad-edges.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/split-eh-lpad-edges.ll?rev=67704&r1=67703&r2=67704&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/split-eh-lpad-edges.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/split-eh-lpad-edges.ll Wed Mar 25 15:59:48 2009
@@ -32,38 +32,3 @@
 }
 
 declare %struct.NSObject* @objc_msgSend(%struct.NSObject*, %struct.objc_selector*, ...)
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | not grep jmp
-; rdar://6647639
-; XFAIL: *
-
-	%struct.FetchPlanHeader = type { i8*, i8*, i32, i8*, i8*, i8*, i8*, i8*, %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)*, %struct.__attributeDescriptionFlags }
-	%struct.NSArray = type { %struct.NSObject }
-	%struct.NSAutoreleasePool = type { %struct.NSObject, i8*, i8*, i8*, i8* }
-	%struct.NSObject = type { %struct.NSObject* }
-	%struct.__attributeDescriptionFlags = type <{ i32 }>
-	%struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* }
-	%struct.objc_selector = type opaque
-@"\01l_objc_msgSend_fixup_alloc" = external global %struct._message_ref_t, align 16		; <%struct._message_ref_t*> [#uses=2]
-
-define %struct.NSArray* @newFetchedRowsForFetchPlan_MT(%struct.FetchPlanHeader* %fetchPlan, %struct.objc_selector* %selectionMethod, %struct.NSObject* %selectionParameter) ssp {
-entry:
-	%0 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc")
-			to label %invcont unwind label %lpad		; <%struct.NSObject*> [#uses=1]
-
-invcont:		; preds = %entry
-	%1 = invoke %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)* @objc_msgSend(%struct.NSObject* %0, %struct.objc_selector* null)
-			to label %invcont26 unwind label %lpad		; <%struct.NSObject*> [#uses=0]
-
-invcont26:		; preds = %invcont
-	%2 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc")
-			to label %invcont27 unwind label %lpad		; <%struct.NSObject*> [#uses=0]
-
-invcont27:		; preds = %invcont26
-	unreachable
-
-lpad:		; preds = %invcont26, %invcont, %entry
-	%pool.1 = phi %struct.NSAutoreleasePool* [ null, %entry ], [ null, %invcont ], [ null, %invcont26 ]		; <%struct.NSAutoreleasePool*> [#uses=0]
-	unreachable
-}
-
-declare %struct.NSObject* @objc_msgSend(%struct.NSObject*, %struct.objc_selector*, ...)





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