[llvm-commits] [llvm] r66917 - /llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp

[Bill Wendling]

Author: void
Date: Fri Mar 13 13:16:49 2009
New Revision: 66917

URL: http://llvm.org/viewvc/llvm-project?rev=66917&view=rev
Log:
--- Merging (from foreign repository) r66902 into '.':
U    lib/Target/X86/X86FastISel.cpp

generalize this code so that fast isel handles integer truncates to i1, which
codegen to the same thing as integer truncates to i8 (the top bits are 
just undefined).  This implements rdar://6667338

Modified:
    llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp

Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp?rev=66917&r1=66916&r2=66917&view=diff

==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp Fri Mar 13 13:16:49 2009
@@ -993,7 +993,9 @@
     return false;
   MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
   MVT DstVT = TLI.getValueType(I->getType());
-  if (DstVT != MVT::i8)
+  
+  // This code only handles truncation to byte right now.
+  if (DstVT != MVT::i8 && DstVT != MVT::i1)
     // All other cases should be handled by the tblgen generated code.
     return false;
   if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
@@ -1013,7 +1015,7 @@
   BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
 
   // Then issue an extract_subreg.
-  unsigned ResultReg = FastEmitInst_extractsubreg(DstVT.getSimpleVT(),
+  unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
                                                   CopyReg, X86::SUBREG_8BIT);
   if (!ResultReg)
     return false;