[llvm-commits] [llvm] r66676 - in /llvm/branches/Apple/Dib: include/llvm/CodeGen/ lib/CodeGen/ lib/CodeGen/SelectionDAG/
Dan Gohman
gohman at apple.com
Wed Mar 11 11:10:31 PDT 2009
Author: djg
Date: Wed Mar 11 13:10:31 2009
New Revision: 66676
URL: http://llvm.org/viewvc/llvm-project?rev=66676&view=rev
Log:
Merge from trunk:
r64288 | djg | 2009-02-10 20:27:20 -0800 (Tue, 10 Feb 2009) | 8 lines
When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
Modified:
llvm/branches/Apple/Dib/include/llvm/CodeGen/ScheduleDAG.h
llvm/branches/Apple/Dib/include/llvm/CodeGen/SchedulerRegistry.h
llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGISel.h
llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp
llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAG.cpp
llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGEmit.cpp
llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.h
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/ScheduleDAG.h?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/ScheduleDAG.h Wed Mar 11 13:10:31 2009
@@ -31,7 +31,6 @@
class MachineInstr;
class TargetRegisterInfo;
class ScheduleDAG;
- class SelectionDAG;
class SDNode;
class TargetInstrInfo;
class TargetInstrDesc;
@@ -426,10 +425,8 @@
class ScheduleDAG {
public:
- SelectionDAG *DAG; // DAG of the current basic block
- MachineBasicBlock *BB; // Current basic block
- MachineBasicBlock::iterator Begin; // The beginning of the range to be scheduled.
- MachineBasicBlock::iterator End; // The end of the range to be scheduled.
+ MachineBasicBlock *BB; // The block in which to insert instructions.
+ MachineBasicBlock::iterator InsertPos;// The position to insert instructions.
const TargetMachine &TM; // Target processor
const TargetInstrInfo *TII; // Target instruction information
const TargetRegisterInfo *TRI; // Target processor register info
@@ -452,12 +449,6 @@
///
void viewGraph();
- /// Run - perform scheduling.
- ///
- void Run(SelectionDAG *DAG, MachineBasicBlock *MBB,
- MachineBasicBlock::iterator Begin,
- MachineBasicBlock::iterator End);
-
/// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
/// according to the order specified in Sequence.
///
@@ -482,6 +473,10 @@
#endif
protected:
+ /// Run - perform scheduling.
+ ///
+ void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
+
/// BuildSchedGraph - Build SUnits and set up their Preds and Succs
/// to form the scheduling dependency graph.
///
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/SchedulerRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/SchedulerRegistry.h?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/SchedulerRegistry.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/SchedulerRegistry.h Wed Mar 11 13:10:31 2009
@@ -26,13 +26,13 @@
//===----------------------------------------------------------------------===//
class SelectionDAGISel;
-class ScheduleDAG;
+class ScheduleDAGSDNodes;
class SelectionDAG;
class MachineBasicBlock;
class RegisterScheduler : public MachinePassRegistryNode {
public:
- typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, bool);
+ typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, bool);
static MachinePassRegistry Registry;
@@ -63,28 +63,28 @@
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
-ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
- bool Fast);
+ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
+ bool Fast);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
-ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
- bool Fast);
+ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
+ bool Fast);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
-ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
- bool Fast);
+ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
+ bool Fast);
/// createFastDAGScheduler - This creates a "fast" scheduler.
///
-ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
- bool Fast);
+ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
+ bool Fast);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
-ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
- bool Fast);
+ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
+ bool Fast);
} // end namespace llvm
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGISel.h?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGISel.h Wed Mar 11 13:10:31 2009
@@ -35,7 +35,7 @@
class FunctionLoweringInfo;
class ScheduleHazardRecognizer;
class GCFunctionInfo;
- class ScheduleDAG;
+ class ScheduleDAGSDNodes;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
@@ -133,7 +133,7 @@
/// via the SchedulerRegistry, use it, otherwise select the
/// one preferred by the target.
///
- ScheduleDAG *CreateScheduler();
+ ScheduleDAGSDNodes *CreateScheduler();
};
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/PostRASchedulerList.cpp Wed Mar 11 13:10:31 2009
@@ -139,7 +139,7 @@
/// Observe - Update liveness information to account for the current
/// instruction, which will not be scheduled.
///
- void Observe(MachineInstr *MI);
+ void Observe(MachineInstr *MI, unsigned Count);
/// FinishBlock - Clean up register live-range state.
///
@@ -254,19 +254,26 @@
// Schedule each sequence of instructions not interrupted by a label
// or anything else that effectively needs to shut down scheduling.
MachineBasicBlock::iterator Current = MBB->end();
+ unsigned Count = MBB->size(), CurrentCount = Count;
for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
MachineInstr *MI = prior(I);
if (isSchedulingBoundary(MI, Fn)) {
if (I != Current) {
- Scheduler.Run(0, MBB, I, Current);
+ Scheduler.Run(MBB, I, Current, CurrentCount);
Scheduler.EmitSchedule();
}
- Scheduler.Observe(MI);
+ Scheduler.Observe(MI, Count);
Current = MI;
+ CurrentCount = Count - 1;
}
I = MI;
+ --Count;
+ }
+ assert(Count == 0 && "Instruction count mismatch!");
+ if (MBB->begin() != Current) {
+ assert(CurrentCount != 0 && "Instruction count mismatch!");
+ Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
}
- Scheduler.Run(0, MBB, MBB->begin(), Current);
Scheduler.EmitSchedule();
// Clean up register live-range state.
@@ -311,7 +318,7 @@
else
// In a non-return block, examine the live-in regs of all successors.
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
- SE = BB->succ_end(); SI != SE; ++SI)
+ SE = BB->succ_end(); SI != SE; ++SI)
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
E = (*SI)->livein_end(); I != E; ++I) {
unsigned Reg = *I;
@@ -384,9 +391,9 @@
/// Observe - Update liveness information to account for the current
/// instruction, which will not be scheduled.
///
-void SchedulePostRATDList::Observe(MachineInstr *MI) {
+void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
PrescanInstruction(MI);
- ScanInstruction(MI, 0);
+ ScanInstruction(MI, Count);
}
/// FinishBlock - Clean up register live-range state.
@@ -484,6 +491,9 @@
DefIndices[Reg] = Count;
KillIndices[Reg] = ~0u;
+ assert(((KillIndices[Reg] == ~0u) !=
+ (DefIndices[Reg] == ~0u)) &&
+ "Kill and Def maps aren't consistent for Reg!");
Classes[Reg] = 0;
RegRefs.erase(Reg);
// Repeat, for all subregs.
@@ -525,6 +535,9 @@
if (KillIndices[Reg] == ~0u) {
KillIndices[Reg] = Count;
DefIndices[Reg] = ~0u;
+ assert(((KillIndices[Reg] == ~0u) !=
+ (DefIndices[Reg] == ~0u)) &&
+ "Kill and Def maps aren't consistent for Reg!");
}
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
@@ -608,8 +621,8 @@
// instructions from the bottom up, tracking information about liveness
// as we go to help determine which registers are available.
bool Changed = false;
- unsigned Count = SUnits.size() - 1;
- for (MachineBasicBlock::iterator I = End, E = Begin;
+ unsigned Count = InsertPosIndex - 1;
+ for (MachineBasicBlock::iterator I = InsertPos, E = Begin;
I != E; --Count) {
MachineInstr *MI = --I;
@@ -739,10 +752,16 @@
Classes[NewReg] = Classes[AntiDepReg];
DefIndices[NewReg] = DefIndices[AntiDepReg];
KillIndices[NewReg] = KillIndices[AntiDepReg];
+ assert(((KillIndices[NewReg] == ~0u) !=
+ (DefIndices[NewReg] == ~0u)) &&
+ "Kill and Def maps aren't consistent for NewReg!");
Classes[AntiDepReg] = 0;
DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
KillIndices[AntiDepReg] = ~0u;
+ assert(((KillIndices[AntiDepReg] == ~0u) !=
+ (DefIndices[AntiDepReg] == ~0u)) &&
+ "Kill and Def maps aren't consistent for AntiDepReg!");
RegRefs.erase(AntiDepReg);
Changed = true;
@@ -754,7 +773,6 @@
ScanInstruction(MI, Count);
}
- assert(Count == ~0u && "Count mismatch!");
return Changed;
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAG.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAG.cpp Wed Mar 11 13:10:31 2009
@@ -23,7 +23,7 @@
using namespace llvm;
ScheduleDAG::ScheduleDAG(MachineFunction &mf)
- : DAG(0), BB(0), TM(mf.getTarget()),
+ : TM(mf.getTarget()),
TII(TM.getInstrInfo()),
TRI(TM.getRegisterInfo()),
TLI(TM.getTargetLowering()),
@@ -47,23 +47,18 @@
/// Run - perform scheduling.
///
-void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb,
- MachineBasicBlock::iterator begin,
- MachineBasicBlock::iterator end) {
- assert((!dag || begin == end) &&
- "An instruction range was given for SelectionDAG scheduling!");
+void ScheduleDAG::Run(MachineBasicBlock *bb,
+ MachineBasicBlock::iterator insertPos) {
+ BB = bb;
+ InsertPos = insertPos;
SUnits.clear();
Sequence.clear();
- DAG = dag;
- BB = bb;
- Begin = begin;
- End = end;
EntrySU = SUnit();
ExitSU = SUnit();
Schedule();
-
+
DOUT << "*** Final schedule ***\n";
DEBUG(dumpSchedule());
DOUT << "\n";
Modified: llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGEmit.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGEmit.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGEmit.cpp Wed Mar 11 13:10:31 2009
@@ -33,7 +33,7 @@
}
void ScheduleDAG::EmitNoop() {
- TII->insertNoop(*BB, End);
+ TII->insertNoop(*BB, InsertPos);
}
void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
@@ -54,7 +54,7 @@
break;
}
}
- TII->copyRegToReg(*BB, End, Reg, VRI->second,
+ TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second,
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
@@ -63,7 +63,7 @@
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
- TII->copyRegToReg(*BB, End, VRBase, I->getReg(),
+ TII->copyRegToReg(*BB, InsertPos, VRBase, I->getReg(),
SU->CopyDstRC, SU->CopySrcRC);
}
break;
Modified: llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Mar 11 13:10:31 2009
@@ -32,6 +32,19 @@
const MachineDominatorTree &mdt)
: ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {}
+/// Run - perform scheduling.
+///
+void ScheduleDAGInstrs::Run(MachineBasicBlock *bb,
+ MachineBasicBlock::iterator begin,
+ MachineBasicBlock::iterator end,
+ unsigned endcount) {
+ BB = bb;
+ Begin = begin;
+ InsertPosIndex = endcount;
+
+ ScheduleDAG::Run(bb, end);
+}
+
/// getOpcode - If this is an Instruction or a ConstantExpr, return the
/// opcode value. Otherwise return UserOp1.
static unsigned getOpcode(const Value *V) {
@@ -146,7 +159,7 @@
TM.getSubtarget<TargetSubtarget>().getSpecialAddressLatency();
// Walk the list of instructions, from bottom moving up.
- for (MachineBasicBlock::iterator MII = End, MIE = Begin;
+ for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
MII != MIE; --MII) {
MachineInstr *MI = prior(MII);
const TargetInstrDesc &TID = MI->getDesc();
@@ -428,7 +441,7 @@
MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
// For MachineInstr-based scheduling, we're rescheduling the instructions in
// the block, so start by removing them from the block.
- while (Begin != End) {
+ while (Begin != InsertPos) {
MachineBasicBlock::iterator I = Begin;
++Begin;
BB->remove(I);
@@ -443,7 +456,7 @@
continue;
}
- BB->insert(End, SU->getInstr());
+ BB->insert(InsertPos, SU->getInstr());
}
// Update the Begin iterator, as the first instruction in the block
Modified: llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.h?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.h (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/ScheduleDAGInstrs.h Wed Mar 11 13:10:31 2009
@@ -120,6 +120,12 @@
SmallSet<unsigned, 8> LoopLiveInRegs;
public:
+ MachineBasicBlock *BB; // Current basic block
+ MachineBasicBlock::iterator Begin; // The beginning of the range to
+ // be scheduled. The range extends
+ // to InsertPos.
+ unsigned InsertPosIndex; // The index in BB of InsertPos.
+
explicit ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt);
@@ -139,6 +145,13 @@
return &SUnits.back();
}
+ /// Run - perform scheduling.
+ ///
+ void Run(MachineBasicBlock *bb,
+ MachineBasicBlock::iterator begin,
+ MachineBasicBlock::iterator end,
+ unsigned endindex);
+
/// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
/// input.
virtual void BuildSchedGraph();
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Wed Mar 11 13:10:31 2009
@@ -629,6 +629,7 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::ScheduleDAGSDNodes *
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
return new ScheduleDAGFast(*IS->MF);
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Mar 11 13:10:31 2009
@@ -260,8 +260,8 @@
/// createTDListDAGScheduler - This creates a top-down list scheduler with a
/// new hazard recognizer. This scheduler takes ownership of the hazard
/// recognizer and deletes it when done.
-ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
- bool Fast) {
+ScheduleDAGSDNodes *
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
return new ScheduleDAGList(*IS->MF,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Mar 11 13:10:31 2009
@@ -1364,8 +1364,8 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
- bool) {
+llvm::ScheduleDAGSDNodes *
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1378,8 +1378,8 @@
return SD;
}
-llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
- bool) {
+llvm::ScheduleDAGSDNodes *
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Mar 11 13:10:31 2009
@@ -26,6 +26,14 @@
: ScheduleDAG(mf) {
}
+/// Run - perform scheduling.
+///
+void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
+ MachineBasicBlock::iterator insertPos) {
+ DAG = dag;
+ ScheduleDAG::Run(bb, insertPos);
+}
+
SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
SUnit *SU = NewSUnit(Old->getNode());
SU->OrigNode = Old->OrigNode;
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h Wed Mar 11 13:10:31 2009
@@ -35,10 +35,17 @@
///
class ScheduleDAGSDNodes : public ScheduleDAG {
public:
+ SelectionDAG *DAG; // DAG of the current basic block
+
explicit ScheduleDAGSDNodes(MachineFunction &mf);
virtual ~ScheduleDAGSDNodes() {}
+ /// Run - perform scheduling.
+ ///
+ void Run(SelectionDAG *dag, MachineBasicBlock *bb,
+ MachineBasicBlock::iterator insertPos);
+
/// isPassiveNode - Return true if the node is a non-scheduled leaf.
///
static bool isPassiveNode(SDNode *Node) {
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp Wed Mar 11 13:10:31 2009
@@ -125,7 +125,8 @@
} else {
// Create the reg, emit the copy.
VRBase = MRI.createVirtualRegister(DstRC);
- bool Emitted = TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC);
+ bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
+ DstRC, SrcRC);
if (!Emitted) {
cerr << "Unable to issue a copy instruction!\n";
abort();
@@ -381,7 +382,7 @@
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
MI->addOperand(MachineOperand::CreateImm(SubIdx));
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
} else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
Opc == TargetInstrInfo::SUBREG_TO_REG) {
SDValue N0 = Node->getOperand(0);
@@ -414,7 +415,7 @@
// Add the subregster being inserted
AddOperand(MI, N1, 0, 0, VRBaseMap);
MI->addOperand(MachineOperand::CreateImm(SubIdx));
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
} else
assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
@@ -478,9 +479,9 @@
// Insert this instruction into the basic block using a target
// specific inserter which may returns a new basic block.
BB = TLI->EmitInstrWithCustomInserter(MI, BB);
- Begin = End = BB->end();
+ InsertPos = BB->end();
} else {
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
}
// Additional results must be an physical register def.
@@ -530,7 +531,8 @@
else
DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
Node->getOperand(1).getValueType());
- bool Emitted = TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC);
+ bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
+ DstTRC, SrcTRC);
if (!Emitted) {
cerr << "Unable to issue a copy instruction!\n";
abort();
@@ -590,7 +592,7 @@
break;
}
}
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
break;
}
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=66676&r1=66675&r2=66676&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Mar 11 13:10:31 2009
@@ -137,8 +137,8 @@
//===--------------------------------------------------------------------===//
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
- ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
- bool Fast) {
+ ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
+ bool Fast) {
const TargetLowering &TLI = IS->getTargetLowering();
if (Fast)
@@ -662,12 +662,12 @@
if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
// Schedule machine code.
- ScheduleDAG *Scheduler = CreateScheduler();
+ ScheduleDAGSDNodes *Scheduler = CreateScheduler();
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Scheduling", GroupName);
- Scheduler->Run(CurDAG, BB, BB->end(), BB->end());
+ Scheduler->Run(CurDAG, BB, BB->end());
} else {
- Scheduler->Run(CurDAG, BB, BB->end(), BB->end());
+ Scheduler->Run(CurDAG, BB, BB->end());
}
if (ViewSUnitDAGs) Scheduler->viewGraph();
@@ -1068,7 +1068,7 @@
/// via the SchedulerRegistry, use it, otherwise select the
/// one preferred by the target.
///
-ScheduleDAG *SelectionDAGISel::CreateScheduler() {
+ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
if (!Ctor) {
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