[llvm-commits] [llvm] r65997 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/Target/X86/X86RegisterInfo.td test/CodeGen/X86/pr3701.ll
Bill Wendling
isanbard at gmail.com
Tue Mar 3 17:47:35 PST 2009
Author: void
Date: Tue Mar 3 19:47:35 2009
New Revision: 65997
URL: http://llvm.org/viewvc/llvm-project?rev=65997&view=rev
Log:
--- Merging (from foreign repository) r65996 into '.':
A test/CodeGen/X86/pr3701.ll
U lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
U lib/Target/X86/X86RegisterInfo.td
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what
llvm-gcc generates so codegen knows flags register is being clobbered by inline
asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live"
physical registers. Previously it was only checking target nodes with implicit
defs.
Added:
llvm/branches/Apple/Dib/test/CodeGen/X86/pr3701.ll
Modified:
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=65997&r1=65996&r2=65997&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Mar 3 19:47:35 2009
@@ -572,6 +572,30 @@
return N->getValueType(NumRes);
}
+/// CheckForLiveRegDef - Return true and update live register vector if the
+/// specified register def of the specified SUnit clobbers any "live" registers.
+static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
+ std::vector<SUnit*> &LiveRegDefs,
+ SmallSet<unsigned, 4> &RegAdded,
+ SmallVector<unsigned, 4> &LRegs,
+ const TargetRegisterInfo *TRI) {
+ bool Added = false;
+ if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != SU) {
+ if (RegAdded.insert(Reg)) {
+ LRegs.push_back(Reg);
+ Added = true;
+ }
+ }
+ for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
+ if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
+ if (RegAdded.insert(*Alias)) {
+ LRegs.push_back(*Alias);
+ Added = true;
+ }
+ }
+ return Added;
+}
+
/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
/// scheduling of the given node to satisfy live physical register dependencies.
/// If the specific node is the last one that's available to schedule, do
@@ -585,39 +609,44 @@
// If this node would clobber any "live" register, then it's not ready.
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
- if (I->isAssignedRegDep()) {
- unsigned Reg = I->getReg();
- if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->getSUnit()) {
- if (RegAdded.insert(Reg))
- LRegs.push_back(Reg);
- }
- for (const unsigned *Alias = TRI->getAliasSet(Reg);
- *Alias; ++Alias)
- if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->getSUnit()) {
- if (RegAdded.insert(*Alias))
- LRegs.push_back(*Alias);
- }
- }
+ if (I->isAssignedRegDep())
+ CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
+ RegAdded, LRegs, TRI);
}
for (SDNode *Node = SU->getNode(); Node; Node = Node->getFlaggedNode()) {
+ if (Node->getOpcode() == ISD::INLINEASM) {
+ // Inline asm can clobber physical defs.
+ unsigned NumOps = Node->getNumOperands();
+ if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
+ --NumOps; // Ignore the flag operand.
+
+ for (unsigned i = 2; i != NumOps;) {
+ unsigned Flags =
+ cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
+ unsigned NumVals = Flags >> 3;
+
+ ++i; // Skip the ID value.
+ if ((Flags & 7) == 2 || (Flags & 7) == 6) {
+ // Check for def of register or earlyclobber register.
+ for (; NumVals; --NumVals, ++i) {
+ unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(Reg))
+ CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
+ }
+ } else
+ i += NumVals;
+ }
+ continue;
+ }
+
if (!Node->isMachineOpcode())
continue;
const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
if (!TID.ImplicitDefs)
continue;
- for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
- if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) {
- if (RegAdded.insert(*Reg))
- LRegs.push_back(*Reg);
- }
- for (const unsigned *Alias = TRI->getAliasSet(*Reg);
- *Alias; ++Alias)
- if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
- if (RegAdded.insert(*Alias))
- LRegs.push_back(*Alias);
- }
- }
+ for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg)
+ CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
}
return !LRegs.empty();
}
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td?rev=65997&r1=65996&r2=65997&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td Tue Mar 3 19:47:35 2009
@@ -167,7 +167,7 @@
def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
// Status flags register
- def EFLAGS : Register<"eflags">;
+ def EFLAGS : Register<"flags">;
}
Added: llvm/branches/Apple/Dib/test/CodeGen/X86/pr3701.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/pr3701.ll?rev=65997&view=auto
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/pr3701.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/pr3701.ll Tue Mar 3 19:47:35 2009
@@ -0,0 +1,17 @@
+; RUN: llvm-as < %s | llc -march=x86-64 | %prcontext test 1 | grep j
+; PR3701
+
+define i64 @t(i64* %arg) nounwind {
+ br i1 true, label %1, label %5
+
+; <label>:1 ; preds = %0
+ %2 = icmp eq i64* null, %arg ; <i1> [#uses=1]
+ %3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%struct.thread*> [#uses=0]
+ br i1 %2, label %4, label %5
+
+; <label>:4 ; preds = %1
+ ret i64 1
+
+; <label>:5 ; preds = %1
+ ret i64 0
+}
More information about the llvm-commits
mailing list