[llvm-commits] [llvm] r64552 [1/2] - in /llvm/branches/Apple/Dib: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ lib/Target/X86/AsmPrinter/ lib/Target/XCore/ utils/TableGen/
Bill Wendling
isanbard at gmail.com
Sat Feb 14 05:20:35 PST 2009
Author: void
Date: Sat Feb 14 07:20:23 2009
New Revision: 64552
URL: http://llvm.org/viewvc/llvm-project?rev=64552&view=rev
Log:
Merged these revisions into Dib:
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Modified:
llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h
llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h
llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h
llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h
llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h
llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp
llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h
llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h
llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp
llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp
llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h
llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h
llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp
llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp
llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/Sparc/SparcInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/Sparc/SparcRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPoint.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPointRegKill.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.h
llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelDAGToDAG.cpp
llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/XCore/XCoreInstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/XCore/XCoreRegisterInfo.cpp
llvm/branches/Apple/Dib/lib/Target/XCore/XCoreRegisterInfo.h
llvm/branches/Apple/Dib/utils/TableGen/DAGISelEmitter.cpp
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/DebugLoc.h Sat Feb 14 07:20:23 2009
@@ -40,12 +40,17 @@
static DebugLoc getUnknownLoc() { DebugLoc L; L.Idx = 0; return L; }
static DebugLoc get(unsigned idx) { DebugLoc L; L.Idx = idx; return L; }
+ unsigned getIndex() const { return Idx; }
+
/// isInvalid - Return true if the DebugLoc is invalid.
bool isInvalid() const { return Idx == ~0U; }
/// isUnknown - Return true if there is no debug info for the SDNode /
/// MachineInstr.
bool isUnknown() const { return Idx == 0; }
+
+ bool operator==(const DebugLoc &DL) const { return Idx == DL.Idx; }
+ bool operator!=(const DebugLoc &DL) const { return !(*this == DL); }
};
// Partially specialize DenseMapInfo for DebugLocTyple.
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineFunction.h Sat Feb 14 07:20:23 2009
@@ -313,9 +313,12 @@
//
/// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given
- /// source file, line, and column. If none currently exists, create add a new
- /// new DebugLocTuple and insert it into the DebugIdMap.
+ /// source file, line, and column. If none currently exists, create a new
+ /// DebugLocTuple, and insert it into the DebugIdMap.
unsigned getOrCreateDebugLocID(unsigned Src, unsigned Line, unsigned Col);
+
+ /// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object.
+ DebugLocTuple getDebugLocTuple(DebugLoc DL) const;
};
//===--------------------------------------------------------------------===//
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/MachineInstrBuilder.h Sat Feb 14 07:20:23 2009
@@ -99,11 +99,6 @@
/// itself.
///
inline MachineInstrBuilder BuildMI(MachineFunction &MF,
- const TargetInstrDesc &TID) {
- return MachineInstrBuilder(MF.CreateMachineInstr(TID,
- DebugLoc::getUnknownLoc()));
-}
-inline MachineInstrBuilder BuildMI(MachineFunction &MF,
DebugLoc DL,
const TargetInstrDesc &TID) {
return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL));
@@ -113,13 +108,6 @@
/// destination virtual register.
///
inline MachineInstrBuilder BuildMI(MachineFunction &MF,
- const TargetInstrDesc &TID,
- unsigned DestReg) {
- return MachineInstrBuilder(MF.CreateMachineInstr(TID,
- DebugLoc::getUnknownLoc()))
- .addReg(DestReg, true);
-}
-inline MachineInstrBuilder BuildMI(MachineFunction &MF,
DebugLoc DL,
const TargetInstrDesc &TID,
unsigned DestReg) {
@@ -133,15 +121,6 @@
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
- const TargetInstrDesc &TID,
- unsigned DestReg) {
- MachineInstr *MI =
- BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc());
- BB.insert(I, MI);
- return MachineInstrBuilder(MI).addReg(DestReg, true);
-}
-inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
- MachineBasicBlock::iterator I,
DebugLoc DL,
const TargetInstrDesc &TID,
unsigned DestReg) {
@@ -156,14 +135,6 @@
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
- const TargetInstrDesc &TID) {
- MachineInstr *MI =
- BB.getParent()->CreateMachineInstr(TID, DebugLoc::getUnknownLoc());
- BB.insert(I, MI);
- return MachineInstrBuilder(MI);
-}
-inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
- MachineBasicBlock::iterator I,
DebugLoc DL,
const TargetInstrDesc &TID) {
MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL);
@@ -176,10 +147,6 @@
/// destination register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
- const TargetInstrDesc &TID) {
- return BuildMI(*BB, BB->end(), TID);
-}
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
DebugLoc DL,
const TargetInstrDesc &TID) {
return BuildMI(*BB, BB->end(), DL, TID);
@@ -190,11 +157,6 @@
/// operand as a destination virtual register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
- const TargetInstrDesc &TID,
- unsigned DestReg) {
- return BuildMI(*BB, BB->end(), TID, DestReg);
-}
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
DebugLoc DL,
const TargetInstrDesc &TID,
unsigned DestReg) {
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAG.h Sat Feb 14 07:20:23 2009
@@ -41,7 +41,8 @@
private:
mutable SDNode Sentinel;
public:
- ilist_traits() : Sentinel(ISD::DELETED_NODE, SDVTList()) {}
+ ilist_traits() : Sentinel(ISD::DELETED_NODE, DebugLoc::getUnknownLoc(),
+ SDVTList()) {}
SDNode *createSentinel() const {
return &Sentinel;
@@ -306,6 +307,8 @@
int Offset = 0) {
return getConstantPool(C, VT, Align, Offset, true);
}
+ // When generating a branch to a BB, we don't in general know enough
+ // to provide debug info for the BB at that time, so keep this one around.
SDValue getBasicBlock(MachineBasicBlock *MBB);
SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);
SDValue getExternalSymbol(const char *Sym, MVT VT);
@@ -317,74 +320,76 @@
SDValue getRegister(unsigned Reg, MVT VT);
SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col,
Value *CU);
- SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID);
SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root,
unsigned LabelID);
- SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N) {
- return getNode(ISD::CopyToReg, MVT::Other, Chain,
+ SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
+ return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
getRegister(Reg, N.getValueType()), N);
}
// This version of the getCopyToReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
- SDValue getCopyToReg(SDValue Chain, unsigned Reg, SDValue N,
+ SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
SDValue Flag) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
- return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
+ return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
}
// Similar to last getCopyToReg() except parameter Reg is a SDValue
- SDValue getCopyToReg(SDValue Chain, SDValue Reg, SDValue N,
+ SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
SDValue Flag) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Reg, N, Flag };
- return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
+ return getNode(ISD::CopyToReg, dl, VTs, 2, Ops, Flag.getNode() ? 4 : 3);
}
- SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT) {
+ SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
- return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2);
+ return getNode(ISD::CopyFromReg, dl, VTs, 2, Ops, 2);
}
// This version of the getCopyFromReg method takes an extra operand, which
// indicates that there is potentially an incoming flag value (if Flag is not
// null) and that there should be a flag result.
- SDValue getCopyFromReg(SDValue Chain, unsigned Reg, MVT VT,
+ SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, MVT VT,
SDValue Flag) {
const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
- return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.getNode() ? 3 : 2);
+ return getNode(ISD::CopyFromReg, dl, VTs, 3, Ops, Flag.getNode() ? 3 : 2);
}
SDValue getCondCode(ISD::CondCode Cond);
/// Returns the ConvertRndSat Note: Avoid using this node because it may
/// disappear in the future and most targets don't support it.
- SDValue getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy,
+ SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
+ SDValue STy,
SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
/// getZeroExtendInReg - Return the expression required to zero extend the Op
/// value assuming it was the smaller SrcTy value.
- SDValue getZeroExtendInReg(SDValue Op, MVT SrcTy);
SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
- /// a flag result (to ensure it's not CSE'd).
+ /// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a
+ /// useful DebugLoc.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Op };
- return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2);
+ return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
+ VTs, 2, Ops, 2);
}
/// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a
- /// flag result (to ensure it's not CSE'd).
+ /// flag result (to ensure it's not CSE'd). CALLSEQ_END does not have
+ /// a useful DebugLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
SDValue InFlag) {
SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
@@ -393,98 +398,74 @@
Ops.push_back(Op1);
Ops.push_back(Op2);
Ops.push_back(InFlag);
- return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
+ return getNode(ISD::CALLSEQ_END, DebugLoc::getUnknownLoc(), NodeTys,
+ &Ops[0],
(unsigned)Ops.size() - (InFlag.getNode() == 0 ? 1 : 0));
}
+ /// getUNDEF - Return an UNDEF node. UNDEF does not have a useful DebugLoc.
+ SDValue getUNDEF(MVT VT) {
+ return getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), VT);
+ }
+
+ /// getGLOBAL_OFFSET_TABLE - Return a GLOBAL_OFFSET_TABLE node. This does
+ /// not have a useful DebugLoc.
+ SDValue getGLOBAL_OFFSET_TABLE(MVT VT) {
+ return getNode(ISD::GLOBAL_OFFSET_TABLE, DebugLoc::getUnknownLoc(), VT);
+ }
+
/// getNode - Gets or creates the specified node.
///
- SDValue getNode(unsigned Opcode, MVT VT);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT);
- SDValue getNode(unsigned Opcode, MVT VT, SDValue N);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N);
- SDValue getNode(unsigned Opcode, MVT VT, SDValue N1, SDValue N2);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDValue N1, SDValue N2);
- SDValue getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3);
- SDValue getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3, SDValue N4);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4);
- SDValue getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3, SDValue N4,
- SDValue N5);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5);
- SDValue getNode(unsigned Opcode, MVT VT,
- const SDUse *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
const SDUse *Ops, unsigned NumOps);
- SDValue getNode(unsigned Opcode, MVT VT,
- const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, MVT VT,
const SDValue *Ops, unsigned NumOps);
- SDValue getNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
- const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL,
const std::vector<MVT> &ResultTys,
const SDValue *Ops, unsigned NumOps);
- SDValue getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
- const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, const MVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps);
- SDValue getNode(unsigned Opcode, SDVTList VTs,
- const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);
-
- SDValue getNode(unsigned Opcode, SDVTList VTs);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs);
- SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N);
- SDValue getNode(unsigned Opcode, SDVTList VTs, SDValue N1, SDValue N2);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
SDValue N1, SDValue N2);
- SDValue getNode(unsigned Opcode, SDVTList VTs,
- SDValue N1, SDValue N2, SDValue N3);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
SDValue N1, SDValue N2, SDValue N3);
- SDValue getNode(unsigned Opcode, SDVTList VTs,
- SDValue N1, SDValue N2, SDValue N3, SDValue N4);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
SDValue N1, SDValue N2, SDValue N3, SDValue N4);
- SDValue getNode(unsigned Opcode, SDVTList VTs,
- SDValue N1, SDValue N2, SDValue N3, SDValue N4,
- SDValue N5);
SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
SDValue N1, SDValue N2, SDValue N3, SDValue N4,
SDValue N5);
- SDValue getMemcpy(SDValue Chain, SDValue Dst, SDValue Src,
+ SDValue getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
const Value *SrcSV, uint64_t SrcSVOff);
- SDValue getMemmove(SDValue Chain, SDValue Dst, SDValue Src,
+ SDValue getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstOSVff,
const Value *SrcSV, uint64_t SrcSVOff);
- SDValue getMemset(SDValue Chain, SDValue Dst, SDValue Src,
+ SDValue getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstSVOff);
/// getSetCC - Helper function to make it easier to build SetCC's if you just
/// have an ISD::CondCode instead of an SDValue.
///
- SDValue getSetCC(MVT VT, SDValue LHS, SDValue RHS,
- ISD::CondCode Cond) {
- return getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), VT,
- LHS, RHS, getCondCode(Cond));
- }
SDValue getSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
@@ -493,11 +474,6 @@
/// getVSetCC - Helper function to make it easier to build VSetCC's nodes
/// if you just have an ISD::CondCode instead of an SDValue.
///
- SDValue getVSetCC(MVT VT, SDValue LHS, SDValue RHS,
- ISD::CondCode Cond) {
- return getNode(ISD::VSETCC, DebugLoc::getUnknownLoc(), VT,
- LHS, RHS, getCondCode(Cond));
- }
SDValue getVSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS,
ISD::CondCode Cond) {
return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond));
@@ -506,11 +482,6 @@
/// getSelectCC - Helper function to make it easier to build SelectCC's if you
/// just have an ISD::CondCode instead of an SDValue.
///
- SDValue getSelectCC(SDValue LHS, SDValue RHS,
- SDValue True, SDValue False, ISD::CondCode Cond) {
- return getNode(ISD::SELECT_CC, DebugLoc::getUnknownLoc(), True.getValueType(),
- LHS, RHS, True, False, getCondCode(Cond));
- }
SDValue getSelectCC(DebugLoc DL, SDValue LHS, SDValue RHS,
SDValue True, SDValue False, ISD::CondCode Cond) {
return getNode(ISD::SELECT_CC, DL, True.getValueType(),
@@ -519,35 +490,23 @@
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
- SDValue getVAArg(MVT VT, SDValue Chain, SDValue Ptr,
+ SDValue getVAArg(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
SDValue SV);
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 3 operands
- SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr,
- SDValue Cmp, SDValue Swp, const Value* PtrVal,
- unsigned Alignment=0);
SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal,
unsigned Alignment=0);
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 2 operands.
- SDValue getAtomic(unsigned Opcode, MVT MemVT, SDValue Chain, SDValue Ptr,
- SDValue Val, const Value* PtrVal,
- unsigned Alignment = 0);
SDValue getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, SDValue Chain,
SDValue Ptr, SDValue Val, const Value* PtrVal,
unsigned Alignment = 0);
/// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
/// result and takes a list of operands.
- SDValue getMemIntrinsicNode(unsigned Opcode,
- const MVT *VTs, unsigned NumVTs,
- const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
- unsigned Align = 0, bool Vol = false,
- bool ReadMem = true, bool WriteMem = true);
SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
const MVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps,
@@ -555,11 +514,6 @@
unsigned Align = 0, bool Vol = false,
bool ReadMem = true, bool WriteMem = true);
- SDValue getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
- const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
- unsigned Align = 0, bool Vol = false,
- bool ReadMem = true, bool WriteMem = true);
SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
const SDValue *Ops, unsigned NumOps,
MVT MemVT, const Value *srcValue, int SVOff,
@@ -567,14 +521,10 @@
bool ReadMem = true, bool WriteMem = true);
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
- SDValue getMergeValues(const SDValue *Ops, unsigned NumOps);
SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);
/// getCall - Create a CALL node from the given information.
///
- SDValue getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall,
- bool isInreg, SDVTList VTs, const SDValue *Operands,
- unsigned NumOperands);
SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
bool IsTailCall, bool isInreg, SDVTList VTs,
const SDValue *Operands, unsigned NumOperands);
@@ -582,29 +532,15 @@
/// getLoad - Loads are not normal binary operators: their result type is not
/// determined by their operands, and they produce a value AND a token chain.
///
- SDValue getLoad(MVT VT, SDValue Chain, SDValue Ptr,
- const Value *SV, int SVOffset, bool isVolatile=false,
- unsigned Alignment=0);
SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
- SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT,
- SDValue Chain, SDValue Ptr, const Value *SV,
- int SVOffset, MVT EVT, bool isVolatile=false,
- unsigned Alignment=0);
SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
SDValue Chain, SDValue Ptr, const Value *SV,
int SVOffset, MVT EVT, bool isVolatile=false,
unsigned Alignment=0);
- SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base,
- SDValue Offset, ISD::MemIndexedMode AM);
SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
- SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
- MVT VT, SDValue Chain,
- SDValue Ptr, SDValue Offset,
- const Value *SV, int SVOffset, MVT EVT,
- bool isVolatile=false, unsigned Alignment=0);
SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
MVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
@@ -613,20 +549,12 @@
/// getStore - Helper function to build ISD::STORE nodes.
///
- SDValue getStore(SDValue Chain, SDValue Val, SDValue Ptr,
- const Value *SV, int SVOffset, bool isVolatile=false,
- unsigned Alignment=0);
SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
- SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr,
- const Value *SV, int SVOffset, MVT TVT,
- bool isVolatile=false, unsigned Alignment=0);
SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, MVT TVT,
bool isVolatile=false, unsigned Alignment=0);
- SDValue getIndexedStore(SDValue OrigStoe, SDValue Base,
- SDValue Offset, ISD::MemIndexedMode AM);
SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
@@ -719,70 +647,31 @@
/// Note that getTargetNode returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
- SDNode *getTargetNode(unsigned Opcode, MVT VT);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT, SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, SDValue Op1,
SDValue Op2);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT,
- SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
SDValue Op1, SDValue Op2, SDValue Op3);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT,
- const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
const SDValue *Ops, unsigned NumOps);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDValue Op1);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
SDValue Op1);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, SDValue Op1, SDValue Op2);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
- const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2,
const SDValue *Ops, unsigned NumOps);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDValue Op1, SDValue Op2);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
SDValue Op1, SDValue Op2);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDValue Op1, SDValue Op2, SDValue Op3);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
SDValue Op1, SDValue Op2, SDValue Op3);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
const SDValue *Ops, unsigned NumOps);
-
- SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
- const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, MVT VT2, MVT VT3,
MVT VT4, const SDValue *Ops, unsigned NumOps);
-
- SDNode *getTargetNode(unsigned Opcode, const std::vector<MVT> &ResultTys,
- const SDValue *Ops, unsigned NumOps);
SDNode *getTargetNode(unsigned Opcode, DebugLoc dl,
const std::vector<MVT> &ResultTys, const SDValue *Ops,
unsigned NumOps);
Modified: llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/CodeGen/SelectionDAGNodes.h Sat Feb 14 07:20:23 2009
@@ -1349,33 +1349,6 @@
return Ret;
}
- /// The constructors that supply DebugLoc explicitly should be preferred
- /// for new code.
- SDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps)
- : NodeType(Opc), OperandsNeedDelete(true), SubclassData(0),
- NodeId(-1),
- OperandList(NumOps ? new SDUse[NumOps] : 0),
- ValueList(VTs.VTs),
- UseList(NULL),
- NumOperands(NumOps), NumValues(VTs.NumVTs),
- debugLoc(DebugLoc::getUnknownLoc()) {
- for (unsigned i = 0; i != NumOps; ++i) {
- OperandList[i].setUser(this);
- OperandList[i].setInitial(Ops[i]);
- }
- }
-
- /// This constructor adds no operands itself; operands can be
- /// set later with InitOperands.
- SDNode(unsigned Opc, SDVTList VTs)
- : NodeType(Opc), OperandsNeedDelete(false), SubclassData(0),
- NodeId(-1), OperandList(0), ValueList(VTs.VTs), UseList(NULL),
- NumOperands(0), NumValues(VTs.NumVTs),
- debugLoc(DebugLoc::getUnknownLoc()) {}
-
- /// The next two constructors specify DebugLoc explicitly; the intent
- /// is that they will replace the above two over time, and eventually
- /// the ones above can be removed.
SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops,
unsigned NumOps)
: NodeType(Opc), OperandsNeedDelete(true), SubclassData(0),
@@ -1520,10 +1493,6 @@
class UnarySDNode : public SDNode {
SDUse Op;
public:
- UnarySDNode(unsigned Opc, SDVTList VTs, SDValue X)
- : SDNode(Opc, VTs) {
- InitOperands(&Op, X);
- }
UnarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X)
: SDNode(Opc, dl, VTs) {
InitOperands(&Op, X);
@@ -1535,10 +1504,6 @@
class BinarySDNode : public SDNode {
SDUse Ops[2];
public:
- BinarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y)
- : SDNode(Opc, VTs) {
- InitOperands(Ops, X, Y);
- }
BinarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y)
: SDNode(Opc, dl, VTs) {
InitOperands(Ops, X, Y);
@@ -1550,11 +1515,6 @@
class TernarySDNode : public SDNode {
SDUse Ops[3];
public:
- TernarySDNode(unsigned Opc, SDVTList VTs, SDValue X, SDValue Y,
- SDValue Z)
- : SDNode(Opc, VTs) {
- InitOperands(Ops, X, Y, Z);
- }
TernarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y,
SDValue Z)
: SDNode(Opc, dl, VTs) {
@@ -1577,7 +1537,8 @@
#else
explicit HandleSDNode(SDValue X)
#endif
- : SDNode(ISD::HANDLENODE, getSDVTList(MVT::Other)) {
+ : SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)) {
InitOperands(&Op, X);
}
~HandleSDNode();
@@ -1597,14 +1558,6 @@
int SVOffset;
public:
- MemSDNode(unsigned Opc, SDVTList VTs, MVT MemoryVT,
- const Value *srcValue, int SVOff,
- unsigned alignment, bool isvolatile);
-
- MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps,
- MVT MemoryVT, const Value *srcValue, int SVOff,
- unsigned alignment, bool isvolatile);
-
MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
const Value *srcValue, int SVOff,
unsigned alignment, bool isvolatile);
@@ -1680,21 +1633,6 @@
// Swp: swap value
// SrcVal: address to update as a Value (used for MemOperand)
// Align: alignment of memory
- AtomicSDNode(unsigned Opc, SDVTList VTL, MVT MemVT,
- SDValue Chain, SDValue Ptr,
- SDValue Cmp, SDValue Swp, const Value* SrcVal,
- unsigned Align=0)
- : MemSDNode(Opc, VTL, MemVT, SrcVal, /*SVOffset=*/0,
- Align, /*isVolatile=*/true) {
- InitOperands(Ops, Chain, Ptr, Cmp, Swp);
- }
- AtomicSDNode(unsigned Opc, SDVTList VTL, MVT MemVT,
- SDValue Chain, SDValue Ptr,
- SDValue Val, const Value* SrcVal, unsigned Align=0)
- : MemSDNode(Opc, VTL, MemVT, SrcVal, /*SVOffset=*/0,
- Align, /*isVolatile=*/true) {
- InitOperands(Ops, Chain, Ptr, Val);
- }
AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, MVT MemVT,
SDValue Chain, SDValue Ptr,
SDValue Cmp, SDValue Swp, const Value* SrcVal,
@@ -1744,13 +1682,6 @@
bool ReadMem; // Intrinsic reads memory
bool WriteMem; // Intrinsic writes memory
public:
- MemIntrinsicSDNode(unsigned Opc, SDVTList VTs,
- const SDValue *Ops, unsigned NumOps,
- MVT MemoryVT, const Value *srcValue, int SVO,
- unsigned Align, bool Vol, bool ReadMem, bool WriteMem)
- : MemSDNode(Opc, VTs, Ops, NumOps, MemoryVT, srcValue, SVO, Align, Vol),
- ReadMem(ReadMem), WriteMem(WriteMem) {
- }
MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
const SDValue *Ops, unsigned NumOps,
MVT MemoryVT, const Value *srcValue, int SVO,
@@ -1778,8 +1709,8 @@
protected:
friend class SelectionDAG;
ConstantSDNode(bool isTarget, const ConstantInt *val, MVT VT)
- : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, getSDVTList(VT)),
- Value(val) {
+ : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
+ DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
}
public:
@@ -1804,7 +1735,7 @@
friend class SelectionDAG;
ConstantFPSDNode(bool isTarget, const ConstantFP *val, MVT VT)
: SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
- getSDVTList(VT)), Value(val) {
+ DebugLoc::getUnknownLoc(), getSDVTList(VT)), Value(val) {
}
public:
@@ -1866,8 +1797,8 @@
protected:
friend class SelectionDAG;
FrameIndexSDNode(int fi, MVT VT, bool isTarg)
- : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, getSDVTList(VT)),
- FI(fi) {
+ : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
+ DebugLoc::getUnknownLoc(), getSDVTList(VT)), FI(fi) {
}
public:
@@ -1885,8 +1816,8 @@
protected:
friend class SelectionDAG;
JumpTableSDNode(int jti, MVT VT, bool isTarg)
- : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, getSDVTList(VT)),
- JTI(jti) {
+ : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
+ DebugLoc::getUnknownLoc(), getSDVTList(VT)), JTI(jti) {
}
public:
@@ -1910,12 +1841,14 @@
friend class SelectionDAG;
ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o=0)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
+ DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Offset(o), Alignment(0) {
assert((int)Offset >= 0 && "Offset is too large");
Val.ConstVal = c;
}
ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align)
- : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
+ : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
+ DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Offset(o), Alignment(Align) {
assert((int)Offset >= 0 && "Offset is too large");
Val.ConstVal = c;
@@ -1923,6 +1856,7 @@
ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
MVT VT, int o=0)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
+ DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Offset(o), Alignment(0) {
assert((int)Offset >= 0 && "Offset is too large");
Val.MachineCPVal = v;
@@ -1931,6 +1865,7 @@
ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
MVT VT, int o, unsigned Align)
: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
+ DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Offset(o), Alignment(Align) {
assert((int)Offset >= 0 && "Offset is too large");
Val.MachineCPVal = v;
@@ -1973,11 +1908,12 @@
MachineBasicBlock *MBB;
protected:
friend class SelectionDAG;
+ /// Debug info is meaningful and potentially useful here, but we create
+ /// blocks out of order when they're jumped to, which makes it a bit
+ /// harder. Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
- : SDNode(ISD::BasicBlock, getSDVTList(MVT::Other)), MBB(mbb) {
- }
- explicit BasicBlockSDNode(MachineBasicBlock *mbb, DebugLoc dl)
- : SDNode(ISD::BasicBlock, dl, getSDVTList(MVT::Other)), MBB(mbb) {
+ : SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)), MBB(mbb) {
}
public:
@@ -2003,7 +1939,8 @@
friend class SelectionDAG;
/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
- : SDNode(ISD::SRCVALUE, getSDVTList(MVT::Other)), V(v) {}
+ : SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)), V(v) {}
public:
/// getValue - return the contained Value.
@@ -2025,7 +1962,8 @@
friend class SelectionDAG;
/// Create a MachineMemOperand node
explicit MemOperandSDNode(const MachineMemOperand &mo)
- : SDNode(ISD::MEMOPERAND, getSDVTList(MVT::Other)), MO(mo) {}
+ : SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)), MO(mo) {}
public:
/// MO - The contained MachineMemOperand.
@@ -2043,7 +1981,8 @@
protected:
friend class SelectionDAG;
RegisterSDNode(unsigned reg, MVT VT)
- : SDNode(ISD::Register, getSDVTList(VT)), Reg(reg) {
+ : SDNode(ISD::Register, DebugLoc::getUnknownLoc(),
+ getSDVTList(VT)), Reg(reg) {
}
public:
@@ -2064,8 +2003,8 @@
friend class SelectionDAG;
DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
Value *cu)
- : SDNode(ISD::DBG_STOPPOINT, getSDVTList(MVT::Other)),
- Line(l), Column(c), CU(cu) {
+ : SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) {
InitOperands(&Chain, ch);
}
public:
@@ -2084,11 +2023,7 @@
unsigned LabelID;
protected:
friend class SelectionDAG;
- LabelSDNode(unsigned NodeTy, SDValue ch, unsigned id)
- : SDNode(NodeTy, getSDVTList(MVT::Other)), LabelID(id) {
- InitOperands(&Chain, ch);
- }
- LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
+LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
: SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
InitOperands(&Chain, ch);
}
@@ -2108,10 +2043,7 @@
friend class SelectionDAG;
ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT VT)
: SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
- getSDVTList(VT)), Symbol(Sym) {
- }
- ExternalSymbolSDNode(bool isTarget, DebugLoc dl, const char *Sym, MVT VT)
- : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, dl,
+ DebugLoc::getUnknownLoc(),
getSDVTList(VT)), Symbol(Sym) {
}
public:
@@ -2130,7 +2062,8 @@
protected:
friend class SelectionDAG;
explicit CondCodeSDNode(ISD::CondCode Cond)
- : SDNode(ISD::CONDCODE, getSDVTList(MVT::Other)), Condition(Cond) {
+ : SDNode(ISD::CONDCODE, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)), Condition(Cond) {
}
public:
@@ -2148,9 +2081,10 @@
ISD::CvtCode CvtCode;
protected:
friend class SelectionDAG;
- explicit CvtRndSatSDNode(MVT VT, const SDValue *Ops, unsigned NumOps,
- ISD::CvtCode Code)
- : SDNode(ISD::CONVERT_RNDSAT, getSDVTList(VT), Ops, NumOps), CvtCode(Code) {
+ explicit CvtRndSatSDNode(MVT VT, DebugLoc dl, const SDValue *Ops,
+ unsigned NumOps, ISD::CvtCode Code)
+ : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
+ CvtCode(Code) {
assert(NumOps == 5 && "wrong number of operations");
}
public:
@@ -2253,7 +2187,8 @@
protected:
friend class SelectionDAG;
explicit ARG_FLAGSSDNode(ISD::ArgFlagsTy Flags)
- : SDNode(ISD::ARG_FLAGS, getSDVTList(MVT::Other)), TheFlags(Flags) {
+ : SDNode(ISD::ARG_FLAGS, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)), TheFlags(Flags) {
}
public:
ISD::ArgFlagsTy getArgFlags() const { return TheFlags; }
@@ -2275,11 +2210,6 @@
bool Inreg;
protected:
friend class SelectionDAG;
- CallSDNode(unsigned cc, bool isvararg, bool istailcall, bool isinreg,
- SDVTList VTs, const SDValue *Operands, unsigned numOperands)
- : SDNode(ISD::CALL, VTs, Operands, numOperands),
- CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
- Inreg(isinreg) {}
CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
bool isinreg, SDVTList VTs, const SDValue *Operands,
unsigned numOperands)
@@ -2326,7 +2256,8 @@
protected:
friend class SelectionDAG;
explicit VTSDNode(MVT VT)
- : SDNode(ISD::VALUETYPE, getSDVTList(MVT::Other)), ValueType(VT) {
+ : SDNode(ISD::VALUETYPE, DebugLoc::getUnknownLoc(),
+ getSDVTList(MVT::Other)), ValueType(VT) {
}
public:
@@ -2350,17 +2281,6 @@
*/
SDUse Ops[4];
public:
- LSBaseSDNode(ISD::NodeType NodeTy, SDValue *Operands, unsigned numOperands,
- SDVTList VTs, ISD::MemIndexedMode AM, MVT VT,
- const Value *SV, int SVO, unsigned Align, bool Vol)
- : MemSDNode(NodeTy, VTs, VT, SV, SVO, Align, Vol) {
- assert(Align != 0 && "Loads and stores should have non-zero aligment");
- SubclassData |= AM << 2;
- assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");
- InitOperands(Ops, Operands, numOperands);
- assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
- "Only indexed loads and stores have a non-undef offset operand");
- }
LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands,
unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
MVT VT, const Value *SV, int SVO, unsigned Align, bool Vol)
@@ -2401,14 +2321,6 @@
class LoadSDNode : public LSBaseSDNode {
protected:
friend class SelectionDAG;
- LoadSDNode(SDValue *ChainPtrOff, SDVTList VTs,
- ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
- const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
- : LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3,
- VTs, AM, LVT, SV, O, Align, Vol) {
- SubclassData |= (unsigned short)ETy;
- assert(getExtensionType() == ETy && "LoadExtType encoding error!");
- }
LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs,
ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
@@ -2439,14 +2351,6 @@
class StoreSDNode : public LSBaseSDNode {
protected:
friend class SelectionDAG;
- StoreSDNode(SDValue *ChainValuePtrOff, SDVTList VTs,
- ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
- const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
- : LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4,
- VTs, AM, SVT, SV, O, Align, Vol) {
- SubclassData |= (unsigned short)isTrunc;
- assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!");
- }
StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,
ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
Modified: llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h (original)
+++ llvm/branches/Apple/Dib/include/llvm/Target/TargetLowering.h Sat Feb 14 07:20:23 2009
@@ -1101,7 +1101,7 @@
/// for another call). If the target chooses to decline an AlwaysInline
/// request here, legalize will resort to using simple loads and stores.
virtual SDValue
- EmitTargetCodeForMemcpy(SelectionDAG &DAG,
+ EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
@@ -1118,7 +1118,7 @@
/// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
virtual SDValue
- EmitTargetCodeForMemmove(SelectionDAG &DAG,
+ EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
@@ -1134,7 +1134,7 @@
/// SDValue if the target declines to use custom code and a different
/// lowering strategy should be used.
virtual SDValue
- EmitTargetCodeForMemset(SelectionDAG &DAG,
+ EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
Modified: llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/AsmPrinter/DwarfWriter.cpp Sat Feb 14 07:20:23 2009
@@ -54,9 +54,9 @@
/// Configuration values for initial hash set sizes (log2).
///
-static const unsigned InitDiesSetSize = 9; // 512
-static const unsigned InitAbbreviationsSetSize = 9; // 512
-static const unsigned InitValuesSetSize = 9; // 512
+static const unsigned InitDiesSetSize = 9; // log2(512)
+static const unsigned InitAbbreviationsSetSize = 9; // log2(512)
+static const unsigned InitValuesSetSize = 9; // log2(512)
//===----------------------------------------------------------------------===//
/// Forward declarations.
@@ -855,9 +855,7 @@
/// Dwarf - Emits general Dwarf directives.
///
class Dwarf {
-
protected:
-
//===--------------------------------------------------------------------===//
// Core attributes used by the Dwarf writer.
//
@@ -918,7 +916,6 @@
}
public:
-
//===--------------------------------------------------------------------===//
// Accessors.
//
@@ -1166,7 +1163,7 @@
unsigned LabelID; // Label in code ID number.
public:
SrcLineInfo(unsigned L, unsigned C, unsigned S, unsigned I)
- : Line(L), Column(C), SourceID(S), LabelID(I) {}
+ : Line(L), Column(C), SourceID(S), LabelID(I) {}
// Accessors
unsigned getLine() const { return Line; }
@@ -1175,7 +1172,6 @@
unsigned getLabelID() const { return LabelID; }
};
-
//===----------------------------------------------------------------------===//
/// SrcFileInfo - This class is used to track source information.
///
@@ -1207,10 +1203,8 @@
/// DbgVariable - This class is used to track local variable information.
///
class DbgVariable {
-private:
DIVariable Var; // Variable Descriptor.
unsigned FrameIndex; // Variable frame index.
-
public:
DbgVariable(DIVariable V, unsigned I) : Var(V), FrameIndex(I) {}
@@ -1223,7 +1217,6 @@
/// DbgScope - This class is used to track scope information.
///
class DbgScope {
-private:
DbgScope *Parent; // Parent to this scope.
DIDescriptor Desc; // Debug info descriptor for scope.
// Either subprogram or block.
@@ -1231,7 +1224,6 @@
unsigned EndLabelID; // Label ID of the end of scope.
SmallVector<DbgScope *, 4> Scopes; // Scopes defined in scope.
SmallVector<DbgVariable *, 8> Variables;// Variables declared in scope.
-
public:
DbgScope(DbgScope *P, DIDescriptor D)
: Parent(P), Desc(D), StartLabelID(0), EndLabelID(0), Scopes(), Variables()
@@ -1264,8 +1256,6 @@
/// DwarfDebug - Emits Dwarf debug directives.
///
class DwarfDebug : public Dwarf {
-
-private:
//===--------------------------------------------------------------------===//
// Attributes used to construct specific Dwarf sections.
//
@@ -1641,7 +1631,7 @@
else if (Ty.isDerivedType(Ty.getTag()))
ConstructTypeDIE(DW_Unit, Buffer, DIDerivedType(Ty.getGV()));
else {
- assert (Ty.isCompositeType(Ty.getTag()) && "Unknown kind of DIType");
+ assert(Ty.isCompositeType(Ty.getTag()) && "Unknown kind of DIType");
ConstructTypeDIE(DW_Unit, Buffer, DICompositeType(Ty.getGV()));
}
@@ -1656,8 +1646,7 @@
Die->AddChild(Child);
Buffer.Detach();
SetDIEntry(Slot, Child);
- }
- else {
+ } else {
Die = DW_Unit->AddDie(Buffer);
SetDIEntry(Slot, Die);
}
@@ -1806,8 +1795,8 @@
}
}
- // ConstructSubrangeDIE - Construct subrange DIE from DISubrange.
- void ConstructSubrangeDIE (DIE &Buffer, DISubrange SR, DIE *IndexTy) {
+ /// ConstructSubrangeDIE - Construct subrange DIE from DISubrange.
+ void ConstructSubrangeDIE(DIE &Buffer, DISubrange SR, DIE *IndexTy) {
int64_t L = SR.getLo();
int64_t H = SR.getHi();
DIE *DW_Subrange = new DIE(DW_TAG_subrange_type);
@@ -1845,8 +1834,7 @@
}
}
- /// ConstructEnumTypeDIE - Construct enum type DIE from
- /// DIEnumerator.
+ /// ConstructEnumTypeDIE - Construct enum type DIE from DIEnumerator.
DIE *ConstructEnumTypeDIE(CompileUnit *DW_Unit, DIEnumerator *ETy) {
DIE *Enumerator = new DIE(DW_TAG_enumerator);
@@ -1857,7 +1845,7 @@
}
/// CreateGlobalVariableDIE - Create new DIE using GV.
- DIE *CreateGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV)
+ DIE *CreateGlobalVariableDIE(CompileUnit *DW_Unit, const DIGlobalVariable &GV)
{
DIE *GVDie = new DIE(DW_TAG_variable);
AddString(GVDie, DW_AT_name, DW_FORM_string, GV.getName());
@@ -2101,9 +2089,9 @@
std::string SPName = "llvm.dbg.subprograms";
std::vector<GlobalVariable*> Result;
getGlobalVariablesUsing(*M, SPName, Result);
+
for (std::vector<GlobalVariable *>::iterator I = Result.begin(),
E = Result.end(); I != E; ++I) {
-
DISubprogram SPD(*I);
if (SPD.getName() == MF->getFunction()->getName()) {
@@ -2795,7 +2783,7 @@
CompileUnit *Unit = new CompileUnit(ID, Die);
if (DIUnit.isMain()) {
- assert (!MainCU && "Multiple main compile units are found!");
+ assert(!MainCU && "Multiple main compile units are found!");
MainCU = Unit;
}
DW_CUs[DIUnit.getGV()] = Unit;
@@ -2901,41 +2889,40 @@
/// SetDebugInfo - Create global DIEs and emit initial debug info sections.
/// This is inovked by the target AsmPrinter.
void SetDebugInfo(MachineModuleInfo *mmi) {
-
- // Create all the compile unit DIEs.
- ConstructCompileUnits();
+ // Create all the compile unit DIEs.
+ ConstructCompileUnits();
- if (DW_CUs.empty())
- return;
+ if (DW_CUs.empty())
+ return;
- MMI = mmi;
- shouldEmit = true;
- MMI->setDebugInfoAvailability(true);
-
- // Create DIEs for each of the externally visible global variables.
- ConstructGlobalVariableDIEs();
-
- // Create DIEs for each of the externally visible subprograms.
- ConstructSubprograms();
-
- // Prime section data.
- SectionMap.insert(TAI->getTextSection());
-
- // Print out .file directives to specify files for .loc directives. These
- // are printed out early so that they precede any .loc directives.
- if (TAI->hasDotLocAndDotFile()) {
- for (unsigned i = 1, e = SrcFiles.size(); i <= e; ++i) {
- sys::Path FullPath(Directories[SrcFiles[i].getDirectoryID()]);
- bool AppendOk = FullPath.appendComponent(SrcFiles[i].getName());
- assert(AppendOk && "Could not append filename to directory!");
- AppendOk = false;
- Asm->EmitFile(i, FullPath.toString());
- Asm->EOL();
- }
+ MMI = mmi;
+ shouldEmit = true;
+ MMI->setDebugInfoAvailability(true);
+
+ // Create DIEs for each of the externally visible global variables.
+ ConstructGlobalVariableDIEs();
+
+ // Create DIEs for each of the externally visible subprograms.
+ ConstructSubprograms();
+
+ // Prime section data.
+ SectionMap.insert(TAI->getTextSection());
+
+ // Print out .file directives to specify files for .loc directives. These
+ // are printed out early so that they precede any .loc directives.
+ if (TAI->hasDotLocAndDotFile()) {
+ for (unsigned i = 1, e = SrcFiles.size(); i <= e; ++i) {
+ sys::Path FullPath(Directories[SrcFiles[i].getDirectoryID()]);
+ bool AppendOk = FullPath.appendComponent(SrcFiles[i].getName());
+ assert(AppendOk && "Could not append filename to directory!");
+ AppendOk = false;
+ Asm->EmitFile(i, FullPath.toString());
+ Asm->EOL();
}
+ }
- // Emit initial sections
- EmitInitial();
+ // Emit initial sections
+ EmitInitial();
}
/// BeginModule - Emit all Dwarf sections that should come prior to the
@@ -3094,13 +3081,13 @@
unsigned Tag = DI.getTag();
switch (Tag) {
case DW_TAG_variable:
- assert (DIVariable(GV).Verify() && "Invalid DebugInfo value");
+ assert(DIVariable(GV).Verify() && "Invalid DebugInfo value");
break;
case DW_TAG_compile_unit:
- assert (DICompileUnit(GV).Verify() && "Invalid DebugInfo value");
+ assert(DICompileUnit(GV).Verify() && "Invalid DebugInfo value");
break;
case DW_TAG_subprogram:
- assert (DISubprogram(GV).Verify() && "Invalid DebugInfo value");
+ assert(DISubprogram(GV).Verify() && "Invalid DebugInfo value");
break;
default:
break;
@@ -3114,7 +3101,7 @@
/// correspondence to the source line list.
unsigned RecordSourceLine(Value *V, unsigned Line, unsigned Col) {
CompileUnit *Unit = DW_CUs[V];
- assert (Unit && "Unable to find CompileUnit");
+ assert(Unit && "Unable to find CompileUnit");
unsigned ID = MMI->NextLabelID();
Lines.push_back(SrcLineInfo(Line, Col, Unit->getID(), ID));
return ID;
@@ -3173,7 +3160,7 @@
DIVariable DV(GV);
Scope = getOrCreateScope(DV.getContext().getGV());
}
- assert (Scope && "Unable to find variable' scope");
+ assert(Scope && "Unable to find variable' scope");
DbgVariable *DV = new DbgVariable(DIVariable(GV), FrameIndex);
Scope->AddVariable(DV);
}
@@ -3183,8 +3170,6 @@
/// DwarfException - Emits Dwarf exception handling directives.
///
class DwarfException : public Dwarf {
-
-private:
struct FunctionEHFrameInfo {
std::string FnName;
unsigned Number;
Modified: llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/GCStrategy.cpp Sat Feb 14 07:20:23 2009
@@ -329,6 +329,7 @@
unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
unsigned Label = MMI->NextLabelID();
+ // N.B. we assume that MI is *not* equal to the "end()" iterator.
BuildMI(MBB, MI, MI->getDebugLoc(),
TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label);
return Label;
Modified: llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/MachineFunction.cpp Sat Feb 14 07:20:23 2009
@@ -380,11 +380,11 @@
}
/// getOrCreateDebugLocID - Look up the DebugLocTuple index with the given
-/// source file, line, and column. If none currently exists, create add a new
-/// new DebugLocTuple and insert it into the DebugIdMap.
+/// source file, line, and column. If none currently exists, create a new
+/// DebugLocTuple, and insert it into the DebugIdMap.
unsigned MachineFunction::getOrCreateDebugLocID(unsigned Src, unsigned Line,
unsigned Col) {
- struct DebugLocTuple Tuple(Src, Line, Col);
+ DebugLocTuple Tuple(Src, Line, Col);
DenseMap<DebugLocTuple, unsigned>::iterator II
= DebugLocInfo.DebugIdMap.find(Tuple);
if (II != DebugLocInfo.DebugIdMap.end())
@@ -396,6 +396,14 @@
return Id;
}
+/// getDebugLocTuple - Get the DebugLocTuple for a given DebugLoc object.
+DebugLocTuple MachineFunction::getDebugLocTuple(DebugLoc DL) const {
+ unsigned Idx = DL.getIndex();
+ assert(Idx < DebugLocInfo.DebugLocations.size() &&
+ "Invalid index into debug locations!");
+ return DebugLocInfo.DebugLocations[Idx];
+}
+
//===----------------------------------------------------------------------===//
// MachineFrameInfo implementation
//===----------------------------------------------------------------------===//
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Feb 14 07:20:23 2009
@@ -2490,7 +2490,7 @@
return N0;
// fold (shl x, c >= size(x)) -> undef
if (N1C && N1C->getZExtValue() >= OpSizeInBits)
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+ return DAG.getUNDEF(VT);
// fold (shl x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
@@ -2571,7 +2571,7 @@
return N0;
// fold (sra x, (setge c, size(x))) -> undef
if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+ return DAG.getUNDEF(VT);
// fold (sra x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
@@ -2679,7 +2679,7 @@
return N0;
// fold (srl x, c >= size(x)) -> undef
if (N1C && N1C->getZExtValue() >= OpSizeInBits)
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+ return DAG.getUNDEF(VT);
// fold (srl x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
@@ -2704,7 +2704,7 @@
// Shifting in all undef bits?
MVT SmallVT = N0.getOperand(0).getValueType();
if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+ return DAG.getUNDEF(VT);
SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
N0.getOperand(0), N1);
@@ -3909,7 +3909,7 @@
}
if (EltIsUndef)
- Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT));
+ Ops.push_back(DAG.getUNDEF(DstEltVT));
else
Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
}
@@ -3929,7 +3929,7 @@
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
for (unsigned j = 0; j != NumOutputsPerInput; ++j)
- Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT));
+ Ops.push_back(DAG.getUNDEF(DstEltVT));
continue;
}
@@ -4075,7 +4075,8 @@
if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
- DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
+ DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
+ N0.getOperand(1), N1));
return SDValue();
}
@@ -4809,16 +4810,14 @@
// Indexed loads.
assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
- SDValue Undef = DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- N->getValueType(0));
+ SDValue Undef = DAG.getUNDEF(N->getValueType(0));
DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
DOUT << " and 2 other values\n";
WorkListRemover DeadNodes(*this);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
- DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- N->getValueType(1)),
+ DAG.getUNDEF(N->getValueType(1)),
&DeadNodes);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
removeFromWorkList(N);
@@ -5239,9 +5238,7 @@
SmallVector<SDValue, 8> BuildVecIndices;
for (unsigned i = 0; i != NumInScalars; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
- BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF,
- N->getDebugLoc(),
- TLI.getPointerTy()));
+ BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy()));
continue;
}
@@ -5272,8 +5269,7 @@
} else {
// Use an undef build_vector as input for the second operand.
std::vector<SDValue> UnOps(NumInScalars,
- DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- EltType));
+ DAG.getUNDEF(EltType));
Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
&UnOps[0], UnOps.size());
AddToWorkList(Ops[1].getNode());
@@ -5429,8 +5425,7 @@
AddToWorkList(ShufMask.getNode());
return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
N->getValueType(0), N0,
- DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- N->getValueType(0)),
+ DAG.getUNDEF(N->getValueType(0)),
ShufMask);
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Feb 14 07:20:23 2009
@@ -345,15 +345,14 @@
SDValue InOp = Mask.getOperand(i);
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
if (InOp.getOpcode() == ISD::UNDEF)
- Ops.push_back(DAG.getNode(ISD::UNDEF,
- InOp.getNode()->getDebugLoc(), EltVT));
+ Ops.push_back(DAG.getUNDEF(EltVT));
else {
unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
}
}
}
- Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(),
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
NVT, &Ops[0], Ops.size());
}
VT = NVT;
@@ -556,6 +555,7 @@
static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
SelectionDAG &DAG, const TargetLowering &TLI) {
bool Extend = false;
+ DebugLoc dl = CFP->getDebugLoc();
// If a FP immediate is precise when represented as a float and if the
// target can do an extending load from float to double, we put it into
@@ -591,10 +591,11 @@
SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
if (Extend)
- return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
+ return DAG.getExtLoad(ISD::EXTLOAD, dl,
+ OrigVT, DAG.getEntryNode(),
CPIdx, PseudoSourceValue::getConstantPool(),
0, VT, false, Alignment);
- return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
+ return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0, false, Alignment);
}
@@ -892,7 +893,7 @@
"Can't unroll a vector with multiple results!");
unsigned NE = VT.getVectorNumElements();
MVT EltVT = VT.getVectorElementType();
- DebugLoc dl = Op.getNode()->getDebugLoc();
+ DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 8> Scalars;
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
@@ -1114,7 +1115,7 @@
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
unsigned Reg = TLI.getExceptionAddressRegister();
- Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
+ Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
}
break;
case TargetLowering::Custom:
@@ -1148,7 +1149,7 @@
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
unsigned Reg = TLI.getExceptionSelectorRegister();
- Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
+ Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
}
break;
case TargetLowering::Custom:
@@ -1736,7 +1737,7 @@
for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
- Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+ Ops.push_back(DAG.getUNDEF(EltVT));
} else {
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
@@ -1919,7 +1920,7 @@
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
SDValue Size = Tmp2.getOperand(1);
- SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
+ SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
Chain = SP.getValue(1);
unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
unsigned StackAlign =
@@ -1928,7 +1929,7 @@
SP = DAG.getNode(ISD::AND, dl, VT, SP,
DAG.getConstant(-(uint64_t)Align, VT));
Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
- Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
+ Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
DAG.getIntPtrConstant(0, true), SDValue());
@@ -2188,7 +2189,7 @@
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
- Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
+ Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
Tmp4 = LegalizeOp(Tmp1.getValue(1));
break;
}
@@ -2890,11 +2891,11 @@
// Expand to CopyFromReg if the target set
// StackPointerRegisterToSaveRestore.
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
- Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
+ Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
Node->getValueType(0));
Tmp2 = Tmp1.getValue(1);
} else {
- Tmp1 = DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0));
+ Tmp1 = DAG.getUNDEF(Node->getValueType(0));
Tmp2 = Node->getOperand(0);
}
break;
@@ -2922,7 +2923,7 @@
// Expand to CopyToReg if the target set
// StackPointerRegisterToSaveRestore.
if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
- Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
+ Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
} else {
Result = Tmp1;
}
@@ -3428,7 +3429,7 @@
// Select between the nabs and abs value based on the sign bit of
// the input.
Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
- DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
+ DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
AbsVal),
AbsVal);
Result = LegalizeOp(Result);
@@ -4037,7 +4038,7 @@
Result = PromoteOp(Node->getOperand(0));
// For FP, make Op1 a i32
- Result = DAG.getConvertRndSat(Op.getValueType(), Result,
+ Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
DTyOp, STyOp, RndOp, SatOp, CvtCode);
break;
}
@@ -4530,7 +4531,7 @@
assert(0 && "Do not know how to promote this operator!");
abort();
case ISD::UNDEF:
- Result = DAG.getNode(ISD::UNDEF, dl, NVT);
+ Result = DAG.getUNDEF(NVT);
break;
case ISD::Constant:
if (VT != MVT::i1)
@@ -4601,7 +4602,7 @@
CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
"can only promote integers");
- Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
+ Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
Node->getOperand(1), Node->getOperand(2),
Node->getOperand(3), Node->getOperand(4),
CvtCode);
@@ -4885,11 +4886,11 @@
Tmp1 = Node->getOperand(0); // Get the chain.
Tmp2 = Node->getOperand(1); // Get the pointer.
if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
- Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
+ Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
Result = TLI.LowerOperation(Tmp3, DAG);
} else {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
+ SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(VT.getSizeInBits()/8,
@@ -5000,7 +5001,7 @@
// lower to a store then an indexed load.
SDValue Vec = Op.getOperand(0);
SDValue Idx = Op.getOperand(1);
- DebugLoc dl = Op.getNode()->getDebugLoc();
+ DebugLoc dl = Op.getDebugLoc();
MVT TVT = Vec.getValueType();
unsigned NumElems = TVT.getVectorNumElements();
@@ -5512,7 +5513,7 @@
if (isOnlyLowElement) {
// If the low element is an undef too, then this whole things is an undef.
if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
- return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0));
+ return DAG.getUNDEF(Node->getValueType(0));
// Otherwise, turn this into a scalar_to_vector node.
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
Node->getOperand(0));
@@ -5562,7 +5563,7 @@
// Return shuffle(LowValVec, undef, <0,0,0,0>)
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
Node->getValueType(0), LowValVec,
- DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
+ DAG.getUNDEF(Node->getValueType(0)),
SplatMask);
}
}
@@ -5600,7 +5601,7 @@
if (Val2.getOpcode() != ISD::UNDEF)
MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
else
- MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT);
+ MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
@@ -5986,7 +5987,7 @@
case TargetLowering::Expand:
break; // This case is handled below.
case TargetLowering::Custom: {
- SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
+ SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
Source), DAG);
if (NV.getNode())
return LegalizeOp(NV);
@@ -6374,7 +6375,8 @@
VT.getVectorElementType().getSizeInBits() : len;
SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
- Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
+ Op = DAG.getNode(ISD::ADD, dl, VT,
+ DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
Tmp2));
@@ -6397,7 +6399,7 @@
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, dl, VT, Op,
- DAG.getNode(ISD::SRL, VT, Op, Tmp3));
+ DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
}
Op = DAG.getNOT(dl, Op, VT);
return DAG.getNode(ISD::CTPOP, dl, VT, Op);
@@ -6480,8 +6482,8 @@
Lo = ExpandEXTRACT_VECTOR_ELT(Op);
return ExpandOp(Lo, Lo, Hi);
case ISD::UNDEF:
- Lo = DAG.getNode(ISD::UNDEF, dl, NVT);
- Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+ Lo = DAG.getUNDEF(NVT);
+ Hi = DAG.getUNDEF(NVT);
break;
case ISD::Constant: {
unsigned NVTBits = NVT.getSizeInBits();
@@ -6586,8 +6588,8 @@
case ISD::VAARG: {
SDValue Ch = Node->getOperand(0); // Legalize the chain.
SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
- Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
- Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
+ Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
+ Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
// Remember that we legalized the chain.
Hi = LegalizeOp(Hi);
@@ -6674,7 +6676,7 @@
Hi = DAG.getConstant(0, NVT);
} else /* if (ExtType == ISD::EXTLOAD) */ {
// The high part is undefined.
- Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+ Hi = DAG.getUNDEF(NVT);
}
}
break;
@@ -6717,7 +6719,7 @@
// The low part is any extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
// The high part is undefined.
- Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+ Hi = DAG.getUNDEF(NVT);
break;
case ISD::SIGN_EXTEND: {
// The low part is just a sign extension of the input (which degenerates to
@@ -6944,7 +6946,7 @@
// If the target wants custom lowering, do so.
SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
- SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
+ SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
Op = TLI.LowerOperation(Op, DAG);
if (Op.getNode()) {
// Now that the custom expander is done, expand the result, which is
@@ -7513,8 +7515,8 @@
#endif
assert(0 && "Unhandled operation in SplitVectorOp!");
case ISD::UNDEF:
- Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo);
- Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi);
+ Lo = DAG.getUNDEF(NewVT_Lo);
+ Hi = DAG.getUNDEF(NewVT_Hi);
break;
case ISD::BUILD_PAIR:
Lo = Node->getOperand(0);
@@ -7551,7 +7553,7 @@
for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
SDValue IdxNode = Mask.getOperand(i);
if (IdxNode.getOpcode() == ISD::UNDEF) {
- Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
+ Ops.push_back(DAG.getUNDEF(NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
@@ -7569,7 +7571,7 @@
for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
SDValue IdxNode = Mask.getOperand(i);
if (IdxNode.getOpcode() == ISD::UNDEF) {
- Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
+ Ops.push_back(DAG.getUNDEF(NewEltVT));
continue;
}
unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
@@ -7752,9 +7754,9 @@
SDValue RndOp = Node->getOperand(3);
SDValue SatOp = Node->getOperand(4);
- Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
+ Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
RndOp, SatOp, CvtCode);
- Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
+ Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
RndOp, SatOp, CvtCode);
break;
}
@@ -7770,7 +7772,7 @@
bool isVolatile = LD->isVolatile();
assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
- SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
+ SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
MVT MemNewEltVT = MemoryVT.getVectorElementType();
MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
@@ -7900,7 +7902,7 @@
break;
case ISD::CONVERT_RNDSAT: {
SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
- Result = DAG.getConvertRndSat(NewVT, Op0,
+ Result = DAG.getConvertRndSat(NewVT, dl, Op0,
DAG.getValueType(NewVT),
DAG.getValueType(Op0.getValueType()),
Node->getOperand(3),
@@ -7927,7 +7929,7 @@
bool isVolatile = LD->isVolatile();
assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
- SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
+ SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
NewVT, Ch, Ptr, Offset, SV, SVOffset,
@@ -8049,13 +8051,13 @@
assert(0 && "Unexpected operation in WidenVectorOp!");
break;
case ISD::UNDEF:
- Result = DAG.getNode(ISD::UNDEF, dl, WidenVT);
+ Result = DAG.getUNDEF(WidenVT);
break;
case ISD::BUILD_VECTOR: {
// Build a vector with undefined for the new nodes
SDValueVector NewOps(Node->op_begin(), Node->op_end());
for (unsigned i = NumElts; i < NewNumElts; ++i) {
- NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT));
+ NewOps.push_back(DAG.getUNDEF(EVT));
}
Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
&NewOps[0], NewOps.size());
@@ -8092,7 +8094,7 @@
}
}
for (unsigned i = NumElts; i < NewNumElts; ++i) {
- NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT));
+ NewOps.push_back(DAG.getUNDEF(PVT));
}
SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
@@ -8137,7 +8139,7 @@
"can not widen bit convert that are not multiple of element type");
unsigned NewNumElts = WidenSize / InSize;
SmallVector<SDValue, 16> Ops(NewNumElts);
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+ SDValue UndefVal = DAG.getUNDEF(InVT);
Ops[0] = Tmp1;
for (unsigned i = 1; i < NewNumElts; ++i)
Ops[i] = UndefVal;
@@ -8207,7 +8209,7 @@
SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
- Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
+ Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
RndOp, SatOp, CvtCode);
break;
}
@@ -8266,7 +8268,7 @@
// We could widen on a multiple of the incoming operand if necessary.
unsigned NumConcat = NewNumElts / NumElts;
assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
+ SDValue UndefVal = DAG.getUNDEF(VT);
SmallVector<SDValue, 8> MOps;
MOps.push_back(Op);
for (unsigned i = 1; i != NumConcat; ++i) {
@@ -8296,7 +8298,7 @@
} else if (NewNumElts % NumElts == 0) {
// Widen the extracted subvector.
unsigned NumConcat = NewNumElts / NumElts;
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
+ SDValue UndefVal = DAG.getUNDEF(VT);
SmallVector<SDValue, 8> MOps;
MOps.push_back(Op);
for (unsigned i = 1; i != NumConcat; ++i) {
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Sat Feb 14 07:20:23 2009
@@ -1107,7 +1107,7 @@
MVT::i64, Src);
LC = RTLIB::SINTTOFP_I64_PPCF128;
} else if (SrcVT.bitsLE(MVT::i128)) {
- Src = DAG.getNode(ISD::SIGN_EXTEND, MVT::i128, Src);
+ Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
LC = RTLIB::SINTTOFP_I128_PPCF128;
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sat Feb 14 07:20:23 2009
@@ -150,8 +150,8 @@
SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
SDValue Op2 = GetPromotedInteger(N->getOperand(2));
SDValue Op3 = GetPromotedInteger(N->getOperand(3));
- SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(),
- N->getChain(), N->getBasePtr(),
+ SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
+ N->getMemoryVT(), N->getChain(), N->getBasePtr(),
Op2, Op3, N->getSrcValue(), N->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
@@ -246,10 +246,12 @@
SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
MVT VT = N->getValueType(0);
+ // FIXME there is no actual debug info here
+ DebugLoc dl = N->getDebugLoc();
// Zero extend things like i1, sign extend everything else. It shouldn't
// matter in theory which one we pick, but this tends to give better code?
unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
+ SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
SDValue(N, 0));
assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
return Result;
@@ -262,7 +264,7 @@
CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
"can only promote integers");
MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
- return DAG.getConvertRndSat(OutVT, N->getOperand(0),
+ return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
N->getOperand(1), N->getOperand(2),
N->getOperand(3), N->getOperand(4), CvtCode);
}
@@ -270,11 +272,12 @@
SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
// Zero extend to the promoted type and do the count there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
+ DebugLoc dl = N->getDebugLoc();
MVT OVT = N->getValueType(0);
MVT NVT = Op.getValueType();
- Op = DAG.getNode(ISD::CTLZ, NVT, Op);
+ Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
// Subtract off the extra leading bits in the bigger type.
- return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op,
+ return DAG.getNode(ISD::SUB, dl, NVT, Op,
DAG.getConstant(NVT.getSizeInBits() -
OVT.getSizeInBits(), NVT));
}
@@ -389,7 +392,7 @@
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
DAG.getValueType(N->getOperand(0).getValueType()));
if (N->getOpcode() == ISD::ZERO_EXTEND)
- return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
+ return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
return Res;
}
@@ -573,7 +576,7 @@
// Calculate the overflow flag: zero extend the arithmetic result from
// the original type.
- SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT);
+ SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
// Overflowed if and only if this is not equal to Res.
Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
@@ -592,8 +595,7 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- TLI.getTypeToTransformTo(N->getValueType(0)));
+ return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
}
SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
@@ -608,7 +610,7 @@
SmallVector<SDValue, 8> Parts(NumRegs);
for (unsigned i = 0; i < NumRegs; ++i) {
- Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2));
+ Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
Chain = Parts[i].getValue(1);
}
@@ -823,7 +825,7 @@
CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
"can only promote integer arguments");
SDValue InOp = GetPromotedInteger(N->getOperand(0));
- return DAG.getConvertRndSat(N->getValueType(0), InOp,
+ return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
N->getOperand(1), N->getOperand(2),
N->getOperand(3), N->getOperand(4), CvtCode);
}
@@ -853,10 +855,11 @@
SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
SDValue NewOps[6];
+ DebugLoc dl = N->getDebugLoc();
NewOps[0] = N->getOperand(0);
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
SDValue Flag = GetPromotedInteger(N->getOperand(i));
- NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
+ NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
}
return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
array_lengthof(NewOps));
@@ -941,9 +944,10 @@
}
SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
+ DebugLoc dl = N->getDebugLoc();
SDValue Op = GetPromotedInteger(N->getOperand(0));
- Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
- return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
+ Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
+ return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
}
@@ -1108,7 +1112,7 @@
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else {
- Lo = DAG.getNode(ISD::OR, NVT,
+ Lo = DAG.getNode(ISD::OR, dl, NVT,
DAG.getNode(ISD::SRL, dl, NVT, InL,
DAG.getConstant(Amt, ShTy)),
DAG.getNode(ISD::SHL, dl, NVT, InH,
@@ -1248,7 +1252,7 @@
Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
SDValue Cmp =
- DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()),
+ DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
LoOps[0], LoOps[1], ISD::SETULT);
SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
DAG.getConstant(1, NVT),
@@ -1312,7 +1316,7 @@
if (Op.getValueType().bitsLE(NVT)) {
// The low part is any extension of the input (which degenerates to a copy).
Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
- Hi = DAG.getNode(ISD::UNDEF, dl, NVT); // The high part is undefined.
+ Hi = DAG.getUNDEF(NVT); // The high part is undefined.
} else {
// For example, extension of an i48 to an i64. The operand type necessarily
// promotes to the result type, so will end up being expanded too.
@@ -1407,7 +1411,7 @@
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
MVT NVT = Lo.getValueType();
- Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
+ Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
Hi = DAG.getConstant(0, NVT);
}
@@ -1493,7 +1497,7 @@
} else {
assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
// The high part is undefined.
- Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+ Hi = DAG.getUNDEF(NVT);
}
} else if (TLI.isLittleEndian()) {
// Little-endian - low bits are at low addresses.
@@ -1905,7 +1909,7 @@
SplitInteger(Res, Lo, Hi);
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
- Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
+ Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
}
}
@@ -2203,7 +2207,7 @@
DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
TLI.getPointerTy()));
Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
- DAG.getNode(ISD::SRL, NVT, Lo,
+ DAG.getNode(ISD::SRL, dl, NVT, Lo,
DAG.getConstant(ExcessBits,
TLI.getPointerTy())));
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Sat Feb 14 07:20:23 2009
@@ -852,13 +852,13 @@
/// BitConvertToInteger - Convert to an integer of the same size.
SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
unsigned BitWidth = Op.getValueType().getSizeInBits();
- return DAG.getNode(ISD::BIT_CONVERT, Op.getNode()->getDebugLoc(),
+ return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
MVT::getIntegerVT(BitWidth), Op);
}
SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
MVT DestVT) {
- DebugLoc dl = Op.getNode()->getDebugLoc();
+ DebugLoc dl = Op.getDebugLoc();
// Create the stack frame object. Make sure it is aligned for both
// the source and destination types.
SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT);
@@ -922,7 +922,7 @@
SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
SDValue Index) {
- DebugLoc dl = Index.getNode()->getDebugLoc();
+ DebugLoc dl = Index.getDebugLoc();
// Make sure the index type is big enough to compute in.
if (Index.getValueType().bitsGT(TLI.getPointerTy()))
Index = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Index);
@@ -940,8 +940,8 @@
/// JoinIntegers - Build an integer with low bits Lo and high bits Hi.
SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
// Arbitrarily use dlHi for result DebugLoc
- DebugLoc dlHi = Hi.getNode()->getDebugLoc();
- DebugLoc dlLo = Lo.getNode()->getDebugLoc();
+ DebugLoc dlHi = Hi.getDebugLoc();
+ DebugLoc dlLo = Lo.getDebugLoc();
MVT LVT = Lo.getValueType();
MVT HVT = Hi.getValueType();
MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
@@ -1004,7 +1004,7 @@
/// of the given type. A target boolean is an integer value, not necessarily of
/// type i1, the bits of which conform to getBooleanContents.
SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) {
- DebugLoc dl = Bool.getNode()->getDebugLoc();
+ DebugLoc dl = Bool.getDebugLoc();
ISD::NodeType ExtendCode;
switch (TLI.getBooleanContents()) {
default:
@@ -1031,7 +1031,7 @@
void DAGTypeLegalizer::SplitInteger(SDValue Op,
MVT LoVT, MVT HiVT,
SDValue &Lo, SDValue &Hi) {
- DebugLoc dl = Op.getNode()->getDebugLoc();
+ DebugLoc dl = Op.getDebugLoc();
assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
Op.getValueType().getSizeInBits() && "Invalid integer splitting!");
Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op);
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypes.h Sat Feb 14 07:20:23 2009
@@ -231,8 +231,9 @@
/// final size.
SDValue SExtPromotedInteger(SDValue Op) {
MVT OldVT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
- return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
DAG.getValueType(OldVT));
}
@@ -240,8 +241,9 @@
/// final size.
SDValue ZExtPromotedInteger(SDValue Op) {
MVT OldVT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
- return DAG.getZeroExtendInReg(Op, OldVT);
+ return DAG.getZeroExtendInReg(Op, dl, OldVT);
}
// Integer Result Promotion.
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Sat Feb 14 07:20:23 2009
@@ -154,7 +154,7 @@
if (Idx.getValueType().bitsLT(TLI.getPointerTy()))
Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
- Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx);
+ Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
@@ -209,9 +209,10 @@
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Chain = N->getOperand(0);
SDValue Ptr = N->getOperand(1);
+ DebugLoc dl = N->getDebugLoc();
- Lo = DAG.getVAArg(NVT, Chain, Ptr, N->getOperand(2));
- Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, N->getOperand(2));
+ Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2));
+ Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2));
// Handle endianness of the load.
if (TLI.isBigEndian())
@@ -331,7 +332,7 @@
unsigned NumElts = VT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(NumElts);
Ops[0] = N->getOperand(0);
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, Ops[0].getValueType());
+ SDValue UndefVal = DAG.getUNDEF(Ops[0].getValueType());
for (unsigned i = 1; i < NumElts; ++i)
Ops[i] = UndefVal;
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
@@ -432,6 +433,6 @@
MVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
- Lo = DAG.getNode(ISD::UNDEF, dl, LoVT);
- Hi = DAG.getNode(ISD::UNDEF, dl, HiVT);
+ Lo = DAG.getUNDEF(LoVT);
+ Hi = DAG.getUNDEF(HiVT);
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Sat Feb 14 07:20:23 2009
@@ -126,7 +126,8 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
MVT NewVT = N->getValueType(0).getVectorElementType();
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
- return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
+ return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
+ Op0, DAG.getValueType(NewVT),
DAG.getValueType(Op0.getValueType()),
N->getOperand(3),
N->getOperand(4),
@@ -163,8 +164,7 @@
N->getExtensionType(),
N->getValueType(0).getVectorElementType(),
N->getChain(), N->getBasePtr(),
- DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- N->getBasePtr().getValueType()),
+ DAG.getUNDEF(N->getBasePtr().getValueType()),
N->getSrcValue(), N->getSrcValueOffset(),
N->getMemoryVT().getVectorElementType(),
N->isVolatile(), N->getAlignment());
@@ -202,16 +202,14 @@
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- N->getValueType(0).getVectorElementType());
+ return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
// Figure out if the scalar is the LHS or RHS and return it.
SDValue Arg = N->getOperand(2).getOperand(0);
if (Arg.getOpcode() == ISD::UNDEF)
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
- N->getValueType(0).getVectorElementType());
+ return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
return GetScalarizedVector(N->getOperand(Op));
}
@@ -533,6 +531,7 @@
void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
MVT LoVT, HiVT;
+ DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SDValue VLo, VHi;
GetSplitVector(N->getOperand(0), VLo, VHi);
@@ -545,8 +544,10 @@
SDValue SatOp = N->getOperand(4);
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
- Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
- Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
+ Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
+ CvtCode);
+ Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
+ CvtCode);
}
void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
@@ -628,7 +629,7 @@
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
- Hi = DAG.getNode(ISD::UNDEF, dl, HiVT);
+ Hi = DAG.getUNDEF(HiVT);
}
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
@@ -641,7 +642,7 @@
ISD::LoadExtType ExtType = LD->getExtensionType();
SDValue Ch = LD->getChain();
SDValue Ptr = LD->getBasePtr();
- SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
MVT MemoryVT = LD->getMemoryVT();
@@ -743,7 +744,7 @@
if (Input >= array_lengthof(Inputs)) {
// The mask element does not index into any input vector.
- Ops.push_back(DAG.getNode(ISD::UNDEF, dl, IdxVT));
+ Ops.push_back(DAG.getUNDEF(IdxVT));
continue;
}
@@ -791,7 +792,7 @@
if (Input >= array_lengthof(Inputs)) {
// The mask element is "undef" or indexes off the end of the input.
- Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+ Ops.push_back(DAG.getUNDEF(EltVT));
continue;
}
@@ -807,7 +808,7 @@
Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, &Ops[0], Ops.size());
} else if (InputUsed[0] == -1U) {
// No input vectors were used! The result is undefined.
- Output = DAG.getNode(ISD::UNDEF, dl, NewVT);
+ Output = DAG.getUNDEF(NewVT);
} else {
// At least one input vector was used. Create a new shuffle vector.
SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
@@ -816,7 +817,7 @@
SDValue Op0 = Inputs[InputUsed[0]];
// If only one input was used, use an undefined vector for the other.
SDValue Op1 = InputUsed[1] == -1U ?
- DAG.getNode(ISD::UNDEF, dl, NewVT) : Inputs[InputUsed[1]];
+ DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
Output = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, Op0, Op1, NewMask);
}
@@ -1071,7 +1072,7 @@
for (unsigned i = 0; i < MaskLength; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
- Ops[i] = DAG.getNode(ISD::UNDEF, dl, OpVT);
+ Ops[i] = DAG.getUNDEF(OpVT);
} else {
uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
Ops[i] = DAG.getConstant(Idx, OpVT);
@@ -1215,7 +1216,7 @@
unsigned NumConcat = WidenNumElts/InVTNumElts;
SmallVector<SDValue, 16> Ops(NumConcat);
Ops[0] = InOp;
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+ SDValue UndefVal = DAG.getUNDEF(InVT);
for (unsigned i = 1; i != NumConcat; ++i)
Ops[i] = UndefVal;
return DAG.getNode(Opcode, dl, WidenVT,
@@ -1241,7 +1242,7 @@
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
DAG.getIntPtrConstant(i)));
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+ SDValue UndefVal = DAG.getUNDEF(EltVT);
for (; i < WidenNumElts; ++i)
Ops[i] = UndefVal;
@@ -1333,7 +1334,7 @@
// and then widening it. To avoid this, we widen the input only if
// it results in a legal type.
SmallVector<SDValue, 16> Ops(NewNumElts);
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
+ SDValue UndefVal = DAG.getUNDEF(InVT);
Ops[0] = InOp;
for (unsigned i = 1; i < NewNumElts; ++i)
Ops[i] = UndefVal;
@@ -1376,7 +1377,7 @@
SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
NewOps.reserve(WidenNumElts);
for (unsigned i = NumElts; i < WidenNumElts; ++i)
- NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+ NewOps.push_back(DAG.getUNDEF(EltVT));
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
}
@@ -1394,7 +1395,7 @@
// Add undef vectors to widen to correct length.
unsigned NumConcat = WidenVT.getVectorNumElements() /
InVT.getVectorNumElements();
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+ SDValue UndefVal = DAG.getUNDEF(InVT);
SmallVector<SDValue, 16> Ops(NumConcat);
for (unsigned i=0; i < NumOperands; ++i)
Ops[i] = N->getOperand(i);
@@ -1447,13 +1448,14 @@
Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
DAG.getIntPtrConstant(j));
}
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+ SDValue UndefVal = DAG.getUNDEF(EltVT);
for (; Idx < WidenNumElts; ++Idx)
Ops[Idx] = UndefVal;
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
}
SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
+ DebugLoc dl = N->getDebugLoc();
SDValue InOp = N->getOperand(0);
SDValue RndOp = N->getOperand(3);
SDValue SatOp = N->getOperand(4);
@@ -1475,7 +1477,7 @@
InVT = InOp.getValueType();
InVTNumElts = InVT.getVectorNumElements();
if (InVTNumElts == WidenNumElts)
- return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
+ return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
SatOp, CvtCode);
}
@@ -1490,20 +1492,20 @@
unsigned NumConcat = WidenNumElts/InVTNumElts;
SmallVector<SDValue, 16> Ops(NumConcat);
Ops[0] = InOp;
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
+ SDValue UndefVal = DAG.getUNDEF(InVT);
for (unsigned i = 1; i != NumConcat; ++i) {
Ops[i] = UndefVal;
}
- InOp = DAG.getNode(ISD::CONCAT_VECTORS, InWidenVT, &Ops[0], NumConcat);
- return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
+ InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
+ return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
SatOp, CvtCode);
}
if (InVTNumElts % WidenNumElts == 0) {
// Extract the input and convert the shorten input vector.
- InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InWidenVT, InOp,
+ InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
DAG.getIntPtrConstant(0));
- return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
+ return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
SatOp, CvtCode);
}
}
@@ -1517,17 +1519,17 @@
unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
unsigned i;
for (i=0; i < MinElts; ++i) {
- SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp,
+ SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
DAG.getIntPtrConstant(i));
- Ops[i] = DAG.getConvertRndSat(WidenVT, ExtVal, DTyOp, STyOp, RndOp,
+ Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
SatOp, CvtCode);
}
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
+ SDValue UndefVal = DAG.getUNDEF(EltVT);
for (; i < WidenNumElts; ++i)
Ops[i] = UndefVal;
- return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
}
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
@@ -1577,7 +1579,7 @@
}
}
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+ SDValue UndefVal = DAG.getUNDEF(EltVT);
for (; i < WidenNumElts; ++i)
Ops[i] = UndefVal;
return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
@@ -1633,7 +1635,7 @@
}
// Fill the rest with undefs
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+ SDValue UndefVal = DAG.getUNDEF(EltVT);
for (; i != WidenNumElts; ++i)
Ops[i] = UndefVal;
@@ -1701,7 +1703,7 @@
SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), WidenVT);
+ return DAG.getUNDEF(WidenVT);
}
SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
@@ -1732,7 +1734,7 @@
}
}
for (unsigned i = NumElts; i < WidenNumElts; ++i)
- MaskOps[i] = DAG.getNode(ISD::UNDEF, dl, IdxVT);
+ MaskOps[i] = DAG.getUNDEF(IdxVT);
SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
MVT::getVectorVT(IdxVT, WidenNumElts),
&MaskOps[0], WidenNumElts);
@@ -2142,7 +2144,7 @@
MVT InVT = InOp.getValueType();
assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match");
- DebugLoc dl = InOp.getNode()->getDebugLoc();
+ DebugLoc dl = InOp.getDebugLoc();
// Check if InOp already has the right width.
if (InVT == NVT)
@@ -2153,7 +2155,7 @@
if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
unsigned NumConcat = WidenNumElts / InNumElts;
SmallVector<SDValue, 16> Ops(NumConcat);
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+ SDValue UndefVal = DAG.getUNDEF(InVT);
Ops[0] = InOp;
for (unsigned i = 1; i != NumConcat; ++i)
Ops[i] = UndefVal;
@@ -2174,7 +2176,7 @@
Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
DAG.getIntPtrConstant(Idx));
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+ SDValue UndefVal = DAG.getUNDEF(EltVT);
for ( ; Idx < WidenNumElts; ++Idx)
Ops[Idx] = UndefVal;
return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Feb 14 07:20:23 2009
@@ -786,10 +786,11 @@
return TLI.getTargetData()->getABITypeAlignment(Ty);
}
+// EntryNode could meaningfully have debug info if we can find it...
SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
: TLI(tli), FLI(fli), DW(0),
- EntryNode(ISD::EntryToken, getVTList(MVT::Other)),
- Root(getEntryNode()) {
+ EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
+ getVTList(MVT::Other)), Root(getEntryNode()) {
AllNodes.push_back(&EntryNode);
}
@@ -829,14 +830,6 @@
Root = getEntryNode();
}
-SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) {
- if (Op.getValueType() == VT) return Op;
- APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
- VT.getSizeInBits());
- return getNode(ISD::AND, Op.getValueType(), Op,
- getConstant(Imm, Op.getValueType()));
-}
-
SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
if (Op.getValueType() == VT) return Op;
APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
@@ -900,7 +893,8 @@
if (VT.isVector()) {
SmallVector<SDValue, 8> Ops;
Ops.assign(VT.getVectorNumElements(), Result);
- Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
+ Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
+ VT, &Ops[0], Ops.size());
}
return Result;
}
@@ -943,7 +937,9 @@
if (VT.isVector()) {
SmallVector<SDValue, 8> Ops;
Ops.assign(VT.getVectorNumElements(), Result);
- Result = getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
+ // FIXME DebugLoc info might be appropriate here
+ Result = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(),
+ VT, &Ops[0], Ops.size());
}
return Result;
}
@@ -1068,7 +1064,6 @@
return SDValue(N, 0);
}
-
SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
@@ -1083,20 +1078,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl) {
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
- ID.AddPointer(MBB);
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode *N = NodeAllocator.Allocate<BasicBlockSDNode>();
- new (N) BasicBlockSDNode(MBB, dl);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
@@ -1134,15 +1115,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT) {
- SDNode *&N = ExternalSymbols[Sym];
- if (N) return SDValue(N, 0);
- N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
- new (N) ExternalSymbolSDNode(false, dl, Sym, VT);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT) {
SDNode *&N = TargetExternalSymbols[Sym];
if (N) return SDValue(N, 0);
@@ -1152,16 +1124,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, DebugLoc dl,
- MVT VT) {
- SDNode *&N = TargetExternalSymbols[Sym];
- if (N) return SDValue(N, 0);
- N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
- new (N) ExternalSymbolSDNode(true, dl, Sym, VT);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
if ((unsigned)Cond >= CondCodeNodes.size())
CondCodeNodes.resize(Cond+1);
@@ -1175,7 +1137,8 @@
return SDValue(CondCodeNodes[Cond], 0);
}
-SDValue SelectionDAG::getConvertRndSat(MVT VT, SDValue Val, SDValue DTy,
+SDValue SelectionDAG::getConvertRndSat(MVT VT,
+ SDValue Val, SDValue DTy,
SDValue STy, SDValue Rnd, SDValue Sat,
ISD::CvtCode Code) {
// If the src and dest types are the same and the conversion is between
@@ -1219,23 +1182,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getLabel(unsigned Opcode,
- SDValue Root,
- unsigned LabelID) {
- FoldingSetNodeID ID;
- SDValue Ops[] = { Root };
- AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
- ID.AddInteger(LabelID);
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode *N = NodeAllocator.Allocate<LabelSDNode>();
- new (N) LabelSDNode(Opcode, Root, LabelID);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl,
SDValue Root,
unsigned LabelID) {
@@ -1302,7 +1248,7 @@
if (OpTy == ShTy || OpTy.isVector()) return Op;
ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
- return getNode(Opcode, ShTy, Op);
+ return getNode(Opcode, Op.getDebugLoc(), ShTy, Op);
}
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
@@ -1388,29 +1334,29 @@
switch (Cond) {
default: break;
case ISD::SETEQ: if (R==APFloat::cmpUnordered)
- return getNode(ISD::UNDEF, dl, VT);
+ return getUNDEF(VT);
// fall through
case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
case ISD::SETNE: if (R==APFloat::cmpUnordered)
- return getNode(ISD::UNDEF, dl, VT);
+ return getUNDEF(VT);
// fall through
case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpLessThan, VT);
case ISD::SETLT: if (R==APFloat::cmpUnordered)
- return getNode(ISD::UNDEF, dl, VT);
+ return getUNDEF(VT);
// fall through
case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
case ISD::SETGT: if (R==APFloat::cmpUnordered)
- return getNode(ISD::UNDEF, dl, VT);
+ return getUNDEF(VT);
// fall through
case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
case ISD::SETLE: if (R==APFloat::cmpUnordered)
- return getNode(ISD::UNDEF, dl, VT);
+ return getUNDEF(VT);
// fall through
case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
R==APFloat::cmpEqual, VT);
case ISD::SETGE: if (R==APFloat::cmpUnordered)
- return getNode(ISD::UNDEF, dl, VT);
+ return getUNDEF(VT);
// fall through
case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
R==APFloat::cmpEqual, VT);
@@ -2155,7 +2101,7 @@
SDValue PermMask = N->getOperand(2);
SDValue Idx = PermMask.getOperand(i);
if (Idx.getOpcode() == ISD::UNDEF)
- return getNode(ISD::UNDEF, dl, VT.getVectorElementType());
+ return getUNDEF(VT.getVectorElementType());
unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
unsigned NumElems = PermMask.getNumOperands();
SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
@@ -2169,7 +2115,7 @@
}
if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
return (Index == 0) ? V.getOperand(0)
- : getNode(ISD::UNDEF, dl, VT.getVectorElementType());
+ : getUNDEF(VT.getVectorElementType());
if (V.getOpcode() == ISD::BUILD_VECTOR)
return V.getOperand(Index);
if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
@@ -2180,10 +2126,6 @@
/// getNode - Gets or creates the specified node.
///
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
@@ -2201,10 +2143,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT, SDValue Operand) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Operand);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
MVT VT, SDValue Operand) {
// Constant fold unary operations with an integer constant operand.
@@ -2303,7 +2241,7 @@
Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
if (Operand.getValueType() == VT) return Operand; // noop conversion.
if (Operand.getOpcode() == ISD::UNDEF)
- return getNode(ISD::UNDEF, DL, VT);
+ return getUNDEF(VT);
break;
case ISD::SIGN_EXTEND:
assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2361,14 +2299,14 @@
if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0));
if (OpOpcode == ISD::UNDEF)
- return getNode(ISD::UNDEF, DL, VT);
+ return getUNDEF(VT);
break;
case ISD::SCALAR_TO_VECTOR:
assert(VT.isVector() && !Operand.getValueType().isVector() &&
VT.getVectorElementType() == Operand.getValueType() &&
"Illegal SCALAR_TO_VECTOR node!");
if (OpOpcode == ISD::UNDEF)
- return getNode(ISD::UNDEF, DL, VT);
+ return getUNDEF(VT);
// scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
isa<ConstantSDNode>(Operand.getOperand(1)) &&
@@ -2450,11 +2388,6 @@
return SDValue();
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2) {
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
@@ -2602,7 +2535,7 @@
case ISD::EXTRACT_VECTOR_ELT:
// EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
if (N1.getOpcode() == ISD::UNDEF)
- return getNode(ISD::UNDEF, DL, VT);
+ return getUNDEF(VT);
// EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
// expanding copies of large vectors from registers.
@@ -2815,11 +2748,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3) {
// Perform various simplifications.
@@ -2901,12 +2829,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3,
- SDValue N4) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4) {
@@ -2914,12 +2836,6 @@
return getNode(Opcode, DL, VT, Ops, 4);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3,
- SDValue N4, SDValue N5) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4, N5);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4, SDValue N5) {
@@ -2929,7 +2845,8 @@
/// getMemsetValue - Vectorized representation of the memset value
/// operand.
-static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) {
+static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG,
+ DebugLoc dl) {
unsigned NumBits = VT.isVector() ?
VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
@@ -2945,11 +2862,11 @@
}
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
+ Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value);
unsigned Shift = 8;
for (unsigned i = NumBits; i > 8; i >>= 1) {
- Value = DAG.getNode(ISD::OR, VT,
- DAG.getNode(ISD::SHL, VT, Value,
+ Value = DAG.getNode(ISD::OR, dl, VT,
+ DAG.getNode(ISD::SHL, dl, VT, Value,
DAG.getConstant(Shift,
TLI.getShiftAmountTy())),
Value);
@@ -2962,7 +2879,7 @@
/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
/// used when a memcpy is turned into a memset when the source is a constant
/// string ptr.
-static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG,
+static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG,
const TargetLowering &TLI,
std::string &Str, unsigned Offset) {
// Handle vector with all elements zero.
@@ -2971,7 +2888,7 @@
return DAG.getConstant(0, VT);
unsigned NumElts = VT.getVectorNumElements();
MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
- return DAG.getNode(ISD::BIT_CONVERT, VT,
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts)));
}
@@ -2993,7 +2910,7 @@
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
SelectionDAG &DAG) {
MVT VT = Base.getValueType();
- return DAG.getNode(ISD::ADD, Base.getNode()->getDebugLoc(),
+ return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
VT, Base, DAG.getConstant(Offset, VT));
}
@@ -3106,7 +3023,7 @@
return true;
}
-static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG,
+static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Dst,
SDValue Src, uint64_t Size,
unsigned Align, bool AlwaysInline,
@@ -3143,15 +3060,15 @@
// We also handle store a vector with all zero's.
// FIXME: Handle other cases where store of vector immediate is done in
// a single instruction.
- Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
- Store = DAG.getStore(Chain, Value,
+ Value = getMemsetStringVal(VT, dl, DAG, TLI, Str, SrcOff);
+ Store = DAG.getStore(Chain, dl, Value,
getMemBasePlusOffset(Dst, DstOff, DAG),
DstSV, DstSVOff + DstOff, false, DstAlign);
} else {
- Value = DAG.getLoad(VT, Chain,
+ Value = DAG.getLoad(VT, dl, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
SrcSV, SrcSVOff + SrcOff, false, Align);
- Store = DAG.getStore(Chain, Value,
+ Store = DAG.getStore(Chain, dl, Value,
getMemBasePlusOffset(Dst, DstOff, DAG),
DstSV, DstSVOff + DstOff, false, DstAlign);
}
@@ -3160,11 +3077,11 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
-static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG,
+static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Dst,
SDValue Src, uint64_t Size,
unsigned Align, bool AlwaysInline,
@@ -3196,14 +3113,14 @@
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
- Value = DAG.getLoad(VT, Chain,
+ Value = DAG.getLoad(VT, dl, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
SrcSV, SrcSVOff + SrcOff, false, Align);
LoadValues.push_back(Value);
LoadChains.push_back(Value.getValue(1));
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&LoadChains[0], LoadChains.size());
OutChains.clear();
for (unsigned i = 0; i < NumMemOps; i++) {
@@ -3211,18 +3128,18 @@
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
- Store = DAG.getStore(Chain, LoadValues[i],
+ Store = DAG.getStore(Chain, dl, LoadValues[i],
getMemBasePlusOffset(Dst, DstOff, DAG),
DstSV, DstSVOff + DstOff, false, DstAlign);
OutChains.push_back(Store);
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
-static SDValue getMemsetStores(SelectionDAG &DAG,
+static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Dst,
SDValue Src, uint64_t Size,
unsigned Align,
@@ -3245,19 +3162,19 @@
for (unsigned i = 0; i < NumMemOps; i++) {
MVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
- SDValue Value = getMemsetValue(Src, VT, DAG);
- SDValue Store = DAG.getStore(Chain, Value,
+ SDValue Value = getMemsetValue(Src, VT, DAG, dl);
+ SDValue Store = DAG.getStore(Chain, dl, Value,
getMemBasePlusOffset(Dst, DstOff, DAG),
DstSV, DstSVOff + DstOff);
OutChains.push_back(Store);
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size());
}
-SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst,
+SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst,
SDValue Src, SDValue Size,
unsigned Align, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff,
@@ -3272,7 +3189,7 @@
return Chain;
SDValue Result =
- getMemcpyLoadsAndStores(*this, Chain, Dst, Src,
+ getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
ConstantSize->getZExtValue(),
Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.getNode())
@@ -3282,7 +3199,7 @@
// Then check to see if we should lower the memcpy with target-specific
// code. If the target chooses to do this, this is the next best.
SDValue Result =
- TLI.EmitTargetCodeForMemcpy(*this, Chain, Dst, Src, Size, Align,
+ TLI.EmitTargetCodeForMemcpy(*this, dl, Chain, Dst, Src, Size, Align,
AlwaysInline,
DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.getNode())
@@ -3292,7 +3209,7 @@
// use a (potentially long) sequence of loads and stores.
if (AlwaysInline) {
assert(ConstantSize && "AlwaysInline requires a constant size!");
- return getMemcpyLoadsAndStores(*this, Chain, Dst, Src,
+ return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src,
ConstantSize->getZExtValue(), Align, true,
DstSV, DstSVOff, SrcSV, SrcSVOff);
}
@@ -3309,11 +3226,11 @@
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
getExternalSymbol("memcpy", TLI.getPointerTy()),
- Args, *this, DebugLoc::getUnknownLoc());
+ Args, *this, dl);
return CallResult.second;
}
-SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst,
+SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst,
SDValue Src, SDValue Size,
unsigned Align,
const Value *DstSV, uint64_t DstSVOff,
@@ -3328,7 +3245,7 @@
return Chain;
SDValue Result =
- getMemmoveLoadsAndStores(*this, Chain, Dst, Src,
+ getMemmoveLoadsAndStores(*this, dl, Chain, Dst, Src,
ConstantSize->getZExtValue(),
Align, false, DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.getNode())
@@ -3338,7 +3255,7 @@
// Then check to see if we should lower the memmove with target-specific
// code. If the target chooses to do this, this is the next best.
SDValue Result =
- TLI.EmitTargetCodeForMemmove(*this, Chain, Dst, Src, Size, Align,
+ TLI.EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, Align,
DstSV, DstSVOff, SrcSV, SrcSVOff);
if (Result.getNode())
return Result;
@@ -3355,11 +3272,11 @@
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
getExternalSymbol("memmove", TLI.getPointerTy()),
- Args, *this, DebugLoc::getUnknownLoc());
+ Args, *this, dl);
return CallResult.second;
}
-SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst,
+SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
SDValue Src, SDValue Size,
unsigned Align,
const Value *DstSV, uint64_t DstSVOff) {
@@ -3373,7 +3290,7 @@
return Chain;
SDValue Result =
- getMemsetStores(*this, Chain, Dst, Src, ConstantSize->getZExtValue(),
+ getMemsetStores(*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
Align, DstSV, DstSVOff);
if (Result.getNode())
return Result;
@@ -3382,7 +3299,7 @@
// Then check to see if we should lower the memset with target-specific
// code. If the target chooses to do this, this is the next best.
SDValue Result =
- TLI.EmitTargetCodeForMemset(*this, Chain, Dst, Src, Size, Align,
+ TLI.EmitTargetCodeForMemset(*this, dl, Chain, Dst, Src, Size, Align,
DstSV, DstSVOff);
if (Result.getNode())
return Result;
@@ -3395,9 +3312,9 @@
Args.push_back(Entry);
// Extend or truncate the argument to be an i32 value for the call.
if (Src.getValueType().bitsGT(MVT::i32))
- Src = getNode(ISD::TRUNCATE, MVT::i32, Src);
+ Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
else
- Src = getNode(ISD::ZERO_EXTEND, MVT::i32, Src);
+ Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
Args.push_back(Entry);
Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
@@ -3407,39 +3324,10 @@
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
getExternalSymbol("memset", TLI.getPointerTy()),
- Args, *this, DebugLoc::getUnknownLoc());
+ Args, *this, dl);
return CallResult.second;
}
-SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT,
- SDValue Chain,
- SDValue Ptr, SDValue Cmp,
- SDValue Swp, const Value* PtrVal,
- unsigned Alignment) {
- assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
- assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
-
- MVT VT = Cmp.getValueType();
-
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(MemVT);
-
- SDVTList VTs = getVTList(VT, MVT::Other);
- FoldingSetNodeID ID;
- ID.AddInteger(MemVT.getRawBits());
- SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
- AddNodeIDNode(ID, Opcode, VTs, Ops, 4);
- void* IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
- new (N) AtomicSDNode(Opcode, VTs, MemVT,
- Chain, Ptr, Cmp, Swp, PtrVal, Alignment);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
SDValue Chain,
SDValue Ptr, SDValue Cmp,
@@ -3469,45 +3357,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getAtomic(unsigned Opcode, MVT MemVT,
- SDValue Chain,
- SDValue Ptr, SDValue Val,
- const Value* PtrVal,
- unsigned Alignment) {
- assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
- Opcode == ISD::ATOMIC_LOAD_SUB ||
- Opcode == ISD::ATOMIC_LOAD_AND ||
- Opcode == ISD::ATOMIC_LOAD_OR ||
- Opcode == ISD::ATOMIC_LOAD_XOR ||
- Opcode == ISD::ATOMIC_LOAD_NAND ||
- Opcode == ISD::ATOMIC_LOAD_MIN ||
- Opcode == ISD::ATOMIC_LOAD_MAX ||
- Opcode == ISD::ATOMIC_LOAD_UMIN ||
- Opcode == ISD::ATOMIC_LOAD_UMAX ||
- Opcode == ISD::ATOMIC_SWAP) &&
- "Invalid Atomic Op");
-
- MVT VT = Val.getValueType();
-
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(MemVT);
-
- SDVTList VTs = getVTList(VT, MVT::Other);
- FoldingSetNodeID ID;
- ID.AddInteger(MemVT.getRawBits());
- SDValue Ops[] = {Chain, Ptr, Val};
- AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
- void* IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode* N = NodeAllocator.Allocate<AtomicSDNode>();
- new (N) AtomicSDNode(Opcode, VTs, MemVT,
- Chain, Ptr, Val, PtrVal, Alignment);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
SDValue Chain,
SDValue Ptr, SDValue Val,
@@ -3549,18 +3398,6 @@
/// getMergeValues - Create a MERGE_VALUES node from the given operands.
/// Allowed to return something different (and simpler) if Simplify is true.
-SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps) {
- if (NumOps == 1)
- return Ops[0];
-
- SmallVector<MVT, 4> VTs;
- VTs.reserve(NumOps);
- for (unsigned i = 0; i < NumOps; ++i)
- VTs.push_back(Ops[i].getValueType());
- return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps);
-}
-
-/// DebugLoc-aware version.
SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps,
DebugLoc dl) {
if (NumOps == 1)
@@ -3575,18 +3412,6 @@
}
SDValue
-SelectionDAG::getMemIntrinsicNode(unsigned Opcode,
- const MVT *VTs, unsigned NumVTs,
- const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
- unsigned Align, bool Vol,
- bool ReadMem, bool WriteMem) {
- return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps,
- MemVT, srcValue, SVOff, Align, Vol,
- ReadMem, WriteMem);
-}
-
-SDValue
SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
const MVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps,
@@ -3599,34 +3424,6 @@
}
SDValue
-SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList,
- const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
- unsigned Align, bool Vol,
- bool ReadMem, bool WriteMem) {
- // Memoize the node unless it returns a flag.
- MemIntrinsicSDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
-
- N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
- new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT,
- srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
- CSEMap.InsertNode(N, IP);
- } else {
- N = NodeAllocator.Allocate<MemIntrinsicSDNode>();
- new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT,
- srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
- }
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
-SDValue
SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
const SDValue *Ops, unsigned NumOps,
MVT MemVT, const Value *srcValue, int SVOff,
@@ -3655,31 +3452,6 @@
}
SDValue
-SelectionDAG::getCall(unsigned CallingConv, bool IsVarArgs, bool IsTailCall,
- bool IsInreg, SDVTList VTs,
- const SDValue *Operands, unsigned NumOperands) {
- // Do not include isTailCall in the folding set profile.
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
- ID.AddInteger(CallingConv);
- ID.AddInteger(IsVarArgs);
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
- // Instead of including isTailCall in the folding set, we just
- // set the flag of the existing node.
- if (!IsTailCall)
- cast<CallSDNode>(E)->setNotTailCall();
- return SDValue(E, 0);
- }
- SDNode *N = NodeAllocator.Allocate<CallSDNode>();
- new (N) CallSDNode(CallingConv, IsVarArgs, IsTailCall, IsInreg,
- VTs, Operands, NumOperands);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
-SDValue
SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
bool IsTailCall, bool IsInreg, SDVTList VTs,
const SDValue *Operands, unsigned NumOperands) {
@@ -3705,55 +3477,6 @@
}
SDValue
-SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
- MVT VT, SDValue Chain,
- SDValue Ptr, SDValue Offset,
- const Value *SV, int SVOffset, MVT EVT,
- bool isVolatile, unsigned Alignment) {
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
-
- if (VT == EVT) {
- ExtType = ISD::NON_EXTLOAD;
- } else if (ExtType == ISD::NON_EXTLOAD) {
- assert(VT == EVT && "Non-extending load from different memory type!");
- } else {
- // Extending load.
- if (VT.isVector())
- assert(EVT.getVectorNumElements() == VT.getVectorNumElements() &&
- "Invalid vector extload!");
- else
- assert(EVT.bitsLT(VT) &&
- "Should only be an extending load, not truncating!");
- assert((ExtType == ISD::EXTLOAD || VT.isInteger()) &&
- "Cannot sign/zero extend a FP/Vector load!");
- assert(VT.isInteger() == EVT.isInteger() &&
- "Cannot convert from FP to Int or Int -> FP!");
- }
-
- bool Indexed = AM != ISD::UNINDEXED;
- assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
- "Unindexed load with an offset!");
-
- SDVTList VTs = Indexed ?
- getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
- SDValue Ops[] = { Chain, Ptr, Offset };
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
- ID.AddInteger(EVT.getRawBits());
- ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, isVolatile, Alignment));
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode *N = NodeAllocator.Allocate<LoadSDNode>();
- new (N) LoadSDNode(Ops, VTs, AM, ExtType, EVT, SV, SVOffset,
- Alignment, isVolatile);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
-SDValue
SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
@@ -3802,57 +3525,26 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getLoad(MVT VT,
- SDValue Chain, SDValue Ptr,
- const Value *SV, int SVOffset,
- bool isVolatile, unsigned Alignment) {
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
- SV, SVOffset, VT, isVolatile, Alignment);
-}
-
SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset,
bool isVolatile, unsigned Alignment) {
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Undef = getUNDEF(Ptr.getValueType());
return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
SV, SVOffset, VT, isVolatile, Alignment);
}
-SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
- SDValue Chain, SDValue Ptr,
- const Value *SV,
- int SVOffset, MVT EVT,
- bool isVolatile, unsigned Alignment) {
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef,
- SV, SVOffset, EVT, isVolatile, Alignment);
-}
-
SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
SDValue Chain, SDValue Ptr,
const Value *SV,
int SVOffset, MVT EVT,
bool isVolatile, unsigned Alignment) {
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Undef = getUNDEF(Ptr.getValueType());
return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
SV, SVOffset, EVT, isVolatile, Alignment);
}
SDValue
-SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base,
- SDValue Offset, ISD::MemIndexedMode AM) {
- LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
- assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
- "Load is already a indexed load!");
- return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(),
- LD->getChain(), Base, Offset, LD->getSrcValue(),
- LD->getSrcValueOffset(), LD->getMemoryVT(),
- LD->isVolatile(), LD->getAlignment());
-}
-
-SDValue
SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM) {
LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
@@ -3864,33 +3556,6 @@
LD->isVolatile(), LD->getAlignment());
}
-SDValue SelectionDAG::getStore(SDValue Chain, SDValue Val,
- SDValue Ptr, const Value *SV, int SVOffset,
- bool isVolatile, unsigned Alignment) {
- MVT VT = Val.getValueType();
-
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
-
- SDVTList VTs = getVTList(MVT::Other);
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- SDValue Ops[] = { Chain, Val, Ptr, Undef };
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
- ID.AddInteger(VT.getRawBits());
- ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED,
- isVolatile, Alignment));
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
- new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, false,
- VT, SV, SVOffset, Alignment, isVolatile);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV, int SVOffset,
bool isVolatile, unsigned Alignment) {
@@ -3900,7 +3565,7 @@
Alignment = getMVTAlignment(VT);
SDVTList VTs = getVTList(MVT::Other);
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3918,41 +3583,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val,
- SDValue Ptr, const Value *SV,
- int SVOffset, MVT SVT,
- bool isVolatile, unsigned Alignment) {
- MVT VT = Val.getValueType();
-
- if (VT == SVT)
- return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
-
- assert(VT.bitsGT(SVT) && "Not a truncation?");
- assert(VT.isInteger() == SVT.isInteger() &&
- "Can't do FP-INT conversion!");
-
- if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
-
- SDVTList VTs = getVTList(MVT::Other);
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- SDValue Ops[] = { Chain, Val, Ptr, Undef };
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
- ID.AddInteger(SVT.getRawBits());
- ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED,
- isVolatile, Alignment));
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
- new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true,
- SVT, SV, SVOffset, Alignment, isVolatile);
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV,
int SVOffset, MVT SVT,
@@ -3970,7 +3600,7 @@
Alignment = getMVTAlignment(VT);
SDVTList VTs = getVTList(MVT::Other);
- SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+ SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3989,31 +3619,6 @@
}
SDValue
-SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base,
- SDValue Offset, ISD::MemIndexedMode AM) {
- StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
- assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
- "Store is already a indexed store!");
- SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
- SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
- FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
- ID.AddInteger(ST->getMemoryVT().getRawBits());
- ID.AddInteger(ST->getRawSubclassData());
- void *IP = 0;
- if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
- return SDValue(E, 0);
- SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
- new (N) StoreSDNode(Ops, VTs, AM,
- ST->isTruncatingStore(), ST->getMemoryVT(),
- ST->getSrcValue(), ST->getSrcValueOffset(),
- ST->getAlignment(), ST->isVolatile());
- CSEMap.InsertNode(N, IP);
- AllNodes.push_back(N);
- return SDValue(N, 0);
-}
-
-SDValue
SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM) {
StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
@@ -4038,16 +3643,11 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getVAArg(MVT VT,
+SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
SDValue SV) {
SDValue Ops[] = { Chain, Ptr, SV };
- return getNode(ISD::VAARG, getVTList(VT, MVT::Other), Ops, 3);
-}
-
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- const SDUse *Ops, unsigned NumOps) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps);
+ return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
@@ -4066,11 +3666,6 @@
return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- const SDValue *Ops, unsigned NumOps) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, Ops, NumOps);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
const SDValue *Ops, unsigned NumOps) {
switch (NumOps) {
@@ -4128,12 +3723,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode,
- const std::vector<MVT> &ResultTys,
- const SDValue *Ops, unsigned NumOps) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), ResultTys, Ops, NumOps);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
const std::vector<MVT> &ResultTys,
const SDValue *Ops, unsigned NumOps) {
@@ -4141,12 +3730,6 @@
Ops, NumOps);
}
-SDValue SelectionDAG::getNode(unsigned Opcode,
- const MVT *VTs, unsigned NumVTs,
- const SDValue *Ops, unsigned NumOps) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTs, NumVTs, Ops, NumOps);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
const MVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps) {
@@ -4155,11 +3738,6 @@
return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- const SDValue *Ops, unsigned NumOps) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, Ops, NumOps);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
const SDValue *Ops, unsigned NumOps) {
if (VTList.NumVTs == 1)
@@ -4232,53 +3810,28 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList) {
return getNode(Opcode, DL, VTList, 0, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDValue N1) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
SDValue N1) {
SDValue Ops[] = { N1 };
return getNode(Opcode, DL, VTList, Ops, 1);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDValue N1, SDValue N2) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
SDValue N1, SDValue N2) {
SDValue Ops[] = { N1, N2 };
return getNode(Opcode, DL, VTList, Ops, 2);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDValue N1, SDValue N2, SDValue N3) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
SDValue N1, SDValue N2, SDValue N3) {
SDValue Ops[] = { N1, N2, N3 };
return getNode(Opcode, DL, VTList, Ops, 3);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDValue N1, SDValue N2, SDValue N3,
- SDValue N4) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4) {
@@ -4286,12 +3839,6 @@
return getNode(Opcode, DL, VTList, Ops, 4);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
- SDValue N1, SDValue N2, SDValue N3,
- SDValue N4, SDValue N5) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, N1, N2, N3, N4, N5);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4, SDValue N5) {
@@ -4704,7 +4251,7 @@
///
/// Note that MorphNodeTo returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
-/// the current one.
+/// the current one. Note that the DebugLoc need not be the same.
///
/// Using MorphNodeTo is faster than creating a new node and swapping it in
/// with ReplaceAllUsesWith both because it often avoids allocating a new
@@ -4788,55 +4335,31 @@
/// Note that getTargetNode returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT) {
- return getNode(~Opcode, VT).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
return getNode(~Opcode, dl, VT).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT, SDValue Op1) {
- return getNode(~Opcode, VT, Op1).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
SDValue Op1) {
return getNode(~Opcode, dl, VT, Op1).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
- SDValue Op1, SDValue Op2) {
- return getNode(~Opcode, VT, Op1, Op2).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
SDValue Op1, SDValue Op2) {
return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
- SDValue Op1, SDValue Op2,
- SDValue Op3) {
- return getNode(~Opcode, VT, Op1, Op2, Op3).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
SDValue Op1, SDValue Op2,
SDValue Op3) {
return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT,
- const SDValue *Ops, unsigned NumOps) {
- return getNode(~Opcode, VT, Ops, NumOps).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
const SDValue *Ops, unsigned NumOps) {
return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2);
- SDValue Op;
- return getNode(~Opcode, VTs, 2, &Op, 0).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
MVT VT1, MVT VT2) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
@@ -4844,24 +4367,12 @@
return getNode(~Opcode, dl, VTs, 2, &Op, 0).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDValue Op1) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2);
- return getNode(~Opcode, VTs, 2, &Op1, 1).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, SDValue Op1) {
const MVT *VTs = getNodeValueTypes(VT1, VT2);
return getNode(~Opcode, dl, VTs, 2, &Op1, 1).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDValue Op1,
- SDValue Op2) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2);
- SDValue Ops[] = { Op1, Op2 };
- return getNode(~Opcode, VTs, 2, Ops, 2).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, SDValue Op1,
SDValue Op2) {
@@ -4870,13 +4381,6 @@
return getNode(~Opcode, dl, VTs, 2, Ops, 2).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, SDValue Op1,
- SDValue Op2, SDValue Op3) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2);
- SDValue Ops[] = { Op1, Op2, Op3 };
- return getNode(~Opcode, VTs, 2, Ops, 3).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, SDValue Op1,
SDValue Op2, SDValue Op3) {
@@ -4885,11 +4389,6 @@
return getNode(~Opcode, dl, VTs, 2, Ops, 3).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
- const SDValue *Ops, unsigned NumOps) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2);
- return getNode(~Opcode, VTs, 2, Ops, NumOps).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
MVT VT1, MVT VT2,
const SDValue *Ops, unsigned NumOps) {
@@ -4897,12 +4396,6 @@
return getNode(~Opcode, dl, VTs, 2, Ops, NumOps).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDValue Op1, SDValue Op2) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
- SDValue Ops[] = { Op1, Op2 };
- return getNode(~Opcode, VTs, 3, Ops, 2).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
MVT VT1, MVT VT2, MVT VT3,
SDValue Op1, SDValue Op2) {
@@ -4911,13 +4404,6 @@
return getNode(~Opcode, dl, VTs, 3, Ops, 2).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- SDValue Op1, SDValue Op2,
- SDValue Op3) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
- SDValue Ops[] = { Op1, Op2, Op3 };
- return getNode(~Opcode, VTs, 3, Ops, 3).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
MVT VT1, MVT VT2, MVT VT3,
SDValue Op1, SDValue Op2,
@@ -4927,11 +4413,6 @@
return getNode(~Opcode, dl, VTs, 3, Ops, 3).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
- const SDValue *Ops, unsigned NumOps) {
- const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
- return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
MVT VT1, MVT VT2, MVT VT3,
const SDValue *Ops, unsigned NumOps) {
@@ -4939,17 +4420,6 @@
return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
- MVT VT2, MVT VT3, MVT VT4,
- const SDValue *Ops, unsigned NumOps) {
- std::vector<MVT> VTList;
- VTList.push_back(VT1);
- VTList.push_back(VT2);
- VTList.push_back(VT3);
- VTList.push_back(VT4);
- const MVT *VTs = getNodeValueTypes(VTList);
- return getNode(~Opcode, VTs, 4, Ops, NumOps).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
MVT VT2, MVT VT3, MVT VT4,
const SDValue *Ops, unsigned NumOps) {
@@ -4962,13 +4432,6 @@
return getNode(~Opcode, dl, VTs, 4, Ops, NumOps).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode,
- const std::vector<MVT> &ResultTys,
- const SDValue *Ops, unsigned NumOps) {
- const MVT *VTs = getNodeValueTypes(ResultTys);
- return getNode(~Opcode, VTs, ResultTys.size(),
- Ops, NumOps).getNode();
-}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
const std::vector<MVT> &ResultTys,
const SDValue *Ops, unsigned NumOps) {
@@ -5333,31 +4796,10 @@
(isTarget ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress) :
// Non Thread Local
(isTarget ? ISD::TargetGlobalAddress : ISD::GlobalAddress),
- getSDVTList(VT)), Offset(o) {
+ DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o) {
TheGlobal = const_cast<GlobalValue*>(GA);
}
-MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, MVT memvt,
- const Value *srcValue, int SVO,
- unsigned alignment, bool vol)
- : SDNode(Opc, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
- SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
- assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
- assert(getAlignment() == alignment && "Alignment representation error!");
- assert(isVolatile() == vol && "Volatile representation error!");
-}
-
-MemSDNode::MemSDNode(unsigned Opc, SDVTList VTs, const SDValue *Ops,
- unsigned NumOps, MVT memvt, const Value *srcValue,
- int SVO, unsigned alignment, bool vol)
- : SDNode(Opc, VTs, Ops, NumOps),
- MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
- SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, vol, alignment);
- assert(isPowerOf2_32(alignment) && "Alignment is not a power of 2!");
- assert(getAlignment() == alignment && "Alignment representation error!");
- assert(isVolatile() == vol && "Volatile representation error!");
-}
-
MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt,
const Value *srcValue, int SVO,
unsigned alignment, bool vol)
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Sat Feb 14 07:20:23 2009
@@ -757,6 +757,7 @@
PendingLoads.clear();
PendingExports.clear();
DAG.clear();
+ CurDebugLoc = DebugLoc::getUnknownLoc();
}
/// getRoot - Return the current virtual root of the Selection DAG,
@@ -866,7 +867,7 @@
if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
!V->getType()->isAggregateType())
- return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
+ return N = DAG.getUNDEF(VT);
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
visit(CE->getOpcode(), *CE);
@@ -883,7 +884,8 @@
for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
Constants.push_back(SDValue(Val, i));
}
- return DAG.getMergeValues(&Constants[0], Constants.size());
+ return DAG.getMergeValues(&Constants[0], Constants.size(),
+ getCurDebugLoc());
}
if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
@@ -899,13 +901,13 @@
for (unsigned i = 0; i != NumElts; ++i) {
MVT EltVT = ValueVTs[i];
if (isa<UndefValue>(C))
- Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
+ Constants[i] = DAG.getUNDEF(EltVT);
else if (EltVT.isFloatingPoint())
Constants[i] = DAG.getConstantFP(0, EltVT);
else
Constants[i] = DAG.getConstant(0, EltVT);
}
- return DAG.getMergeValues(&Constants[0], NumElts);
+ return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
}
const VectorType *VecTy = cast<VectorType>(V->getType());
@@ -924,7 +926,7 @@
SDValue Op;
if (isa<UndefValue>(C))
- Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
+ Op = DAG.getUNDEF(EltVT);
else if (EltVT.isFloatingPoint())
Op = DAG.getConstantFP(0, EltVT);
else
@@ -1319,6 +1321,7 @@
void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
SDValue Cond;
SDValue CondLHS = getValue(CB.CmpLHS);
+ DebugLoc dl = getCurDebugLoc();
// Build the setcc now.
if (CB.CmpMHS == NULL) {
@@ -1328,10 +1331,9 @@
Cond = CondLHS;
else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
SDValue True = DAG.getConstant(1, CondLHS.getValueType());
- Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
- CondLHS.getValueType(), CondLHS, True);
+ Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
} else
- Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+ Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
} else {
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
@@ -1342,11 +1344,12 @@
MVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
- Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
+ Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
+ ISD::SETLE);
} else {
- SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(),
+ SDValue SUB = DAG.getNode(ISD::SUB, dl,
VT, CmpOp, DAG.getConstant(Low, VT));
- Cond = DAG.getSetCC(MVT::i1, SUB,
+ Cond = DAG.getSetCC(dl, MVT::i1, SUB,
DAG.getConstant(High-Low, VT), ISD::SETULE);
}
}
@@ -1367,10 +1370,9 @@
if (CB.TrueBB == NextBlock) {
std::swap(CB.TrueBB, CB.FalseBB);
SDValue True = DAG.getConstant(1, Cond.getValueType());
- Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(),
- Cond.getValueType(), Cond, True);
+ Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
}
- SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
+ SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
MVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB));
@@ -1386,7 +1388,7 @@
if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
DAG.getBasicBlock(CB.FalseBB)));
}
}
@@ -1396,7 +1398,8 @@
// Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!");
MVT PTy = TLI.getPointerTy();
- SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy);
+ SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
+ JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
MVT::Other, Index.getValue(1),
@@ -1428,13 +1431,15 @@
TLI.getPointerTy(), SUB);
unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
- SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp);
+ SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
+ JumpTableReg, SwitchOp);
JT.Reg = JumpTableReg;
// Emit the range check for the jump table, and branch to the default block
// for the switch statement if the value being switched on exceeds the largest
// case in the switch.
- SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
+ SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
+ TLI.getSetCCResultType(SUB.getValueType()), SUB,
DAG.getConstant(JTH.Last-JTH.First,VT),
ISD::SETUGT);
@@ -1466,8 +1471,9 @@
DAG.getConstant(B.First, VT));
// Check range
- SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB,
- DAG.getConstant(B.Range, VT),
+ SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
+ TLI.getSetCCResultType(SUB.getValueType()),
+ SUB, DAG.getConstant(B.Range, VT),
ISD::SETUGT);
SDValue ShiftOp;
@@ -1479,7 +1485,8 @@
TLI.getPointerTy(), SUB);
B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
- SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp);
+ SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
+ B.Reg, ShiftOp);
// Set NextBlock to be the MBB immediately after the current one, if any.
// This is used to avoid emitting unnecessary branches to the next block.
@@ -1509,7 +1516,7 @@
unsigned Reg,
BitTestCase &B) {
// Make desired shift
- SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg,
+ SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
TLI.getPointerTy());
SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
TLI.getPointerTy(),
@@ -1520,7 +1527,8 @@
SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
TLI.getPointerTy(), SwitchVal,
DAG.getConstant(B.Mask, TLI.getPointerTy()));
- SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
+ SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
+ TLI.getSetCCResultType(AndOp.getValueType()),
AndOp, DAG.getConstant(0, TLI.getPointerTy()),
ISD::SETNE);
@@ -2189,7 +2197,7 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = getICmpCondCode(predicate);
- setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
+ setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
}
void SelectionDAGLowering::visitFCmp(User &I) {
@@ -2201,7 +2209,7 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Condition = getFCmpCondCode(predicate);
- setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
+ setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
}
void SelectionDAGLowering::visitVICmp(User &I) {
@@ -2213,7 +2221,8 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = getICmpCondCode(predicate);
- setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode));
+ setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
+ Op1, Op2, Opcode));
}
void SelectionDAGLowering::visitVFCmp(User &I) {
@@ -2227,7 +2236,7 @@
ISD::CondCode Condition = getFCmpCondCode(predicate);
MVT DestVT = TLI.getValueType(I.getType());
- setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition));
+ setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
}
void SelectionDAGLowering::visitSelect(User &I) {
@@ -2429,7 +2438,7 @@
// Pad both vectors with undefs to make them the same length as the mask.
unsigned NumConcat = MaskNumElts / SrcNumElts;
- SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
+ SDValue UndefVal = DAG.getUNDEF(SrcVT);
SDValue* MOps1 = new SDValue[NumConcat];
SDValue* MOps2 = new SDValue[NumConcat];
@@ -2531,8 +2540,7 @@
}
if (RangeUse[0] == 0 && RangeUse[0] == 0) {
- setValue(&I, DAG.getNode(ISD::UNDEF,
- getCurDebugLoc(), VT)); // Vectors are not used.
+ setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
return;
}
else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
@@ -2540,7 +2548,7 @@
for (int Input=0; Input < 2; ++Input) {
SDValue& Src = Input == 0 ? Src1 : Src2;
if (RangeUse[Input] == 0) {
- Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
+ Src = DAG.getUNDEF(VT);
} else {
Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
Src, DAG.getIntPtrConstant(StartIdx[Input]));
@@ -2580,7 +2588,7 @@
for (int i = 0; i != MaskNumElts; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
- Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
+ Ops.push_back(DAG.getUNDEF(EltVT));
} else {
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
@@ -2622,18 +2630,15 @@
unsigned i = 0;
// Copy the beginning value(s) from the original aggregate.
for (; i != LinearIndex; ++i)
- Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
- AggValueVTs[i]) :
+ Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
// Copy values from the inserted value(s).
for (; i != LinearIndex + NumValValues; ++i)
- Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
- AggValueVTs[i]) :
+ Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
// Copy remaining value(s) from the original aggregate.
for (; i != NumAggValues; ++i)
- Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
- AggValueVTs[i]) :
+ Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
@@ -2661,8 +2666,7 @@
for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
Values[i - LinearIndex] =
OutOfUndef ?
- DAG.getNode(ISD::UNDEF, getCurDebugLoc(),
- Agg.getNode()->getValueType(Agg.getResNo() + i)) :
+ DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
SDValue(Agg.getNode(), Agg.getResNo() + i);
setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
@@ -3852,7 +3856,7 @@
SDValue Op2 = getValue(I.getOperand(2));
SDValue Op3 = getValue(I.getOperand(3));
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
- DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
+ DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
I.getOperand(1), 0, I.getOperand(2), 0));
return 0;
}
@@ -3861,7 +3865,7 @@
SDValue Op2 = getValue(I.getOperand(2));
SDValue Op3 = getValue(I.getOperand(3));
unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
- DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align,
+ DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
I.getOperand(1), 0));
return 0;
}
@@ -3878,12 +3882,12 @@
Size = C->getZExtValue();
if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
AliasAnalysis::NoAlias) {
- DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false,
+ DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
I.getOperand(1), 0, I.getOperand(2), 0));
return 0;
}
- DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align,
+ DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
I.getOperand(1), 0, I.getOperand(2), 0));
return 0;
}
@@ -3911,7 +3915,8 @@
if (DW && DW->ValidDebugInfo(RSI.getContext())) {
unsigned LabelID =
DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
- DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
+ DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
+ getRoot(), LabelID));
}
return 0;
@@ -3922,7 +3927,8 @@
if (DW && DW->ValidDebugInfo(REI.getContext())) {
unsigned LabelID =
DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
- DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
+ DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
+ getRoot(), LabelID));
}
return 0;
@@ -3947,7 +3953,8 @@
unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
if (DW->getRecordSourceLineCount() != 1)
- DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
+ DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
+ getRoot(), LabelID));
setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction().
getOrCreateDebugLocID(SrcFile, Line, 0)));
@@ -4103,7 +4110,7 @@
}
MVT DestVT = TLI.getValueType(I.getType());
Value* Op1 = I.getOperand(1);
- setValue(&I, DAG.getConvertRndSat(DestVT, getValue(Op1),
+ setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
DAG.getValueType(DestVT),
DAG.getValueType(getValue(Op1).getValueType()),
getValue(I.getOperand(2)),
@@ -4392,7 +4399,8 @@
// Both PendingLoads and PendingExports must be flushed here;
// this call might not return.
(void)getRoot();
- DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
+ DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
+ getControlRoot(), BeginLabel));
}
std::pair<SDValue,SDValue> Result =
@@ -4411,7 +4419,8 @@
// Insert a label at the end of the invoke call to mark the try range. This
// can be used to detect deletion of the invoke via the MachineModuleInfo.
EndLabel = MMI->NextLabelID();
- DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
+ DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
+ getRoot(), EndLabel));
// Inform MachineModuleInfo of range.
MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
@@ -4529,9 +4538,9 @@
for (unsigned i = 0; i != NumRegs; ++i) {
SDValue P;
if (Flag == 0)
- P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
+ P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
else {
- P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag);
+ P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
*Flag = P.getValue(2);
}
Chain = P.getValue(1);
@@ -4616,9 +4625,9 @@
for (unsigned i = 0; i != NumRegs; ++i) {
SDValue Part;
if (Flag == 0)
- Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
+ Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
else {
- Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag);
+ Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
*Flag = Part.getValue(1);
}
Chains[i] = Part.getValue(0);
@@ -5453,9 +5462,9 @@
}
void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
- SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
- getValue(I.getOperand(0)),
- DAG.getSrcValue(I.getOperand(0)));
+ SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
+ getRoot(), getValue(I.getOperand(0)),
+ DAG.getSrcValue(I.getOperand(0)));
setValue(&I, V);
DAG.setRoot(V.getValue(1));
}
@@ -5791,7 +5800,8 @@
ComputeValueVTs(TLI, AI->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (!AI->use_empty()) {
- SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues));
+ SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
+ SDL->getCurDebugLoc()));
// If this argument is live outside of the entry block, insert a copy from
// whereever we got it to the vreg that other BB's will reference it as.
DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo->ValueMap.find(AI);
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Feb 14 07:20:23 2009
@@ -440,9 +440,11 @@
MVT VT = Arg.getValueType();
unsigned VReg = MF.getRegInfo().
createVirtualRegister(TLI.getRegClassFor(VT));
- Chain = DAG.getCopyToReg(Chain, VReg, Arg, InFlag);
+ Chain = DAG.getCopyToReg(Chain, Arg.getDebugLoc(),
+ VReg, Arg, InFlag);
InFlag = Chain.getValue(1);
- Arg = DAG.getCopyFromReg(Chain, VReg, VT, InFlag);
+ Arg = DAG.getCopyFromReg(Chain, Arg.getDebugLoc(),
+ VReg, VT, InFlag);
Chain = Arg.getValue(1);
InFlag = Arg.getValue(2);
}
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Feb 14 07:20:23 2009
@@ -692,7 +692,7 @@
SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const {
if (usesGlobalOffsetTable())
- return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
+ return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
return Table;
}
@@ -723,6 +723,7 @@
/// constant and return true.
bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
const APInt &Demanded) {
+ DebugLoc dl = Op.getDebugLoc();
// FIXME: ISD::SELECT, ISD::SELECT_CC
switch (Op.getOpcode()) {
default: break;
@@ -732,7 +733,7 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (C->getAPIntValue().intersects(~Demanded)) {
MVT VT = Op.getValueType();
- SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
+ SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
DAG.getConstant(Demanded &
C->getAPIntValue(),
VT));
@@ -760,7 +761,7 @@
assert(Op.getValueSizeInBits() == BitWidth &&
"Mask size mismatches value type size!");
APInt NewMask = DemandedMask;
- DebugLoc dl = Op.getNode()->getDebugLoc();
+ DebugLoc dl = Op.getDebugLoc();
// Don't know anything.
KnownZero = KnownOne = APInt(BitWidth, 0);
@@ -779,8 +780,7 @@
} else if (DemandedMask == 0) {
// Not demanding any bits from Op.
if (Op.getOpcode() != ISD::UNDEF)
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, dl,
- Op.getValueType()));
+ return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
return false;
} else if (Depth == 6) { // Limit search depth.
return false;
@@ -890,7 +890,7 @@
// (but not both) turn this into an *inclusive* or.
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
+ return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Op.getOperand(0),
Op.getOperand(1)));
@@ -1704,7 +1704,7 @@
case 1: // Known true.
return DAG.getConstant(1, VT);
case 2: // Undefined.
- return DAG.getNode(ISD::UNDEF, VT);
+ return DAG.getUNDEF(VT);
}
}
@@ -1871,7 +1871,7 @@
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
+ N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMConstantIslandPass.cpp Sat Feb 14 07:20:23 2009
@@ -301,7 +301,7 @@
// aligned.
assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
MachineInstr *CPEMI =
- BuildMI(BB, TII->get(ARM::CONSTPOOL_ENTRY))
+ BuildMI(BB, DebugLoc::getUnknownLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
.addImm(i).addConstantPoolIndex(i).addImm(Size);
CPEMIs.push_back(CPEMI);
@@ -567,7 +567,10 @@
// Add an unconditional branch from OrigBB to NewBB.
// Note the new unconditional branch is not being recorded.
- BuildMI(OrigBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB);
+ // There doesn't seem to be meaningful DebugInfo available; this doesn't
+ // correspond to anything in the source.
+ BuildMI(OrigBB, DebugLoc::getUnknownLoc(),
+ TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB);
NumSplit++;
// Update the CFG. All succs of OrigBB are now succs of NewBB.
@@ -931,7 +934,8 @@
// targets will be exchanged, and the altered branch may be out of
// range, so the machinery has to know about it.
int UncondBr = isThumb ? ARM::tB : ARM::B;
- BuildMI(UserMBB, TII->get(UncondBr)).addMBB(*NewMBB);
+ BuildMI(UserMBB, DebugLoc::getUnknownLoc(),
+ TII->get(UncondBr)).addMBB(*NewMBB);
unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
ImmBranches.push_back(ImmBranch(&UserMBB->back(),
MaxDisp, false, UncondBr));
@@ -1042,7 +1046,8 @@
// Now that we have an island to add the CPE to, clone the original CPE and
// add it to the island.
- U.CPEMI = BuildMI(NewIsland, TII->get(ARM::CONSTPOOL_ENTRY))
+ U.CPEMI = BuildMI(NewIsland, DebugLoc::getUnknownLoc(),
+ TII->get(ARM::CONSTPOOL_ENTRY))
.addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
NumCPEs++;
@@ -1240,11 +1245,12 @@
// Insert a new conditional branch and a new unconditional branch.
// Also update the ImmBranch as well as adding a new entry for the new branch.
- BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB)
- .addImm(CC).addReg(CCReg);
+ BuildMI(MBB, DebugLoc::getUnknownLoc(),
+ TII->get(MI->getOpcode()))
+ .addMBB(NextBB).addImm(CC).addReg(CCReg);
Br.MI = &MBB->back();
BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
- BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB);
+ BuildMI(MBB, DebugLoc::getUnknownLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
@@ -1268,7 +1274,7 @@
if (MI->getOpcode() == ARM::tPOP_RET &&
MI->getOperand(0).getReg() == ARM::PC &&
MI->getNumExplicitOperands() == 1) {
- BuildMI(MI->getParent(), TII->get(ARM::tBX_RET));
+ BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
MI->eraseFromParent();
MadeChange = true;
}
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -379,13 +379,15 @@
bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
SDValue &Base, SDValue &Offset){
+ // FIXME dl should come from the parent load or store, not the address
+ DebugLoc dl = Op.getDebugLoc();
if (N.getOpcode() != ISD::ADD) {
Base = N;
// We must materialize a zero in a reg! Returning a constant here
// wouldn't work without additional code to position the node within
// ISel's topological ordering in a place where ISel will process it
// normally. Instead, just explicitly issue a tMOVri8 node!
- Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
+ Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
return true;
}
@@ -532,6 +534,7 @@
SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
+ DebugLoc dl = N->getDebugLoc();
if (N->isMachineOpcode())
return NULL; // Already selected.
@@ -556,7 +559,7 @@
SDNode *ResNode;
if (Subtarget->isThumb())
- ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
+ ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
CPIdx, CurDAG->getEntryNode());
else {
SDValue Ops[] = {
@@ -567,7 +570,8 @@
CurDAG->getRegister(0, MVT::i32),
CurDAG->getEntryNode()
};
- ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
+ ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
+ Ops, 6);
}
ReplaceUses(Op, SDValue(ResNode, 0));
return NULL;
@@ -632,20 +636,20 @@
}
break;
case ARMISD::FMRRD:
- return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
+ return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
Op.getOperand(0), getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32));
case ISD::UMUL_LOHI: {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
case ISD::SMUL_LOHI: {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
CurDAG->getRegister(0, MVT::i32) };
- return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
}
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Op);
@@ -685,7 +689,7 @@
SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain };
- return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
+ return CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::i32,
MVT::Other, Ops, 6);
}
}
@@ -715,7 +719,8 @@
cast<ConstantSDNode>(N2)->getZExtValue()),
MVT::i32);
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
- SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
+ SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
+ MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
if (Op.getNode()->getNumValues() == 2) {
InFlag = SDValue(ResNode, 1);
@@ -855,7 +860,7 @@
TLI.getPointerTy());
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
- return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
+ return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
MVT::Other, Ops, 3);
}
break;
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -403,7 +403,8 @@
TheCall->getCallingConv() == CallingConv::Fast) &&
"unknown calling convention");
SDValue Callee = TheCall->getCallee();
- unsigned NumOps = TheCall->getNumArgs();
+ unsigned NumOps = TheCall->getNumArgs();
+ DebugLoc dl = TheCall->getDebugLoc();
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
@@ -458,25 +459,25 @@
break;
case MVT::f32:
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
- DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg)));
break;
case MVT::i64: {
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
DAG.getConstant(0, getPointerTy()));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
DAG.getConstant(1, getPointerTy()));
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
if (ObjGPRs == 2)
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
else {
SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, NULL, 0));
}
break;
}
case MVT::f64: {
- SDValue Cvt = DAG.getNode(ARMISD::FMRRD,
+ SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
DAG.getVTList(MVT::i32, MVT::i32),
&Arg, 1);
RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
@@ -485,8 +486,8 @@
Cvt.getValue(1)));
else {
SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Cvt.getValue(1), PtrOff,
NULL, 0));
}
break;
@@ -495,8 +496,8 @@
} else {
assert(ObjSize != 0);
SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
}
NumGPRs += ObjGPRs;
@@ -504,15 +505,15 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
- InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
@@ -537,10 +538,12 @@
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
- CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ Callee = DAG.getLoad(getPointerTy(), dl,
+ DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
- Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
+ Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
+ getPointerTy(), Callee, PICLabel);
} else
Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
@@ -554,10 +557,12 @@
ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
ARMCP::CPStub, 4);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
- CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ Callee = DAG.getLoad(getPointerTy(), dl,
+ DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
- Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
+ Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
+ getPointerTy(), Callee, PICLabel);
} else
Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
}
@@ -576,8 +581,7 @@
}
if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
// implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
- Chain = DAG.getCopyToReg(Chain, ARM::LR,
- DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
InFlag = Chain.getValue(1);
}
@@ -594,7 +598,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
@@ -611,25 +615,27 @@
case MVT::Other:
break;
case MVT::i32:
- Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
+ Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0,
+ MVT::i32, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
if (TheCall->getNumRetVals() > 1 &&
TheCall->getRetValType(1) == MVT::i32) {
// Returns a i64 value.
- Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, ARM::R1, MVT::i32,
Chain.getValue(2)).getValue(1);
ResultVals.push_back(Chain.getValue(0));
}
break;
case MVT::f32:
- Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
- ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
+ Chain = DAG.getCopyFromReg(Chain, dl, ARM::R0,
+ MVT::i32, InFlag).getValue(1);
+ ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32,
Chain.getValue(0)));
break;
case MVT::f64: {
- SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
- SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
- ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
+ SDValue Lo = DAG.getCopyFromReg(Chain, dl, ARM::R0, MVT::i32, InFlag);
+ SDValue Hi = DAG.getCopyFromReg(Lo, dl, ARM::R1, MVT::i32, Lo.getValue(2));
+ ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi));
break;
}
}
@@ -638,40 +644,43 @@
return Chain;
ResultVals.push_back(Chain);
- SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
+ SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
return Res.getValue(Op.getResNo());
}
static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
SDValue Copy;
SDValue Chain = Op.getOperand(0);
+ DebugLoc dl = Op.getDebugLoc();
switch(Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1: {
SDValue LR = DAG.getRegister(ARM::LR, MVT::i32);
- return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
+ return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
}
case 3:
Op = Op.getOperand(1);
if (Op.getValueType() == MVT::f32) {
- Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
} else if (Op.getValueType() == MVT::f64) {
// Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
// available.
- Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
+ Op = DAG.getNode(ARMISD::FMRRD, dl,
+ DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
SDValue Sign = DAG.getConstant(0, MVT::i32);
- return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
+ return DAG.getNode(ISD::RET, dl, MVT::Other, Chain, Op, Sign,
Op.getValue(1), Sign);
}
- Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue());
+ Copy = DAG.getCopyToReg(Chain, dl, ARM::R0, Op, SDValue());
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
break;
case 5:
- Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue());
- Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
+ Copy = DAG.getCopyToReg(Chain, dl, ARM::R1, Op.getOperand(3), SDValue());
+ Copy = DAG.getCopyToReg(Copy, dl, ARM::R0, Op.getOperand(1),
+ Copy.getValue(1));
// If we haven't noted the R0+R1 are live out, do so now.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
@@ -679,10 +688,13 @@
}
break;
case 9: // i128 -> 4 regs
- Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue());
- Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1));
- Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1));
- Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1));
+ Copy = DAG.getCopyToReg(Chain, dl, ARM::R3, Op.getOperand(7), SDValue());
+ Copy = DAG.getCopyToReg(Copy , dl, ARM::R2, Op.getOperand(5),
+ Copy.getValue(1));
+ Copy = DAG.getCopyToReg(Copy , dl, ARM::R1, Op.getOperand(3),
+ Copy.getValue(1));
+ Copy = DAG.getCopyToReg(Copy , dl, ARM::R0, Op.getOperand(1),
+ Copy.getValue(1));
// If we haven't noted the R0+R1 are live out, do so now.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
@@ -695,7 +707,7 @@
}
//We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
- return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
+ return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Copy, Copy.getValue(1));
}
// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
@@ -706,6 +718,8 @@
// into MOVi.
static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
MVT PtrVT = Op.getValueType();
+ // FIXME there is no actual debug info here
+ DebugLoc dl = Op.getDebugLoc();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
SDValue Res;
if (CP->isMachineConstantPoolEntry())
@@ -714,25 +728,26 @@
else
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
- return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
+ return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model
SDValue
ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
+ DebugLoc dl = GA->getDebugLoc();
MVT PtrVT = getPointerTy();
unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "tlsgd", true);
SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
- Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
- Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
+ Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
+ Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
SDValue Chain = Argument.getValue(1);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
- Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
+ Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
// call __tls_get_addr.
ArgListTy Args;
@@ -744,8 +759,7 @@
std::pair<SDValue, SDValue> CallResult =
LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
CallingConv::C, false,
- DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
- DebugLoc::getUnknownLoc());
+ DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
return CallResult.first;
}
@@ -755,11 +769,12 @@
ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG) {
GlobalValue *GV = GA->getGlobal();
+ DebugLoc dl = GA->getDebugLoc();
SDValue Offset;
SDValue Chain = DAG.getEntryNode();
MVT PtrVT = getPointerTy();
// Get the Thread Pointer
- SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
+ SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
if (GV->isDeclaration()){
// initial exec model
@@ -768,26 +783,26 @@
new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
PCAdj, "gottpoff", true);
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
- Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
- Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
+ Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
Chain = Offset.getValue(1);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
- Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
+ Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
- Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
+ Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
} else {
// local exec model
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
- Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
- Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
+ Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
+ Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
}
// The address of the thread local variable is the add of the thread
// pointer with the offset of the variable.
- return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
+ return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
}
SDValue
@@ -807,6 +822,7 @@
SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
+ DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
if (RelocM == Reloc::PIC_) {
@@ -814,18 +830,19 @@
ARMConstantPoolValue *CPV =
new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
- CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
+ CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
- SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
- Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
+ SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
+ Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
if (!UseGOTOFF)
- Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
+ Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
return Result;
} else {
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
- CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
}
}
@@ -843,6 +860,7 @@
SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
SelectionDAG &DAG) {
MVT PtrVT = getPointerTy();
+ DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
@@ -858,17 +876,17 @@
Kind, PCAdj);
CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
}
- CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
- SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue Chain = Result.getValue(1);
if (RelocM == Reloc::PIC_) {
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
- Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
+ Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
if (IsIndirect)
- Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
+ Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
return Result;
}
@@ -878,15 +896,16 @@
assert(Subtarget->isTargetELF() &&
"GLOBAL OFFSET TABLE not implemented for non-ELF targets");
MVT PtrVT = getPointerTy();
+ DebugLoc dl = Op.getDebugLoc();
unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
ARMPCLabelIndex,
ARMCP::CPValue, PCAdj);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
- CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
- SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
+ CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
+ SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
- return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
+ return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}
static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
@@ -895,7 +914,8 @@
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::arm_thread_pointer:
- return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
+ return DAG.getNode(ARMISD::THREAD_POINTER, DebugLoc::getUnknownLoc(),
+ PtrVT);
}
}
@@ -903,15 +923,16 @@
unsigned VarArgsFrameIndex) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
+ DebugLoc dl = Op.getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
+ return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
}
static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG,
unsigned ArgNo, unsigned &NumGPRs,
- unsigned &ArgOffset) {
+ unsigned &ArgOffset, DebugLoc dl) {
MachineFunction &MF = DAG.getMachineFunction();
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
SDValue Root = Op.getOperand(0);
@@ -936,20 +957,20 @@
if (ObjGPRs == 1) {
unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
- ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
if (ObjectVT == MVT::f32)
- ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue);
} else if (ObjGPRs == 2) {
unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
- ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ ArgValue = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
- SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue ArgValue2 = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
- ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
+ ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
}
NumGPRs += ObjGPRs;
@@ -958,11 +979,11 @@
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
if (ObjGPRs == 0)
- ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
+ ArgValue = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
else {
- SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
+ SDValue ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
- ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
+ ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
}
ArgOffset += ObjSize; // Move on to the next argument.
@@ -975,13 +996,14 @@
ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
std::vector<SDValue> ArgValues;
SDValue Root = Op.getOperand(0);
+ DebugLoc dl = Op.getDebugLoc();
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
unsigned NumArgs = Op.getNode()->getNumValues()-1;
for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
- NumGPRs, ArgOffset));
+ NumGPRs, ArgOffset, dl));
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
if (isVarArg) {
@@ -1009,14 +1031,14 @@
for (; NumGPRs < 4; ++NumGPRs) {
unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
- SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
- FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
DAG.getConstant(4, getPointerTy()));
}
if (!MemOps.empty())
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
} else
// This will point to the next argument passed via stack.
@@ -1026,7 +1048,7 @@
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size());
}
@@ -1054,7 +1076,8 @@
/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
/// the given operands.
static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
- SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
+ SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
+ DebugLoc dl) {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
unsigned C = RHSC->getZExtValue();
if (!isLegalCmpImmediate(C, isThumb)) {
@@ -1108,17 +1131,18 @@
break;
}
ARMCC = DAG.getConstant(CondCode, MVT::i32);
- return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
+ return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
}
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
-static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) {
+static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
+ DebugLoc dl) {
SDValue Cmp;
if (!isFloatingPointZero(RHS))
- Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
+ Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
else
- Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
- return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
+ Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
+ return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
}
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
@@ -1129,12 +1153,13 @@
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDValue TrueVal = Op.getOperand(2);
SDValue FalseVal = Op.getOperand(3);
+ DebugLoc dl = Op.getDebugLoc();
if (LHS.getValueType() == MVT::i32) {
SDValue ARMCC;
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
- return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
+ SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
+ return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
}
ARMCC::CondCodes CondCode, CondCode2;
@@ -1143,14 +1168,15 @@
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
- SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
+ SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
+ SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
- SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG);
- Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
+ SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
+ Result = DAG.getNode(ARMISD::CMOV, dl, VT,
+ Result, TrueVal, ARMCC2, CCR, Cmp2);
}
return Result;
}
@@ -1162,12 +1188,14 @@
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue Dest = Op.getOperand(4);
+ DebugLoc dl = Op.getDebugLoc();
if (LHS.getValueType() == MVT::i32) {
SDValue ARMCC;
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
- return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
+ SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
+ return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
+ Chain, Dest, ARMCC, CCR,Cmp);
}
assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
@@ -1176,16 +1204,16 @@
// Swap the LHS/RHS of the comparison if needed.
std::swap(LHS, RHS);
- SDValue Cmp = getVFPCmp(LHS, RHS, DAG);
+ SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
- SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
+ SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
if (CondCode2 != ARMCC::AL) {
ARMCC = DAG.getConstant(CondCode2, MVT::i32);
SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
- Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
+ Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
}
return Res;
}
@@ -1194,55 +1222,59 @@
SDValue Chain = Op.getOperand(0);
SDValue Table = Op.getOperand(1);
SDValue Index = Op.getOperand(2);
+ DebugLoc dl = Op.getDebugLoc();
MVT PTy = getPointerTy();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
- Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
- Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
- SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
+ Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
+ Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
+ SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
- Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
+ Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
Chain, Addr, NULL, 0);
Chain = Addr.getValue(1);
if (isPIC)
- Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
- return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
+ Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
+ return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
}
static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
unsigned Opc =
Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
- Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+ Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
}
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
unsigned Opc =
Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
- Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
- return DAG.getNode(Opc, VT, Op);
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(Opc, dl, VT, Op);
}
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
// Implement fcopysign with a fabs and a conditional fneg.
SDValue Tmp0 = Op.getOperand(0);
SDValue Tmp1 = Op.getOperand(1);
+ DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
MVT SrcVT = Tmp1.getValueType();
- SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
- SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
+ SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
+ SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
+ return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
SDValue
-ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
+ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
@@ -1279,24 +1311,24 @@
while (EmittedNumMemOps < NumMemOps) {
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
- Loads[i] = DAG.getLoad(VT, Chain,
- DAG.getNode(ISD::ADD, MVT::i32, Src,
+ Loads[i] = DAG.getLoad(VT, dl, Chain,
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
DAG.getConstant(SrcOff, MVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
for (i = 0;
i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
- TFOps[i] = DAG.getStore(Chain, Loads[i],
- DAG.getNode(ISD::ADD, MVT::i32, Dst,
+ TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
DAG.getConstant(DstOff, MVT::i32)),
DstSV, DstSVOff + DstOff);
DstOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
EmittedNumMemOps += i;
}
@@ -1316,8 +1348,8 @@
VTSize = 1;
}
- Loads[i] = DAG.getLoad(VT, Chain,
- DAG.getNode(ISD::ADD, MVT::i32, Src,
+ Loads[i] = DAG.getLoad(VT, dl, Chain,
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
DAG.getConstant(SrcOff, MVT::i32)),
SrcSV, SrcSVOff + SrcOff);
TFOps[i] = Loads[i].getValue(1);
@@ -1325,7 +1357,7 @@
SrcOff += VTSize;
BytesLeft -= VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
i = 0;
BytesLeft = BytesLeftSave;
@@ -1338,34 +1370,35 @@
VTSize = 1;
}
- TFOps[i] = DAG.getStore(Chain, Loads[i],
- DAG.getNode(ISD::ADD, MVT::i32, Dst,
+ TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
DAG.getConstant(DstOff, MVT::i32)),
DstSV, DstSVOff + DstOff);
++i;
DstOff += VTSize;
BytesLeft -= VTSize;
}
- return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
}
static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
SDValue Op = N->getOperand(0);
+ DebugLoc dl = N->getDebugLoc();
if (N->getValueType(0) == MVT::f64) {
// Turn i64->f64 into FMDRR.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
DAG.getConstant(0, MVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
DAG.getConstant(1, MVT::i32));
- return DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi);
+ return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
}
// Turn f64->i64 into FMRRD.
- SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
- &Op, 1);
+ SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
+ DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1));
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
}
static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
@@ -1382,21 +1415,22 @@
if (ST->isThumb()) return SDValue();
// Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
+ DebugLoc dl = N->getDebugLoc();
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
DAG.getConstant(0, MVT::i32));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
DAG.getConstant(1, MVT::i32));
// First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
// captures the result into a carry flag.
unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
- Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
+ Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
// The low part is an ARMISD::RRX operand, which shifts the carry in.
- Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
+ Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
}
@@ -1464,6 +1498,7 @@
ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+ DebugLoc dl = MI->getDebugLoc();
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");
case ARM::tMOVCCr: {
@@ -1485,7 +1520,7 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
+ BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
.addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
@@ -1513,7 +1548,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMISelLowering.h Sat Feb 14 07:20:23 2009
@@ -149,7 +149,7 @@
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
- SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
+ SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMInstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -147,10 +147,11 @@
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
+ DebugLoc dl = Orig->getDebugLoc();
if (Orig->getOpcode() == ARM::MOVi2pieces) {
RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
Orig->getOperand(2).getImm(),
- Orig->getOperand(3).getReg(), this, false);
+ Orig->getOperand(3).getReg(), this, false, dl);
return;
}
@@ -243,17 +244,20 @@
// Can't encode it in a so_imm operand. This transformation will
// add more than 1 instruction. Abandon!
return NULL;
- UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
+ UpdateMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
.addReg(BaseReg).addImm(SOImmVal)
.addImm(Pred).addReg(0).addReg(0);
} else if (Amt != 0) {
ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
- UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
+ UpdateMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
.addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
.addImm(Pred).addReg(0).addReg(0);
} else
- UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
+ UpdateMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
.addReg(BaseReg).addReg(OffReg)
.addImm(Pred).addReg(0).addReg(0);
break;
@@ -263,11 +267,13 @@
unsigned Amt = ARM_AM::getAM3Offset(OffImm);
if (OffReg == 0)
// Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
- UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
+ UpdateMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
.addReg(BaseReg).addImm(Amt)
.addImm(Pred).addReg(0).addReg(0);
else
- UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
+ UpdateMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
.addReg(BaseReg).addReg(OffReg)
.addImm(Pred).addReg(0).addReg(0);
break;
@@ -277,19 +283,23 @@
std::vector<MachineInstr*> NewMIs;
if (isPre) {
if (isLoad)
- MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg())
+ MemMI = BuildMI(MF, MI->getDebugLoc(),
+ get(MemOpc), MI->getOperand(0).getReg())
.addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
else
- MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg())
+ MemMI = BuildMI(MF, MI->getDebugLoc(),
+ get(MemOpc)).addReg(MI->getOperand(1).getReg())
.addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
NewMIs.push_back(MemMI);
NewMIs.push_back(UpdateMI);
} else {
if (isLoad)
- MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg())
+ MemMI = BuildMI(MF, MI->getDebugLoc(),
+ get(MemOpc), MI->getOperand(0).getReg())
.addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
else
- MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg())
+ MemMI = BuildMI(MF, MI->getDebugLoc(),
+ get(MemOpc)).addReg(MI->getOperand(1).getReg())
.addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
if (WB.isDead())
UpdateMI->getOperand(0).setIsDead();
@@ -438,6 +448,8 @@
unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
@@ -450,17 +462,17 @@
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch?
- BuildMI(&MBB, get(BOpc)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
else
- BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
+ BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
return 1;
}
// Two-way conditional branch.
- BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
+ BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
- BuildMI(&MBB, get(BOpc)).addMBB(FBB);
+ BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
return 2;
}
@@ -474,19 +486,22 @@
return false;
}
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (DestRC == ARM::GPRRegisterClass) {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction())
- BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
else
- AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg)
+ AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
.addReg(SrcReg)));
} else if (DestRC == ARM::SPRRegisterClass)
- AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg)
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
.addReg(SrcReg));
else if (DestRC == ARM::DPRRegisterClass)
- AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
.addReg(SrcReg));
else
return false;
@@ -512,40 +527,45 @@
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (RC == ARM::GPRRegisterClass) {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction())
- BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
+ BuildMI(MBB, I, DL, get(ARM::tSpill))
+ .addReg(SrcReg, false, false, isKill)
.addFrameIndex(FI).addImm(0);
else
- AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
.addReg(SrcReg, false, false, isKill)
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::DPRRegisterClass) {
- AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
.addReg(SrcReg, false, false, isKill)
.addFrameIndex(FI).addImm(0));
} else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
- AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
.addReg(SrcReg, false, false, isKill)
.addFrameIndex(FI).addImm(0));
}
}
void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const{
+ DebugLoc DL = DebugLoc::getUnknownLoc();
unsigned Opc = 0;
if (RC == ARM::GPRRegisterClass) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction()) {
Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
MachineInstrBuilder MIB =
- BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = ARMInstrAddOperand(MIB, Addr[i]);
NewMIs.push_back(MIB);
@@ -560,7 +580,7 @@
}
MachineInstrBuilder MIB =
- BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = ARMInstrAddOperand(MIB, Addr[i]);
AddDefaultPred(MIB);
@@ -572,35 +592,39 @@
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (RC == ARM::GPRRegisterClass) {
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction())
- BuildMI(MBB, I, get(ARM::tRestore), DestReg)
+ BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
.addFrameIndex(FI).addImm(0);
else
- AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
.addFrameIndex(FI).addReg(0).addImm(0));
} else if (RC == ARM::DPRRegisterClass) {
- AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
.addFrameIndex(FI).addImm(0));
} else {
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
- AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
.addFrameIndex(FI).addImm(0));
}
}
void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
unsigned Opc = 0;
if (RC == ARM::GPRRegisterClass) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->isThumbFunction()) {
Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = ARMInstrAddOperand(MIB, Addr[i]);
NewMIs.push_back(MIB);
@@ -614,7 +638,7 @@
Opc = ARM::FLDS;
}
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = ARMInstrAddOperand(MIB, Addr[i]);
AddDefaultPred(MIB);
@@ -630,7 +654,10 @@
if (!AFI->isThumbFunction() || CSI.empty())
return false;
- MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH));
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
+ MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
for (unsigned i = CSI.size(); i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill.
@@ -686,12 +713,14 @@
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = BuildMI(MF, get(ARM::STR)).addReg(SrcReg, false, false, isKill)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
+ .addReg(SrcReg, false, false, isKill)
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(ARM::LDR)).addReg(DstReg, true, false, false, isDead)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
+ .addReg(DstReg, true, false, false, isDead)
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
}
break;
@@ -703,7 +732,8 @@
if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
// tSpill cannot take a high register operand.
break;
- NewMI = BuildMI(MF, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
+ .addReg(SrcReg, false, false, isKill)
.addFrameIndex(FI).addImm(0);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
@@ -711,7 +741,7 @@
// tRestore cannot target a high register operand.
break;
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(ARM::tRestore))
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
.addReg(DstReg, true, false, false, isDead)
.addFrameIndex(FI).addImm(0);
}
@@ -722,11 +752,13 @@
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
- NewMI = BuildMI(MF, get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
+ .addReg(SrcReg).addFrameIndex(FI)
.addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
- NewMI = BuildMI(MF, get(ARM::FLDS), DstReg).addFrameIndex(FI)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
+ .addFrameIndex(FI)
.addImm(0).addImm(Pred).addReg(PredReg);
}
break;
@@ -737,12 +769,14 @@
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = BuildMI(MF, get(ARM::FSTD)).addReg(SrcReg, false, false, isKill)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
+ .addReg(SrcReg, false, false, isKill)
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
+ .addReg(DstReg, true, false, false, isDead)
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
}
break;
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Sat Feb 14 07:20:23 2009
@@ -116,6 +116,8 @@
ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
SmallVector<std::pair<unsigned, bool>, 8> &Regs,
const TargetInstrInfo *TII) {
+ // FIXME would it be better to take a DL from one of the loads arbitrarily?
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Only a single register to load / store. Don't bother.
unsigned NumRegs = Regs.size();
if (NumRegs <= 1)
@@ -156,7 +158,7 @@
if (ImmedOffset == -1)
return false; // Probably not worth it then.
- BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
+ BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase)
.addReg(Base, false, false, BaseKill).addImm(ImmedOffset)
.addImm(Pred).addReg(PredReg).addReg(0);
Base = NewBase;
@@ -167,9 +169,11 @@
bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
Opcode = getLoadStoreMultipleOpcode(Opcode);
MachineInstrBuilder MIB = (isAM4)
- ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
+ ? BuildMI(MBB, MBBI, dl, TII->get(Opcode))
+ .addReg(Base, false, false, BaseKill)
.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
- : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
+ : BuildMI(MBB, MBBI, dl, TII->get(Opcode))
+ .addReg(Base, false, false, BaseKill)
.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
.addImm(Pred).addReg(PredReg);
for (unsigned i = 0; i != NumRegs; ++i)
@@ -450,6 +454,7 @@
bool BaseKill = MI->getOperand(1).isKill();
unsigned Bytes = getLSMultipleTransferSize(MI);
int Opcode = MI->getOpcode();
+ DebugLoc dl = MI->getDebugLoc();
bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) ||
(!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0))
@@ -510,24 +515,25 @@
if (isLd) {
if (isAM2)
// LDR_PRE, LDR_POST;
- BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
+ BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
.addReg(Base, true)
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
else
// FLDMS, FLDMD
- BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill)
+ BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
+ .addReg(Base, false, false, BaseKill)
.addImm(Offset).addImm(Pred).addReg(PredReg)
.addReg(MI->getOperand(0).getReg(), true);
} else {
MachineOperand &MO = MI->getOperand(0);
if (isAM2)
// STR_PRE, STR_POST;
- BuildMI(MBB, MBBI, TII->get(NewOpc), Base)
+ BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
.addReg(MO.getReg(), false, false, MO.isKill())
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
else
// FSTMS, FSTMD
- BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset)
+ BuildMI(MBB, MBBI, dl, TII->get(NewOpc)).addReg(Base).addImm(Offset)
.addImm(Pred).addReg(PredReg)
.addReg(MO.getReg(), false, false, MO.isKill());
}
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -179,15 +179,18 @@
unsigned DestReg, int Val,
unsigned Pred, unsigned PredReg,
const TargetInstrInfo *TII,
- bool isThumb) const {
+ bool isThumb,
+ DebugLoc dl) const {
MachineFunction &MF = *MBB.getParent();
MachineConstantPool *ConstantPool = MF.getConstantPool();
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
if (isThumb)
- BuildMI(MBB, MBBI, TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
+ BuildMI(MBB, MBBI, dl,
+ TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
else
- BuildMI(MBB, MBBI, TII->get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
+ BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
+ .addConstantPoolIndex(Idx)
.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
}
@@ -321,7 +324,8 @@
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, unsigned BaseReg, int NumBytes,
ARMCC::CondCodes Pred, unsigned PredReg,
- const TargetInstrInfo &TII) {
+ const TargetInstrInfo &TII,
+ DebugLoc dl) {
bool isSub = NumBytes < 0;
if (isSub) NumBytes = -NumBytes;
@@ -338,7 +342,7 @@
assert(SOImmVal != -1 && "Bit extraction didn't work?");
// Build the new ADD / SUB.
- BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
.addReg(BaseReg, false, false, true).addImm(SOImmVal)
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
BaseReg = DestReg;
@@ -379,7 +383,8 @@
unsigned DestReg, unsigned BaseReg,
int NumBytes, bool CanChangeCC,
const TargetInstrInfo &TII,
- const ARMRegisterInfo& MRI) {
+ const ARMRegisterInfo& MRI,
+ DebugLoc dl) {
bool isHigh = !MRI.isLowRegister(DestReg) ||
(BaseReg != 0 && !MRI.isLowRegister(BaseReg));
bool isSub = false;
@@ -395,28 +400,30 @@
if (DestReg == ARM::SP) {
assert(BaseReg == ARM::SP && "Unexpected!");
LdReg = ARM::R3;
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R12)
.addReg(ARM::R3, false, false, true);
}
if (NumBytes <= 255 && NumBytes >= 0)
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
else if (NumBytes < 0 && NumBytes >= -255) {
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
- BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
.addReg(LdReg, false, false, true);
} else
- MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0,&TII,true);
+ MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, &TII,
+ true, dl);
// Emit add / sub.
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
- const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
+ const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl,
+ TII.get(Opc), DestReg);
if (DestReg == ARM::SP || isSub)
MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
else
MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
if (DestReg == ARM::SP)
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R3)
.addReg(ARM::R12, false, false, true);
}
@@ -427,7 +434,8 @@
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, unsigned BaseReg,
int NumBytes, const TargetInstrInfo &TII,
- const ARMRegisterInfo& MRI) {
+ const ARMRegisterInfo& MRI,
+ DebugLoc dl) {
bool isSub = NumBytes < 0;
unsigned Bytes = (unsigned)NumBytes;
if (isSub) Bytes = -NumBytes;
@@ -473,7 +481,8 @@
if (NumMIs > Threshold) {
// This will expand into too many instructions. Load the immediate from a
// constpool entry.
- emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII, MRI);
+ emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
+ MRI, dl);
return;
}
@@ -483,10 +492,10 @@
unsigned Chunk = (1 << 3) - 1;
unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
Bytes -= ThisVal;
- BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
+ BuildMI(MBB, MBBI, dl,TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
.addReg(BaseReg, false, false, true).addImm(ThisVal);
} else {
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
.addReg(BaseReg, false, false, true);
}
BaseReg = DestReg;
@@ -499,10 +508,11 @@
ThisVal /= Scale;
// Build the new tADD / tSUB.
if (isTwoAddr)
- BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
+ BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
+ .addReg(DestReg).addImm(ThisVal);
else {
bool isKill = BaseReg != ARM::SP;
- BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
.addReg(BaseReg, false, false, isKill).addImm(ThisVal);
BaseReg = DestReg;
@@ -520,7 +530,7 @@
}
if (ExtraOpc)
- BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg)
.addReg(DestReg, false, false, true)
.addImm(((unsigned)NumBytes) & 3);
}
@@ -529,12 +539,14 @@
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg,
bool isThumb, const TargetInstrInfo &TII,
- const ARMRegisterInfo& MRI) {
+ const ARMRegisterInfo& MRI,
+ DebugLoc dl) {
if (isThumb)
- emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, MRI);
+ emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
+ MRI, dl);
else
emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
- Pred, PredReg, TII);
+ Pred, PredReg, TII, dl);
}
void ARMRegisterInfo::
@@ -545,6 +557,7 @@
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
// ADJCALLSTACKUP -> add, sp, sp, amount
MachineInstr *Old = I;
+ DebugLoc dl = Old->getDebugLoc();
unsigned Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
@@ -562,12 +575,12 @@
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
- emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this);
+ emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII, *this, dl);
} else {
// Note: PredReg is operand 3 for ADJCALLSTACKUP.
unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
- emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this);
+ emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII, *this, dl);
}
}
}
@@ -580,18 +593,19 @@
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, int Imm,
const TargetInstrInfo &TII,
- const ARMRegisterInfo& MRI) {
+ const ARMRegisterInfo& MRI,
+ DebugLoc dl) {
bool isSub = Imm < 0;
if (isSub) Imm = -Imm;
int Chunk = (1 << 8) - 1;
int ThisVal = (Imm > Chunk) ? Chunk : Imm;
Imm -= ThisVal;
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
if (Imm > 0)
- emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI);
+ emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
if (isSub)
- BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), DestReg)
.addReg(DestReg, false, false, true);
}
@@ -617,6 +631,7 @@
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
bool isThumb = AFI->isThumbFunction();
+ DebugLoc dl = MI.getDebugLoc();
while (!MI.getOperand(i).isFI()) {
++i;
@@ -723,7 +738,8 @@
// MI would expand into a large number of instructions. Don't try to
// simplify the immediate.
if (NumMIs > 2) {
- emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII, *this);
+ emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
+ *this, dl);
MBB.erase(II);
return;
}
@@ -736,12 +752,13 @@
MI.getOperand(i+1).ChangeToImmediate(Mask);
Offset = (Offset - Mask * Scale);
MachineBasicBlock::iterator NII = next(II);
- emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII, *this);
+ emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
+ *this, dl);
} else {
// Translate r0 = add sp, -imm to
// r0 = -imm (this is then translated into a series of instructons)
// r0 = add r0, sp
- emitThumbConstant(MBB, II, DestReg, Offset, TII, *this);
+ emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
MI.setDesc(TII.get(ARM::tADDhirr));
MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
@@ -845,13 +862,15 @@
if (Opcode == ARM::tRestore) {
if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
- Offset, false, TII, *this);
+ Offset, false, TII, *this, dl);
else {
- emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
+ emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
+ true, dl);
UseRR = true;
}
} else
- emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
+ emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
+ *this, dl);
MI.setDesc(TII.get(ARM::tLDR));
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
if (UseRR)
@@ -872,23 +891,25 @@
unsigned TmpReg = ARM::R3;
bool UseRR = false;
if (ValReg == ARM::R3) {
- BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
+ BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12)
.addReg(ARM::R2, false, false, true);
TmpReg = ARM::R2;
}
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
- BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
+ BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), ARM::R12)
.addReg(ARM::R3, false, false, true);
if (Opcode == ARM::tSpill) {
if (FrameReg == ARM::SP)
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
- Offset, false, TII, *this);
+ Offset, false, TII, *this, dl);
else {
- emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
+ emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII,
+ true, dl);
UseRR = true;
}
} else
- emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII, *this);
+ emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
+ *this, dl);
MI.setDesc(TII.get(ARM::tSTR));
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
if (UseRR) // Use [reg, reg] addrmode.
@@ -898,10 +919,10 @@
MachineBasicBlock::iterator NII = next(II);
if (ValReg == ARM::R3)
- BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
+ BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R2)
.addReg(ARM::R12, false, false, true);
if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
- BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
+ BuildMI(MBB, NII, dl, TII.get(ARM::tMOVr), ARM::R3)
.addReg(ARM::R12, false, false, true);
} else
assert(false && "Unexpected opcode!");
@@ -919,7 +940,7 @@
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
- isSub ? -Offset : Offset, Pred, PredReg, TII);
+ isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
}
}
@@ -1201,6 +1222,7 @@
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
unsigned NumBytes = MFI->getStackSize();
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
if (isThumb) {
// Check if R3 is live in. It might have to be used as a scratch register.
@@ -1223,11 +1245,12 @@
int FramePtrSpillFI = 0;
if (VARegSaveSize)
- emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, MBBI, -VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
+ *this, dl);
if (!AFI->hasStackFrame()) {
if (NumBytes != 0)
- emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
return;
}
@@ -1267,7 +1290,7 @@
if (!isThumb) {
// Build the new SUBri to adjust SP for integer callee-save spill area 1.
- emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, MBBI, -GPRCS1Size, ARMCC::AL, 0, isThumb, TII, *this, dl);
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
} else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
++MBBI;
@@ -1276,18 +1299,19 @@
// previous FP.
if (STI.isTargetDarwin() || hasFP(MF)) {
MachineInstrBuilder MIB =
- BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),FramePtr)
+ BuildMI(MBB, MBBI, dl, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri),
+ FramePtr)
.addFrameIndex(FramePtrSpillFI).addImm(0);
if (!isThumb) AddDefaultCC(AddDefaultPred(MIB));
}
if (!isThumb) {
// Build the new SUBri to adjust SP for integer callee-save spill area 2.
- emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this);
+ emitSPUpdate(MBB, MBBI, -GPRCS2Size, ARMCC::AL, 0, false, TII, *this, dl);
// Build the new SUBri to adjust SP for FP callee-save spill area.
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
- emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this);
+ emitSPUpdate(MBB, MBBI, -DPRCSSize, ARMCC::AL, 0, false, TII, *this, dl);
}
// Determine starting offsets of spill areas.
@@ -1304,7 +1328,7 @@
// Insert it after all the callee-save spills.
if (!isThumb)
movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
- emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, MBBI, -NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
}
if(STI.isTargetELF() && hasFP(MF)) {
@@ -1334,6 +1358,7 @@
void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
+ DebugLoc dl = DebugLoc::getUnknownLoc();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert((MBBI->getOpcode() == ARM::BX_RET ||
MBBI->getOpcode() == ARM::tBX_RET ||
@@ -1347,7 +1372,7 @@
int NumBytes = (int)MFI->getStackSize();
if (!AFI->hasStackFrame()) {
if (NumBytes != 0)
- emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this, dl);
} else {
// Unwind MBBI to point to first LDR / FLDD.
const unsigned *CSRegs = getCalleeSavedRegs();
@@ -1370,17 +1395,19 @@
// frame pointer stack slot or target is ELF and the function has FP.
if (NumBytes)
emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
- TII, *this);
+ TII, *this, dl);
else
- BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
} else {
if (MBBI->getOpcode() == ARM::tBX_RET &&
&MBB.front() != MBBI &&
prior(MBBI)->getOpcode() == ARM::tPOP) {
MachineBasicBlock::iterator PMBBI = prior(MBBI);
- emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, PMBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
+ *this, dl);
} else
- emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, isThumb, TII,
+ *this, dl);
}
} else {
// Darwin ABI requires FP to point to the stack slot that contains the
@@ -1394,31 +1421,31 @@
AFI->getDPRCalleeSavedAreaOffset()||
hasFP(MF)) {
if (NumBytes)
- BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
.addImm(NumBytes)
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
else
- BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
}
} else if (NumBytes) {
- emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
+ emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this, dl);
}
// Move SP to start of integer callee save spill area 2.
movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), ARMCC::AL, 0,
- false, TII, *this);
+ false, TII, *this, dl);
// Move SP to start of integer callee save spill area 1.
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), ARMCC::AL, 0,
- false, TII, *this);
+ false, TII, *this, dl);
// Move SP to SP upon entry to the function.
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), ARMCC::AL, 0,
- false, TII, *this);
+ false, TII, *this, dl);
}
}
@@ -1426,12 +1453,13 @@
if (isThumb)
// Epilogue for vararg functions: pop LR to R3 and branch off it.
// FIXME: Verify this is still ok when R3 is no longer being reserved.
- BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)).addReg(ARM::R3);
- emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII, *this);
+ emitSPUpdate(MBB, MBBI, VARegSaveSize, ARMCC::AL, 0, isThumb, TII,
+ *this, dl);
if (isThumb) {
- BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
MBB.erase(MBBI);
}
}
Modified: llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/ARM/ARMRegisterInfo.h Sat Feb 14 07:20:23 2009
@@ -38,7 +38,8 @@
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, int Val,
unsigned Pred, unsigned PredReg,
- const TargetInstrInfo *TII, bool isThumb) const;
+ const TargetInstrInfo *TII, bool isThumb,
+ DebugLoc dl) const;
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// ARM::LR, return the number that it corresponds to (e.g. 14).
Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -204,8 +204,9 @@
break;
}
assert(GP && "GOT PTR not in liveins");
+ // FIXME is there anywhere sensible to get a DebugLoc here?
return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
- GP, MVT::i64);
+ DebugLoc::getUnknownLoc(), GP, MVT::i64);
}
/// getRASaveReg - Grab the return address
@@ -219,8 +220,9 @@
break;
}
assert(RA && "RA PTR not in liveins");
+ // FIXME is there anywhere sensible to get a DebugLoc here?
return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
- RA, MVT::i64);
+ DebugLoc::getUnknownLoc(), RA, MVT::i64);
}
/// InstructionSelect - This callback is invoked by
@@ -240,6 +242,7 @@
if (N->isMachineOpcode()) {
return NULL; // Already selected.
}
+ DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) {
default: break;
@@ -269,23 +272,23 @@
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
+ Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1,
SDValue(0,0));
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
+ Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2,
Chain.getValue(1));
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
+ Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
Chain.getValue(1));
SDNode *CNode =
- CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
+ CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
Chain, Chain.getValue(1));
- Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
+ Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
SDValue(CNode, 1));
return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
}
case ISD::READCYCLECOUNTER: {
SDValue Chain = N->getOperand(0);
- return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
+ return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
Chain);
}
@@ -293,7 +296,7 @@
uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
if (uval == 0) {
- SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
Alpha::R31, MVT::i64);
ReplaceUses(Op, Result);
return NULL;
@@ -311,7 +314,7 @@
//Else use the constant pool
ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
- SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
+ SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI,
getGlobalBaseReg());
return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
@@ -363,25 +366,27 @@
};
SDValue tmp1 = N->getOperand(rev?1:0);
SDValue tmp2 = N->getOperand(rev?0:1);
- SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
+ SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2);
if (inv)
- cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0),
+ cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl,
+ MVT::f64, SDValue(cmp, 0),
CurDAG->getRegister(Alpha::F31, MVT::f64));
switch(CC) {
case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
{
- SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
+ SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64,
tmp1, tmp2);
- cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
+ cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64,
SDValue(cmp2, 0), SDValue(cmp, 0));
break;
}
default: break;
}
- SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0));
- return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
+ SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl,
+ MVT::i64, SDValue(cmp, 0));
+ return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64,
CurDAG->getRegister(Alpha::R31, MVT::i64),
SDValue(LD,0));
}
@@ -400,9 +405,9 @@
SDValue TV = N->getOperand(1);
SDValue FV = N->getOperand(2);
- SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
+ SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, dl, MVT::f64, cond);
return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
- MVT::f64, FV, TV, SDValue(LD,0));
+ dl, MVT::f64, FV, TV, SDValue(LD,0));
}
break;
@@ -427,10 +432,10 @@
if (get_zapImm(mask)) {
SDValue Z =
- SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
+ SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64,
N->getOperand(0).getOperand(0),
getI64Imm(get_zapImm(mask))), 0);
- return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
+ return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z,
getI64Imm(sval));
}
}
@@ -449,6 +454,7 @@
SDValue Chain = N->getOperand(0);
SDValue Addr = N->getOperand(1);
SDValue InFlag(0,0); // Null incoming flag value.
+ DebugLoc dl = N->getDebugLoc();
std::vector<SDValue> CallOperands;
std::vector<MVT> TypeOperands;
@@ -477,16 +483,18 @@
assert(0 && "Unknown operand");
SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
- CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
- Chain };
- Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
+ CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
+ Chain };
+ Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 4), 0);
}
for (int i = 0; i < std::min(6, count); ++i) {
if (TypeOperands[i].isInteger()) {
- Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, args_int[i],
+ CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
- Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, args_float[i],
+ CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else
assert(0 && "Unknown operand");
@@ -496,15 +504,16 @@
// call itself.
if (Addr.getOpcode() == AlphaISD::GPRelLo) {
SDValue GOT = getGlobalBaseReg();
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
- Addr.getOperand(0), Chain, InFlag), 0);
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other,
+ MVT::Flag, Addr.getOperand(0),
+ Chain, InFlag), 0);
} else {
- Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
InFlag = Chain.getValue(1);
- Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
- Chain, InFlag), 0);
+ Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other,
+ MVT::Flag, Chain, InFlag), 0);
}
InFlag = Chain.getValue(1);
@@ -514,15 +523,18 @@
default: assert(0 && "Unexpected ret value!");
case MVT::Other: break;
case MVT::i64:
- Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
+ Chain = CurDAG->getCopyFromReg(Chain, dl,
+ Alpha::R0, MVT::i64, InFlag).getValue(1);
CallResults.push_back(Chain.getValue(0));
break;
case MVT::f32:
- Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
+ Chain = CurDAG->getCopyFromReg(Chain, dl,
+ Alpha::F0, MVT::f32, InFlag).getValue(1);
CallResults.push_back(Chain.getValue(0));
break;
case MVT::f64:
- Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
+ Chain = CurDAG->getCopyFromReg(Chain, dl,
+ Alpha::F0, MVT::f64, InFlag).getValue(1);
CallResults.push_back(Chain.getValue(0));
break;
}
Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -186,10 +186,12 @@
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDValue Zero = DAG.getConstant(0, PtrVT);
+ // FIXME there isn't really any debug info here
+ DebugLoc dl = Op.getDebugLoc();
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
return Lo;
}
@@ -219,6 +221,7 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
std::vector<SDValue> ArgValues;
SDValue Root = Op.getOperand(0);
+ DebugLoc dl = Op.getDebugLoc();
AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
@@ -240,17 +243,17 @@
case MVT::f64:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F8RCRegClass);
- ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
+ ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
break;
case MVT::f32:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F4RCRegClass);
- ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
+ ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
break;
case MVT::i64:
args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
&Alpha::GPRCRegClass);
- ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
+ ArgVal = DAG.getCopyFromReg(Root, dl, args_int[ArgNo], MVT::i64);
break;
}
} else { //more args
@@ -260,7 +263,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
- ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
+ ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
}
@@ -273,34 +276,36 @@
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
- SDValue argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
+ SDValue argt = DAG.getCopyFromReg(Root, dl, args_int[i], MVT::i64);
int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
if (i == 0) VarArgsBase = FI;
SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
- LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
+ LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
- argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
+ argt = DAG.getCopyFromReg(Root, dl, args_float[i], MVT::f64);
FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
SDFI = DAG.getFrameIndex(FI, MVT::i64);
- LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
+ LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
}
//Set up a token factor with all the stack traffic
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
+ Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
}
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size());
}
static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
- SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), dl, Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr,
+ DebugLoc::getUnknownLoc(),
MVT::i64),
SDValue());
switch (Op.getNumOperands()) {
@@ -319,7 +324,8 @@
assert(ArgVT.isFloatingPoint());
ArgReg = Alpha::F0;
}
- Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
+ Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
+ Op.getOperand(1), Copy.getValue(1));
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
break;
@@ -335,12 +341,14 @@
ArgReg1 = Alpha::F0;
ArgReg2 = Alpha::F1;
}
- Copy = DAG.getCopyToReg(Copy, ArgReg1, Op.getOperand(1), Copy.getValue(1));
+ Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
+ Op.getOperand(1), Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
== DAG.getMachineFunction().getRegInfo().liveout_end())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
- Copy = DAG.getCopyToReg(Copy, ArgReg2, Op.getOperand(3), Copy.getValue(1));
+ Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
+ Op.getOperand(3), Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
== DAG.getMachineFunction().getRegInfo().liveout_end())
@@ -348,7 +356,8 @@
break;
}
}
- return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
+ return DAG.getNode(AlphaISD::RET_FLAG, dl,
+ MVT::Other, Copy, Copy.getValue(1));
}
std::pair<SDValue, SDValue>
@@ -434,32 +443,34 @@
Chain = N->getOperand(0);
SDValue VAListP = N->getOperand(1);
const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
+ DebugLoc dl = N->getDebugLoc();
- SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
- SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
+ SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0);
+ SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
- SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
+ SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
Tmp, NULL, 0, MVT::i32);
- DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
+ DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
if (N->getValueType(0).isFloatingPoint())
{
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
- SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
+ SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
DAG.getConstant(8*6, MVT::i64));
- SDValue CC = DAG.getSetCC(MVT::i64, Offset,
+ SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
- DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
+ DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
}
- SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
+ SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
DAG.getConstant(8, MVT::i64));
- Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0,
+ Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0,
MVT::i32);
}
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
@@ -474,7 +485,8 @@
switch (IntNo) {
default: break; // Don't custom lower most intrinsics.
case Intrinsic::alpha_umulh:
- return DAG.getNode(ISD::MULHU, MVT::i64, Op.getOperand(1), Op.getOperand(2));
+ return DAG.getNode(ISD::MULHU, dl, MVT::i64,
+ Op.getOperand(1), Op.getOperand(2));
}
}
@@ -483,8 +495,8 @@
"Unhandled SINT_TO_FP type in custom expander!");
SDValue LD;
bool isDouble = Op.getValueType() == MVT::f64;
- LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
- SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
+ LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0));
+ SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
isDouble?MVT::f64:MVT::f32, LD);
return FP;
}
@@ -493,20 +505,21 @@
SDValue src = Op.getOperand(0);
if (!isDouble) //Promote
- src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
+ src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
- src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
+ src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
- return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
}
case ISD::ConstantPool: {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Constant *C = CP->getConstVal();
SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
+ // FIXME there isn't really any debug info here
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
return Lo;
}
case ISD::GlobalTLSAddress:
@@ -515,22 +528,23 @@
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
+ // FIXME there isn't really any debug info here
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasLocalLinkage()) {
- SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
- SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
+ SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
+ SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
return Lo;
} else
- return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+ return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::ExternalSymbol: {
- return DAG.getNode(AlphaISD::RelLit, MVT::i64,
+ return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
->getSymbol(), MVT::i64),
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+ DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::UREM:
@@ -541,8 +555,8 @@
SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
BuildUDIV(Op.getNode(), DAG, NULL) :
BuildSDIV(Op.getNode(), DAG, NULL);
- Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
- Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
+ Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1));
+ Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
return Tmp1;
}
//fall through
@@ -562,7 +576,7 @@
SDValue Tmp1 = Op.getOperand(0),
Tmp2 = Op.getOperand(1),
Addr = DAG.getExternalSymbol(opstr, MVT::i64);
- return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
+ return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
}
break;
@@ -572,10 +586,10 @@
SDValue Result;
if (Op.getValueType() == MVT::i32)
- Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr,
+ Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
NULL, 0, MVT::i32);
else
- Result = DAG.getLoad(Op.getValueType(), Chain, DataPtr, NULL, 0);
+ Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
return Result;
}
case ISD::VACOPY: {
@@ -585,14 +599,15 @@
const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
- SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
- SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
- SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
+ SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
+ SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
+ SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
- Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
- SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
+ Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
+ NP, NULL,0, MVT::i32);
+ SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
- return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
+ return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
}
case ISD::VASTART: {
SDValue Chain = Op.getOperand(0);
@@ -601,14 +616,15 @@
// vastart stores the address of the VarArgsBase and VarArgsOffset
SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
- SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
- SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
+ SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
+ SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
- return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
+ return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
SA2, NULL, 0, MVT::i32);
}
case ISD::RETURNADDR:
- return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
+ return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
+ MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
}
@@ -619,13 +635,14 @@
void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
+ DebugLoc dl = N->getDebugLoc();
assert(N->getValueType(0) == MVT::i32 &&
N->getOpcode() == ISD::VAARG &&
"Unknown node to custom promote!");
SDValue Chain, DataPtr;
LowerVAARG(N, Chain, DataPtr, DAG);
- SDValue Res = DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0);
+ SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr, NULL, 0);
Results.push_back(Res);
Results.push_back(SDValue(Res.getNode(), 1));
}
@@ -711,6 +728,7 @@
//test sc and maybe branck to start
//exit:
const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ DebugLoc dl = MI->getDebugLoc();
MachineFunction::iterator It = BB;
++It;
@@ -724,46 +742,46 @@
F->insert(It, llscMBB);
F->insert(It, sinkMBB);
- BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
+ BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
unsigned reg_res = MI->getOperand(0).getReg(),
reg_ptr = MI->getOperand(1).getReg(),
reg_v2 = MI->getOperand(2).getReg(),
reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
- BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
+ BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
reg_res).addImm(0).addReg(reg_ptr);
switch (MI->getOpcode()) {
case Alpha::CAS32:
case Alpha::CAS64: {
unsigned reg_cmp
= F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
- BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp)
+ BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
.addReg(reg_v2).addReg(reg_res);
- BuildMI(llscMBB, TII->get(Alpha::BEQ))
+ BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
.addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
- BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
+ BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
.addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
break;
}
case Alpha::LAS32:
case Alpha::LAS64: {
- BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
+ BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
.addReg(reg_res).addReg(reg_v2);
break;
}
case Alpha::SWAP32:
case Alpha::SWAP64: {
- BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
+ BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
.addReg(reg_v2).addReg(reg_v2);
break;
}
}
- BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
+ BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
.addReg(reg_store).addImm(0).addReg(reg_ptr);
- BuildMI(llscMBB, TII->get(Alpha::BEQ))
+ BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
.addImm(0).addReg(reg_store).addMBB(llscMBB);
- BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB);
+ BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB);
thisMBB->addSuccessor(llscMBB);
llscMBB->addSuccessor(llscMBB);
Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaInstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -105,9 +105,11 @@
}
unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
+ MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
"Alpha branch conditions have two components!");
@@ -115,45 +117,54 @@
// One-way branch.
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch
- BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
else // Conditional branch
if (isAlphaIntCondCode(Cond[0].getImm()))
- BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
+ BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
- BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
+ BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return 1;
}
// Two-way Conditional Branch.
if (isAlphaIntCondCode(Cond[0].getImm()))
- BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
+ BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
- BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
+ BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
- BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
+ BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
return 2;
}
bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const {
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const {
//cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
if (DestRC != SrcRC) {
// Not yet supported!
return false;
}
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
if (DestRC == Alpha::GPRCRegisterClass) {
- BuildMI(MBB, MI, get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg);
} else if (DestRC == Alpha::F4RCRegisterClass) {
- BuildMI(MBB, MI, get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg);
} else if (DestRC == Alpha::F8RCRegisterClass) {
- BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
+ .addReg(SrcReg)
+ .addReg(SrcReg);
} else {
// Attempt to copy register that is not GPR or FPR
return false;
@@ -164,22 +175,26 @@
void
AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC) const {
+ MachineBasicBlock::iterator MI,
+ unsigned SrcReg, bool isKill, int FrameIdx,
+ const TargetRegisterClass *RC) const {
//cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
// << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, get(Alpha::STS))
+ BuildMI(MBB, MI, DL, get(Alpha::STS))
.addReg(SrcReg, false, false, isKill)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, get(Alpha::STT))
+ BuildMI(MBB, MI, DL, get(Alpha::STT))
.addReg(SrcReg, false, false, isKill)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, get(Alpha::STQ))
+ BuildMI(MBB, MI, DL, get(Alpha::STQ))
.addReg(SrcReg, false, false, isKill)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
@@ -200,8 +215,9 @@
Opc = Alpha::STQ;
else
abort();
+ DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB =
- BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
+ BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -219,14 +235,17 @@
const TargetRegisterClass *RC) const {
//cerr << "Trying to load " << getPrettyName(DestReg) << " to "
// << FrameIdx << "\n";
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
+ BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
+ BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
+ BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@@ -245,8 +264,9 @@
Opc = Alpha::LDQ;
else
abort();
+ DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB =
- BuildMI(MF, get(Opc), DestReg);
+ BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -279,7 +299,8 @@
bool isKill = MI->getOperand(1).isKill();
Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
- NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
+ .addReg(InReg, false, false, isKill)
.addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
@@ -287,7 +308,8 @@
bool isDead = MI->getOperand(0).isDead();
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
- NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
+ .addReg(OutReg, true, false, false, isDead)
.addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
@@ -410,7 +432,10 @@
void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
- BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31)
.addReg(Alpha::R31);
}
Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaLLRP.cpp Sat Feb 14 07:20:23 2009
@@ -49,6 +49,7 @@
const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
bool Changed = false;
MachineInstr* prev[3] = {0,0,0};
+ DebugLoc dl = DebugLoc::getUnknownLoc();
unsigned count = 0;
for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI) {
@@ -73,7 +74,7 @@
prev[0] = prev[1];
prev[1] = prev[2];
prev[2] = 0;
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+ BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
.addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 1;
@@ -85,10 +86,10 @@
MI->getOperand(1).getImm()) {
prev[0] = prev[2];
prev[1] = prev[2] = 0;
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+ BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
.addReg(Alpha::R31)
.addReg(Alpha::R31);
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+ BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
.addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 2;
@@ -99,12 +100,12 @@
&& prev[2]->getOperand(1).getImm() ==
MI->getOperand(1).getImm()) {
prev[0] = prev[1] = prev[2] = 0;
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
+ BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31).addReg(Alpha::R31);
+ BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31).addReg(Alpha::R31);
+ BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31).addReg(Alpha::R31);
Changed = true; nopintro += 3;
count += 3;
}
@@ -136,7 +137,7 @@
if (ub || AlignAll) {
//we can align stuff for free at this point
while (count % 4) {
- BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
+ BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31)
.addReg(Alpha::R31).addReg(Alpha::R31);
++count;
++nopalign;
Modified: llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Alpha/AlphaRegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -125,11 +125,11 @@
MachineInstr *New;
if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
- New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30)
+ New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
.addImm(-Amount).addReg(Alpha::R30);
} else {
assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
- New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30)
+ New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
.addImm(Amount).addReg(Alpha::R30);
}
@@ -188,7 +188,8 @@
MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
//insert the new
- MachineInstr* nMI=BuildMI(MF, TII.get(Alpha::LDAH), Alpha::R28)
+ MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(),
+ TII.get(Alpha::LDAH), Alpha::R28)
.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
MBB.insert(II, nMI);
} else {
@@ -201,20 +202,21 @@
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
bool FP = hasFP(MF);
static int curgpdist = 0;
//handle GOP offset
- BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
.addGlobalAddress(const_cast<Function*>(MF.getFunction()))
.addReg(Alpha::R27).addImm(++curgpdist);
- BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
.addGlobalAddress(const_cast<Function*>(MF.getFunction()))
.addReg(Alpha::R29).addImm(curgpdist);
//evil const_cast until MO stuff setup to handle const
- BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
.addGlobalAddress(const_cast<Function*>(MF.getFunction()));
// Get the number of bytes to allocate from the FrameInfo
@@ -235,13 +237,13 @@
// adjust stack pointer: r30 -= numbytes
NumBytes = -NumBytes;
if (NumBytes >= IMM_LOW) {
- BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
.addReg(Alpha::R30);
} else if (getUpper16(NumBytes) >= IMM_LOW) {
- BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
- .addReg(Alpha::R30);
- BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
- .addReg(Alpha::R30);
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
+ .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
+ .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
} else {
cerr << "Too big a stack frame at " << NumBytes << "\n";
abort();
@@ -250,10 +252,10 @@
//now if we need to, save the old FP and set the new
if (FP)
{
- BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
.addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
//this must be the last instr in the prolog
- BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
.addReg(Alpha::R30).addReg(Alpha::R30);
}
@@ -266,6 +268,7 @@
assert((MBBI->getOpcode() == Alpha::RETDAG ||
MBBI->getOpcode() == Alpha::RETDAGp)
&& "Can only insert epilog into returning blocks");
+ DebugLoc dl = DebugLoc::getUnknownLoc();
bool FP = hasFP(MF);
@@ -275,20 +278,21 @@
//now if we need to, restore the old FP
if (FP) {
//copy the FP into the SP (discards allocas)
- BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
.addReg(Alpha::R15);
//restore the FP
- BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15)
+ .addImm(0).addReg(Alpha::R15);
}
if (NumBytes != 0) {
if (NumBytes <= IMM_HIGH) {
- BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
.addReg(Alpha::R30);
} else if (getUpper16(NumBytes) <= IMM_HIGH) {
- BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
.addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
- BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
+ BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
.addImm(getLower16(NumBytes)).addReg(Alpha::R30);
} else {
cerr << "Too big a stack frame at " << NumBytes << "\n";
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -249,6 +249,7 @@
SDNode *emitBuildVector(SDValue build_vec) {
MVT vecVT = build_vec.getValueType();
SDNode *bvNode = build_vec.getNode();
+ DebugLoc dl = bvNode->getDebugLoc();
// Check to see if this vector can be represented as a CellSPU immediate
// constant by invoking all of the instruction selection predicates:
@@ -279,7 +280,7 @@
SDValue CGPoolOffset =
SPU::LowerConstantPool(CPIdx, *CurDAG,
SPUtli.getSPUTargetMachine());
- return SelectCode(CurDAG->getLoad(build_vec.getValueType(),
+ return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl,
CurDAG->getEntryNode(), CGPoolOffset,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment));
@@ -661,6 +662,7 @@
unsigned NewOpc;
MVT OpVT = Op.getValueType();
SDValue Ops[8];
+ DebugLoc dl = N->getDebugLoc();
if (N->isMachineOpcode()) {
return NULL; // Already selected.
@@ -679,7 +681,7 @@
} else {
NewOpc = SPU::Ar32;
Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
- Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, Op.getValueType(),
+ Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, dl, Op.getValueType(),
TFI, Imm0), 0);
n_ops = 2;
}
@@ -703,7 +705,7 @@
/*NOTREACHED*/
break;
case MVT::i32:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
CurDAG->getConstant(0x80808080, MVT::i32),
CurDAG->getConstant(0x00010203, MVT::i32),
CurDAG->getConstant(0x80808080, MVT::i32),
@@ -711,7 +713,7 @@
break;
case MVT::i16:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
CurDAG->getConstant(0x80808080, MVT::i32),
CurDAG->getConstant(0x80800203, MVT::i32),
CurDAG->getConstant(0x80808080, MVT::i32),
@@ -719,7 +721,7 @@
break;
case MVT::i8:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
CurDAG->getConstant(0x80808080, MVT::i32),
CurDAG->getConstant(0x80808003, MVT::i32),
CurDAG->getConstant(0x80808080, MVT::i32),
@@ -729,10 +731,10 @@
SDNode *shufMaskLoad = emitBuildVector(shufMask);
SDNode *PromoteScalar =
- SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0));
+ SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl, Op0VecVT, Op0));
SDValue zextShuffle =
- CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
+ CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
SDValue(PromoteScalar, 0),
SDValue(PromoteScalar, 0),
SDValue(shufMaskLoad, 0));
@@ -740,28 +742,28 @@
// N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
// re-use it in the VEC2PREFSLOT selection without needing to explicitly
// call SelectCode (it's already done for us.)
- SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, OpVecVT, zextShuffle));
- return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, OpVT,
+ SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
+ return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
zextShuffle));
} else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
- emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
+ emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl));
- return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT,
+ return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
} else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
- emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG));
+ emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG, dl));
- return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT,
+ return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
} else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
SDNode *CGLoad =
- emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
+ emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl));
- return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT,
+ return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
} else if (Opc == ISD::TRUNCATE) {
@@ -779,7 +781,8 @@
if (shift_amt >= 32) {
SDNode *hi32 =
- CurDAG->getTargetNode(SPU::ORr32_r64, OpVT, Op0.getOperand(0));
+ CurDAG->getTargetNode(SPU::ORr32_r64, dl, OpVT,
+ Op0.getOperand(0));
shift_amt -= 32;
if (shift_amt > 0) {
@@ -790,7 +793,8 @@
if (Op0.getOpcode() == ISD::SRL)
Opc = SPU::ROTMr32;
- hi32 = CurDAG->getTargetNode(Opc, OpVT, SDValue(hi32, 0), shift);
+ hi32 = CurDAG->getTargetNode(Opc, dl, OpVT, SDValue(hi32, 0),
+ shift);
}
return hi32;
@@ -828,9 +832,9 @@
if (vtm->ldresult_imm) {
SDValue Zero = CurDAG->getTargetConstant(0, VT);
- Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
} else {
- Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
}
return Result;
@@ -866,7 +870,7 @@
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
else
- return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
+ return CurDAG->getTargetNode(NewOpc, dl, OpVT, Ops, n_ops);
} else
return SelectCode(Op);
}
@@ -891,13 +895,14 @@
MVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
SDValue SelMaskVal;
+ DebugLoc dl = Op.getDebugLoc();
- VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
+ VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
- SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, SelMaskVal);
- ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, VecVT,
+ SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
+ ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
CurDAG->getTargetConstant(0, OpVT));
- VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
+ VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
SDValue(ZeroFill, 0),
SDValue(VecOp0, 0),
SDValue(SelMask, 0));
@@ -908,35 +913,35 @@
if (bytes > 0) {
Shift =
- CurDAG->getTargetNode(SPU::SHLQBYIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::SHLQBYIv2i64, dl, VecVT,
SDValue(VecOp0, 0),
CurDAG->getTargetConstant(bytes, ShiftAmtVT));
}
if (bits > 0) {
Shift =
- CurDAG->getTargetNode(SPU::SHLQBIIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::SHLQBIIv2i64, dl, VecVT,
SDValue((Shift != 0 ? Shift : VecOp0), 0),
CurDAG->getTargetConstant(bits, ShiftAmtVT));
}
} else {
SDNode *Bytes =
- CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
+ CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
ShiftAmt,
CurDAG->getTargetConstant(3, ShiftAmtVT));
SDNode *Bits =
- CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
+ CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
ShiftAmt,
CurDAG->getTargetConstant(7, ShiftAmtVT));
Shift =
- CurDAG->getTargetNode(SPU::SHLQBYv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::SHLQBYv2i64, dl, VecVT,
SDValue(VecOp0, 0), SDValue(Bytes, 0));
Shift =
- CurDAG->getTargetNode(SPU::SHLQBIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::SHLQBIv2i64, dl, VecVT,
SDValue(Shift, 0), SDValue(Bits, 0));
}
- return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
}
/*!
@@ -954,8 +959,9 @@
SDValue ShiftAmt = Op.getOperand(1);
MVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *Shift = 0;
+ DebugLoc dl = Op.getDebugLoc();
- VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
+ VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
@@ -963,45 +969,45 @@
if (bytes > 0) {
Shift =
- CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, dl, VecVT,
SDValue(VecOp0, 0),
CurDAG->getTargetConstant(bytes, ShiftAmtVT));
}
if (bits > 0) {
Shift =
- CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, dl, VecVT,
SDValue((Shift != 0 ? Shift : VecOp0), 0),
CurDAG->getTargetConstant(bits, ShiftAmtVT));
}
} else {
SDNode *Bytes =
- CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
+ CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
ShiftAmt,
CurDAG->getTargetConstant(3, ShiftAmtVT));
SDNode *Bits =
- CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
+ CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
ShiftAmt,
CurDAG->getTargetConstant(7, ShiftAmtVT));
// Ensure that the shift amounts are negated!
- Bytes = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
+ Bytes = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
SDValue(Bytes, 0),
CurDAG->getTargetConstant(0, ShiftAmtVT));
- Bits = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
+ Bits = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
SDValue(Bits, 0),
CurDAG->getTargetConstant(0, ShiftAmtVT));
Shift =
- CurDAG->getTargetNode(SPU::ROTQMBYv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQMBYv2i64, dl, VecVT,
SDValue(VecOp0, 0), SDValue(Bytes, 0));
Shift =
- CurDAG->getTargetNode(SPU::ROTQMBIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQMBIv2i64, dl, VecVT,
SDValue(Shift, 0), SDValue(Bits, 0));
}
- return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
}
/*!
@@ -1018,24 +1024,25 @@
MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
MVT ShiftAmtVT = ShiftAmt.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
SDNode *VecOp0 =
- CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op.getOperand(0));
+ CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0));
SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
SDNode *SignRot =
- CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, MVT::v2i64,
+ CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
SDValue(VecOp0, 0), SignRotAmt);
SDNode *UpperHalfSign =
- CurDAG->getTargetNode(SPU::ORi32_v4i32, MVT::i32, SDValue(SignRot, 0));
+ CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
SDNode *UpperHalfSignMask =
- CurDAG->getTargetNode(SPU::FSM64r32, VecVT, SDValue(UpperHalfSign, 0));
+ CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
SDNode *UpperLowerMask =
- CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
SDNode *UpperLowerSelect =
- CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
SDValue(UpperHalfSignMask, 0),
SDValue(VecOp0, 0),
SDValue(UpperLowerMask, 0));
@@ -1049,7 +1056,7 @@
if (bytes > 0) {
bytes = 31 - bytes;
Shift =
- CurDAG->getTargetNode(SPU::ROTQBYIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQBYIv2i64, dl, VecVT,
SDValue(UpperLowerSelect, 0),
CurDAG->getTargetConstant(bytes, ShiftAmtVT));
}
@@ -1057,24 +1064,24 @@
if (bits > 0) {
bits = 8 - bits;
Shift =
- CurDAG->getTargetNode(SPU::ROTQBIIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQBIIv2i64, dl, VecVT,
SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
CurDAG->getTargetConstant(bits, ShiftAmtVT));
}
} else {
SDNode *NegShift =
- CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
+ CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
Shift =
- CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
Shift =
- CurDAG->getTargetNode(SPU::ROTQBIv2i64, VecVT,
+ CurDAG->getTargetNode(SPU::ROTQBIv2i64, dl, VecVT,
SDValue(Shift, 0), SDValue(NegShift, 0));
}
- return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
}
/*!
@@ -1082,9 +1089,11 @@
*/
SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
+ // Currently there's no DL on the input, but won't hurt to pretend.
+ DebugLoc dl = Op.getDebugLoc();
MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
SDValue i64vec =
- SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue());
+ SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue(), dl);
// Here's where it gets interesting, because we have to parse out the
// subtree handed back in i64vec:
@@ -1095,7 +1104,7 @@
SDValue Op0 = i64vec.getOperand(0);
ReplaceUses(i64vec, Op0);
- return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT,
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
SDValue(emitBuildVector(Op0), 0));
} else if (i64vec.getOpcode() == SPUISD::SHUFB) {
SDValue lhs = i64vec.getOperand(0);
@@ -1130,11 +1139,12 @@
: emitBuildVector(shufmask));
SDNode *shufNode =
- Select(CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
+ Select(CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
SDValue(lhsNode, 0), SDValue(rhsNode, 0),
SDValue(shufMaskNode, 0)));
- return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(shufNode, 0));
+ return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
+ SDValue(shufNode, 0));
} else {
cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n";
abort();
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -114,7 +114,7 @@
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
CallingConv::C, false, Callee, Args, DAG,
- Op.getNode()->getDebugLoc());
+ Op.getDebugLoc());
return CallInfo.first;
}
@@ -507,6 +507,7 @@
ISD::LoadExtType ExtType = LN->getExtensionType();
unsigned alignment = LN->getAlignment();
const valtype_map_s *vtm = getValueTypeMapEntry(InVT);
+ DebugLoc dl = Op.getDebugLoc();
switch (LN->getAddressingMode()) {
case ISD::UNINDEXED: {
@@ -533,7 +534,7 @@
// Simplify the base pointer for this case:
basePtr = basePtr.getOperand(0);
if ((offset & ~0xf) > 0) {
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
basePtr,
DAG.getConstant((offset & ~0xf), PtrVT));
}
@@ -553,7 +554,7 @@
int64_t rotamt = -vtm->prefslot_byte;
if (rotamt < 0)
rotamt += 16;
- rotate = DAG.getNode(ISD::ADD, PtrVT,
+ rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
basePtr,
DAG.getConstant(rotamt, PtrVT));
}
@@ -572,29 +573,29 @@
// Convert the (add <ptr>, <const>) to an indirect address contained
// in a register. Note that this is done because we need to avoid
// creating a 0(reg) d-form address due to the SPU's block loads.
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1);
- the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag);
- basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT);
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
+ the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
+ basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
} else {
// Convert the (add <arg1>, <arg2>) to an indirect address, which
// will likely be lowered as a reg(reg) x-form address.
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1);
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
}
} else {
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
basePtr,
DAG.getConstant(0, PtrVT));
}
// Offset the rotate amount by the basePtr and the preferred slot
// byte offset
- rotate = DAG.getNode(ISD::ADD, PtrVT,
+ rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
basePtr,
DAG.getConstant(-vtm->prefslot_byte, PtrVT));
}
// Re-emit as a v16i8 vector load
- result = DAG.getLoad(MVT::v16i8, the_chain, basePtr,
+ result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
LN->isVolatile(), 16);
@@ -602,27 +603,27 @@
the_chain = result.getValue(1);
// Rotate into the preferred slot:
- result = DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v16i8,
+ result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8,
result.getValue(0), rotate);
// Convert the loaded v16i8 vector to the appropriate vector type
// specified by the operand:
MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
- result = DAG.getNode(SPUISD::VEC2PREFSLOT, InVT,
- DAG.getNode(ISD::BIT_CONVERT, vecVT, result));
+ result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
+ DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result));
// Handle extending loads by extending the scalar result:
if (ExtType == ISD::SEXTLOAD) {
- result = DAG.getNode(ISD::SIGN_EXTEND, OutVT, result);
+ result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result);
} else if (ExtType == ISD::ZEXTLOAD) {
- result = DAG.getNode(ISD::ZERO_EXTEND, OutVT, result);
+ result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result);
} else if (ExtType == ISD::EXTLOAD) {
unsigned NewOpc = ISD::ANY_EXTEND;
if (OutVT.isFloatingPoint())
NewOpc = ISD::FP_EXTEND;
- result = DAG.getNode(NewOpc, OutVT, result);
+ result = DAG.getNode(NewOpc, dl, OutVT, result);
}
SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
@@ -631,7 +632,7 @@
the_chain
};
- result = DAG.getNode(SPUISD::LDRESULT, retvts,
+ result = DAG.getNode(SPUISD::LDRESULT, dl, retvts,
retops, sizeof(retops) / sizeof(retops[0]));
return result;
}
@@ -663,6 +664,7 @@
MVT VT = Value.getValueType();
MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ DebugLoc dl = Op.getDebugLoc();
unsigned alignment = SN->getAlignment();
switch (SN->getAddressingMode()) {
@@ -688,18 +690,18 @@
// Simplify the base pointer for this case:
basePtr = basePtr.getOperand(0);
- insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
+ insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
basePtr,
DAG.getConstant((offset & 0xf), PtrVT));
if ((offset & ~0xf) > 0) {
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
basePtr,
DAG.getConstant((offset & ~0xf), PtrVT));
}
} else {
// Otherwise, assume it's at byte 0 of basePtr
- insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
+ insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
basePtr,
DAG.getConstant(0, PtrVT));
}
@@ -718,28 +720,28 @@
// Convert the (add <ptr>, <const>) to an indirect address contained
// in a register. Note that this is done because we need to avoid
// creating a 0(reg) d-form address due to the SPU's block loads.
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1);
- the_chain = DAG.getCopyToReg(the_chain, VReg, basePtr, Flag);
- basePtr = DAG.getCopyFromReg(the_chain, VReg, PtrVT);
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
+ the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
+ basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
} else {
// Convert the (add <arg1>, <arg2>) to an indirect address, which
// will likely be lowered as a reg(reg) x-form address.
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, Op0, Op1);
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
}
} else {
- basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
basePtr,
DAG.getConstant(0, PtrVT));
}
// Insertion point is solely determined by basePtr's contents
- insertEltOffs = DAG.getNode(ISD::ADD, PtrVT,
+ insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT,
basePtr,
DAG.getConstant(0, PtrVT));
}
// Re-emit as a v16i8 vector load
- alignLoadVec = DAG.getLoad(MVT::v16i8, the_chain, basePtr,
+ alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
SN->getSrcValue(), SN->getSrcValueOffset(),
SN->isVolatile(), 16);
@@ -771,15 +773,16 @@
#endif
SDValue insertEltOp =
- DAG.getNode(SPUISD::SHUFFLE_MASK, vecVT, insertEltOffs);
+ DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
SDValue vectorizeOp =
- DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue);
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
- result = DAG.getNode(SPUISD::SHUFB, vecVT,
+ result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
vectorizeOp, alignLoadVec,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp));
+ DAG.getNode(ISD::BIT_CONVERT, dl,
+ MVT::v4i32, insertEltOp));
- result = DAG.getStore(the_chain, result, basePtr,
+ result = DAG.getStore(the_chain, dl, result, basePtr,
LN->getSrcValue(), LN->getSrcValueOffset(),
LN->isVolatile(), LN->getAlignment());
@@ -822,15 +825,17 @@
SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
+ // FIXME there is no actual debug info here
+ DebugLoc dl = Op.getDebugLoc();
if (TM.getRelocationModel() == Reloc::Static) {
if (!ST->usingLargeMem()) {
// Just return the SDValue with the constant pool address in it.
- return DAG.getNode(SPUISD::AFormAddr, PtrVT, CPI, Zero);
+ return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, CPI, Zero);
} else {
- SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero);
- SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero);
- return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
+ SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, CPI, Zero);
+ SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, CPI, Zero);
+ return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
}
}
@@ -853,14 +858,16 @@
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
+ // FIXME there is no actual debug info here
+ DebugLoc dl = Op.getDebugLoc();
if (TM.getRelocationModel() == Reloc::Static) {
if (!ST->usingLargeMem()) {
- return DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero);
+ return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, JTI, Zero);
} else {
- SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero);
- SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero);
- return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
+ SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, JTI, Zero);
+ SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, JTI, Zero);
+ return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
}
}
@@ -877,14 +884,16 @@
SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
const TargetMachine &TM = DAG.getTarget();
SDValue Zero = DAG.getConstant(0, PtrVT);
+ // FIXME there is no actual debug info here
+ DebugLoc dl = Op.getDebugLoc();
if (TM.getRelocationModel() == Reloc::Static) {
if (!ST->usingLargeMem()) {
- return DAG.getNode(SPUISD::AFormAddr, PtrVT, GA, Zero);
+ return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, GA, Zero);
} else {
- SDValue Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero);
- SDValue Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero);
- return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
+ SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, GA, Zero);
+ SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, GA, Zero);
+ return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
}
} else {
cerr << "LowerGlobalAddress: Relocation model other than static not "
@@ -900,6 +909,8 @@
static SDValue
LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
+ // FIXME there is no actual debug info here
+ DebugLoc dl = Op.getDebugLoc();
if (VT == MVT::f64) {
ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
@@ -909,9 +920,9 @@
uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
SDValue T = DAG.getConstant(dbits, MVT::i64);
- SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T);
- return DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Tvec));
+ SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
+ return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
}
return SDValue();
@@ -926,6 +937,7 @@
SmallVector<SDValue, 48> ArgValues;
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
+ DebugLoc dl = Op.getDebugLoc();
const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
@@ -986,7 +998,7 @@
unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
- ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
+ ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
++ArgRegIdx;
} else {
// We need to load the argument to a virtual register if we determined
@@ -994,7 +1006,7 @@
// or we're forced to do vararg
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
- ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
+ ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
ArgOffset += StackSlotSize;
}
@@ -1015,7 +1027,7 @@
VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8);
- SDValue Store = DAG.getStore(Root, ArgVal, FIN, NULL, 0);
+ SDValue Store = DAG.getStore(Root, dl, ArgVal, FIN, NULL, 0);
Root = Store.getOperand(0);
MemOps.push_back(Store);
@@ -1023,13 +1035,14 @@
ArgOffset += StackSlotSize;
}
if (!MemOps.empty())
- Root = DAG.getNode(ISD::TokenFactor,MVT::Other,&MemOps[0],MemOps.size());
+ Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &MemOps[0], MemOps.size());
}
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size());
}
@@ -1056,6 +1069,7 @@
unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
+ DebugLoc dl = TheCall->getDebugLoc();
// Handy pointer type
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -1086,7 +1100,7 @@
// PtrOff will be used to store the current argument to the stack if a
// register cannot be found for it.
SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
+ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
switch (Arg.getValueType().getSimpleVT()) {
default: assert(0 && "Unexpected ValueType for argument!");
@@ -1098,7 +1112,7 @@
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
ArgOffset += StackSlotSize;
}
break;
@@ -1107,7 +1121,7 @@
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
ArgOffset += StackSlotSize;
}
break;
@@ -1120,7 +1134,7 @@
if (ArgRegIdx != NumArgRegs) {
RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
} else {
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
ArgOffset += StackSlotSize;
}
break;
@@ -1134,7 +1148,7 @@
if (!MemOpChains.empty()) {
// Adjust the stack pointer for the stack arguments.
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
}
@@ -1142,8 +1156,8 @@
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
- InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
@@ -1169,14 +1183,14 @@
// This may be an unsafe assumption for JIT and really large compilation
// units.
if (GV->isDeclaration()) {
- Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, GA, Zero);
+ Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, GA, Zero);
} else {
- Callee = DAG.getNode(SPUISD::PCRelAddr, CalleeVT, GA, Zero);
+ Callee = DAG.getNode(SPUISD::PCRelAddr, dl, CalleeVT, GA, Zero);
}
} else {
// "Large memory" mode: Turn all calls into indirect calls with a X-form
// address pairs:
- Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, GA, Zero);
+ Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero);
}
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
MVT CalleeVT = Callee.getValueType();
@@ -1185,9 +1199,9 @@
Callee.getValueType());
if (!ST->usingLargeMem()) {
- Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, ExtSym, Zero);
+ Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, ExtSym, Zero);
} else {
- Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, ExtSym, Zero);
+ Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, ExtSym, Zero);
}
} else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
// If this is an absolute destination address that appears to be a legal
@@ -1207,7 +1221,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
- Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
+ Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
&Ops[0], Ops.size());
InFlag = Chain.getValue(1);
@@ -1225,31 +1239,35 @@
case MVT::Other: break;
case MVT::i32:
if (TheCall->getValueType(1) == MVT::i32) {
- Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32, InFlag).getValue(1);
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
+ MVT::i32, InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32,
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
Chain.getValue(2)).getValue(1);
ResultVals[1] = Chain.getValue(0);
NumResults = 2;
} else {
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, InFlag).getValue(1);
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
+ InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
NumResults = 1;
}
break;
case MVT::i64:
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i64, InFlag).getValue(1);
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64,
+ InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
NumResults = 1;
break;
case MVT::i128:
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i128, InFlag).getValue(1);
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128,
+ InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
NumResults = 1;
break;
case MVT::f32:
case MVT::f64:
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0),
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0),
InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
NumResults = 1;
@@ -1260,7 +1278,7 @@
case MVT::v4i32:
case MVT::v8i16:
case MVT::v16i8:
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, TheCall->getValueType(0),
+ Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0),
InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
NumResults = 1;
@@ -1273,7 +1291,7 @@
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals[NumResults++] = Chain;
- SDValue Res = DAG.getMergeValues(ResultVals, NumResults);
+ SDValue Res = DAG.getMergeValues(ResultVals, NumResults, dl);
return Res.getValue(Op.getResNo());
}
@@ -1282,6 +1300,7 @@
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
+ DebugLoc dl = Op.getDebugLoc();
CCState CCInfo(CC, isVarArg, TM, RVLocs);
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
@@ -1299,14 +1318,15 @@
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ Op.getOperand(i*2+1), Flag);
Flag = Chain.getValue(1);
}
if (Flag.getNode())
- return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else
- return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain);
+ return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
}
@@ -1571,6 +1591,7 @@
SDValue
LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
// If this is a vector of constants or undefs, get the bits. A bit in
// UndefBits is set if the corresponding element of the vector is an
// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
@@ -1598,8 +1619,9 @@
&& "LowerBUILD_VECTOR: Unexpected floating point vector element.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
SDValue T = DAG.getConstant(Value32, MVT::i32);
- return DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, T, T, T, T));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MVT::v4i32, T, T, T, T));
break;
}
case MVT::v2f64: {
@@ -1608,8 +1630,8 @@
&& "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
// NOTE: pretend the constant is an integer. LLVM won't load FP constants
SDValue T = DAG.getConstant(f64val, MVT::i64);
- return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
break;
}
case MVT::v16i8: {
@@ -1618,8 +1640,8 @@
SDValue Ops[8];
for (int i = 0; i < 8; ++i)
Ops[i] = DAG.getConstant(Value16, MVT::i16);
- return DAG.getNode(ISD::BIT_CONVERT, VT,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v8i16, Ops, 8));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, Ops, 8));
}
case MVT::v8i16: {
unsigned short Value16;
@@ -1630,20 +1652,20 @@
SDValue T = DAG.getConstant(Value16, VT.getVectorElementType());
SDValue Ops[8];
for (int i = 0; i < 8; ++i) Ops[i] = T;
- return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops, 8);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops, 8);
}
case MVT::v4i32: {
unsigned int Value = SplatBits;
SDValue T = DAG.getConstant(Value, VT.getVectorElementType());
- return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T, T, T);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
}
case MVT::v2i32: {
unsigned int Value = SplatBits;
SDValue T = DAG.getConstant(Value, VT.getVectorElementType());
- return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T);
}
case MVT::v2i64: {
- return SPU::LowerSplat_v2i64(VT, DAG, SplatBits);
+ return SPU::LowerSplat_v2i64(VT, DAG, SplatBits, dl);
}
}
@@ -1651,15 +1673,16 @@
}
SDValue
-SPU::LowerSplat_v2i64(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal) {
+SPU::LowerSplat_v2i64(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
+ DebugLoc dl) {
uint32_t upper = uint32_t(SplatVal >> 32);
uint32_t lower = uint32_t(SplatVal);
if (upper == lower) {
// Magic constant that can be matched by IL, ILA, et. al.
SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
- return DAG.getNode(ISD::BIT_CONVERT, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
Val, Val, Val, Val));
} else {
SDValue LO32;
@@ -1679,16 +1702,16 @@
// Create lower vector if not a special pattern
if (!lower_special) {
SDValue LO32C = DAG.getConstant(lower, MVT::i32);
- LO32 = DAG.getNode(ISD::BIT_CONVERT, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
LO32C, LO32C, LO32C, LO32C));
}
// Create upper vector if not a special pattern
if (!upper_special) {
SDValue HI32C = DAG.getConstant(upper, MVT::i32);
- HI32 = DAG.getNode(ISD::BIT_CONVERT, OpVT,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
HI32C, HI32C, HI32C, HI32C));
}
@@ -1702,7 +1725,7 @@
// Unhappy situation... both upper and lower are special, so punt with
// a target constant:
SDValue Zero = DAG.getConstant(0, MVT::i32);
- HI32 = LO32 = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Zero, Zero,
+ HI32 = LO32 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Zero, Zero,
Zero, Zero);
}
@@ -1732,8 +1755,8 @@
ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
}
- return DAG.getNode(SPUISD::SHUFB, OpVT, HI32, LO32,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size()));
}
}
@@ -1755,6 +1778,7 @@
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
SDValue PermMask = Op.getOperand(2);
+ DebugLoc dl = Op.getDebugLoc();
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
@@ -1829,18 +1853,19 @@
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Initialize temporary register to 0
SDValue InitTempReg =
- DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT));
+ DAG.getCopyToReg(DAG.getEntryNode(), dl, VReg, DAG.getConstant(0, PtrVT));
// Copy register's contents as index in SHUFFLE_MASK:
SDValue ShufMaskOp =
- DAG.getNode(SPUISD::SHUFFLE_MASK, MVT::v4i32,
+ DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v4i32,
DAG.getTargetConstant(V2Elt, MVT::i32),
- DAG.getCopyFromReg(InitTempReg, VReg, PtrVT));
+ DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT));
// Use shuffle mask in SHUFB synthetic instruction:
- return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp);
+ return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
+ ShufMaskOp);
} else if (rotate) {
int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
- return DAG.getNode(SPUISD::ROTBYTES_LEFT, V1.getValueType(),
+ return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
V1, DAG.getConstant(rotamt, MVT::i16));
} else {
// Convert the SHUFFLE_VECTOR mask's input element units to the
@@ -1861,14 +1886,15 @@
}
}
- SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
&ResultMask[0], ResultMask.size());
- return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask);
+ return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask);
}
}
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
SDValue Op0 = Op.getOperand(0); // Op0 = the scalar
+ DebugLoc dl = Op.getDebugLoc();
if (Op0.getNode()->getOpcode() == ISD::Constant) {
// For a constant, build the appropriate constant vector, which will
@@ -1895,7 +1921,7 @@
for (size_t j = 0; j < n_copies; ++j)
ConstVecValues.push_back(CValue);
- return DAG.getNode(ISD::BUILD_VECTOR, Op.getValueType(),
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, Op.getValueType(),
&ConstVecValues[0], ConstVecValues.size());
} else {
// Otherwise, copy the value from one register to another:
@@ -1907,7 +1933,7 @@
case MVT::i64:
case MVT::f32:
case MVT::f64:
- return DAG.getNode(SPUISD::PREFSLOT2VEC, Op.getValueType(), Op0, Op0);
+ return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
}
}
@@ -1918,6 +1944,7 @@
MVT VT = Op.getValueType();
SDValue N = Op.getOperand(0);
SDValue Elt = Op.getOperand(1);
+ DebugLoc dl = Op.getDebugLoc();
SDValue retval;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
@@ -1936,7 +1963,7 @@
if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
// i32 and i64: Element 0 is the preferred slot
- return DAG.getNode(SPUISD::VEC2PREFSLOT, VT, N);
+ return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
}
// Need to generate shuffle mask and extract:
@@ -1995,12 +2022,12 @@
ShufMask[i] = DAG.getConstant(bits, MVT::i32);
}
- SDValue ShufMaskVec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ SDValue ShufMaskVec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufMask[0],
sizeof(ShufMask) / sizeof(ShufMask[0]));
- retval = DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
- DAG.getNode(SPUISD::SHUFB, N.getValueType(),
+ retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
+ DAG.getNode(SPUISD::SHUFB, dl, N.getValueType(),
N, N, ShufMaskVec));
} else {
// Variable index: Rotate the requested element into slot 0, then replicate
@@ -2013,7 +2040,7 @@
// Make life easier by making sure the index is zero-extended to i32
if (Elt.getValueType() != MVT::i32)
- Elt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Elt);
+ Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
// Scale the index to a bit/byte shift quantity
APInt scaleFactor =
@@ -2023,11 +2050,11 @@
if (scaleShift > 0) {
// Scale the shift factor:
- Elt = DAG.getNode(ISD::SHL, MVT::i32, Elt,
+ Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
DAG.getConstant(scaleShift, MVT::i32));
}
- vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, VecVT, N, Elt);
+ vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt);
// Replicate the bytes starting at byte 0 across the entire vector (for
// consistency with the notion of a unified register set)
@@ -2040,20 +2067,20 @@
/*NOTREACHED*/
case MVT::i8: {
SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, factor, factor,
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, factor, factor,
factor, factor);
break;
}
case MVT::i16: {
SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, factor, factor,
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, factor, factor,
factor, factor);
break;
}
case MVT::i32:
case MVT::f32: {
SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, factor, factor,
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, factor, factor,
factor, factor);
break;
}
@@ -2061,14 +2088,14 @@
case MVT::f64: {
SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
- replicate = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, loFactor, hiFactor,
- loFactor, hiFactor);
+ replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ loFactor, hiFactor, loFactor, hiFactor);
break;
}
}
- retval = DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
- DAG.getNode(SPUISD::SHUFB, VecVT,
+ retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
+ DAG.getNode(SPUISD::SHUFB, dl, VecVT,
vecShift, vecShift, replicate));
}
@@ -2079,6 +2106,7 @@
SDValue VecOp = Op.getOperand(0);
SDValue ValOp = Op.getOperand(1);
SDValue IdxOp = Op.getOperand(2);
+ DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
@@ -2086,16 +2114,16 @@
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $sp ($1) because it's always 16-byte aligned and it's available:
- SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, PtrVT,
+ SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
DAG.getConstant(CN->getSExtValue(), PtrVT));
- SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, VT, Pointer);
+ SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
SDValue result =
- DAG.getNode(SPUISD::SHUFB, VT,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp),
+ DAG.getNode(SPUISD::SHUFB, dl, VT,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
VecOp,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask));
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask));
return result;
}
@@ -2104,6 +2132,7 @@
const TargetLowering &TLI)
{
SDValue N0 = Op.getOperand(0); // Everything has at least one operand
+ DebugLoc dl = Op.getDebugLoc();
MVT ShiftVT = TLI.getShiftAmountTy();
assert(Op.getValueType() == MVT::i8);
@@ -2116,10 +2145,10 @@
// 8-bit addition: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, MVT::i8,
- DAG.getNode(Opc, MVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
@@ -2127,81 +2156,81 @@
// 8-bit subtraction: Promote the arguments up to 16-bits and truncate
// the result:
SDValue N1 = Op.getOperand(1);
- N0 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0);
- N1 = DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N1);
- return DAG.getNode(ISD::TRUNCATE, MVT::i8,
- DAG.getNode(Opc, MVT::i16, N0, N1));
+ N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
+ N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::ROTR:
case ISD::ROTL: {
SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
- ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
+ ? DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
N1Opc = N1.getValueType().bitsLT(ShiftVT)
? ISD::ZERO_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
- ? DAG.getNode(N1Opc, ShiftVT, N1)
+ ? DAG.getNode(N1Opc, dl, ShiftVT, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
TLI.getShiftAmountTy()));
SDValue ExpandArg =
- DAG.getNode(ISD::OR, MVT::i16, N0,
- DAG.getNode(ISD::SHL, MVT::i16,
+ DAG.getNode(ISD::OR, dl, MVT::i16, N0,
+ DAG.getNode(ISD::SHL, dl, MVT::i16,
N0, DAG.getConstant(8, MVT::i32)));
- return DAG.getNode(ISD::TRUNCATE, MVT::i8,
- DAG.getNode(Opc, MVT::i16, ExpandArg, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
}
case ISD::SRL:
case ISD::SHL: {
SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
- ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
+ ? DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i32));
N1Opc = N1.getValueType().bitsLT(ShiftVT)
? ISD::ZERO_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
- ? DAG.getNode(N1Opc, ShiftVT, N1)
+ ? DAG.getNode(N1Opc, dl, ShiftVT, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(), ShiftVT));
- return DAG.getNode(ISD::TRUNCATE, MVT::i8,
- DAG.getNode(Opc, MVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::SRA: {
SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
- ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
+ ? DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getSExtValue(),
MVT::i16));
N1Opc = N1.getValueType().bitsLT(ShiftVT)
? ISD::SIGN_EXTEND
: ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
- ? DAG.getNode(N1Opc, ShiftVT, N1)
+ ? DAG.getNode(N1Opc, dl, ShiftVT, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
ShiftVT));
- return DAG.getNode(ISD::TRUNCATE, MVT::i8,
- DAG.getNode(Opc, MVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
}
case ISD::MUL: {
SDValue N1 = Op.getOperand(1);
unsigned N1Opc;
N0 = (N0.getOpcode() != ISD::Constant
- ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
+ ? DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0)
: DAG.getConstant(cast<ConstantSDNode>(N0)->getZExtValue(),
MVT::i16));
N1Opc = N1.getValueType().bitsLT(MVT::i16) ? ISD::SIGN_EXTEND : ISD::TRUNCATE;
N1 = (N1.getOpcode() != ISD::Constant
- ? DAG.getNode(N1Opc, MVT::i16, N1)
+ ? DAG.getNode(N1Opc, dl, MVT::i16, N1)
: DAG.getConstant(cast<ConstantSDNode>(N1)->getSExtValue(),
MVT::i16));
- return DAG.getNode(ISD::TRUNCATE, MVT::i8,
- DAG.getNode(Opc, MVT::i16, N0, N1));
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+ DAG.getNode(Opc, dl, MVT::i16, N0, N1));
break;
}
}
@@ -2210,7 +2239,7 @@
}
//! Generate the carry-generate shuffle mask.
-SDValue SPU::getCarryGenerateShufMask(SelectionDAG &DAG) {
+SDValue SPU::getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
SmallVector<SDValue, 16 > ShufBytes;
// Create the shuffle mask for "rotating" the borrow up one register slot
@@ -2220,12 +2249,12 @@
ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
//! Generate the borrow-generate shuffle mask
-SDValue SPU::getBorrowGenerateShufMask(SelectionDAG &DAG) {
+SDValue SPU::getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
SmallVector<SDValue, 16 > ShufBytes;
// Create the shuffle mask for "rotating" the borrow up one register slot
@@ -2235,7 +2264,7 @@
ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
@@ -2245,6 +2274,7 @@
SDValue ConstVec;
SDValue Arg;
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
ConstVec = Op.getOperand(0);
Arg = Op.getOperand(1);
@@ -2278,8 +2308,9 @@
for (size_t i = 0; i < tcVecSize; ++i)
tcVec[i] = tc;
- return DAG.getNode(Op.getNode()->getOpcode(), VT, Arg,
- DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec, tcVecSize));
+ return DAG.getNode(Op.getNode()->getOpcode(), dl, VT, Arg,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
+ tcVec, tcVecSize));
}
}
@@ -2297,6 +2328,7 @@
static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
+ DebugLoc dl = Op.getDebugLoc();
switch (VT.getSimpleVT()) {
default:
@@ -2305,10 +2337,10 @@
SDValue N = Op.getOperand(0);
SDValue Elt0 = DAG.getConstant(0, MVT::i32);
- SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N);
- SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
+ SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
+ SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i8, CNTB, Elt0);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
}
case MVT::i16: {
@@ -2322,22 +2354,22 @@
SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
SDValue Shift1 = DAG.getConstant(8, MVT::i32);
- SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N);
- SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
+ SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
+ SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
SDValue CNTB_rescopy =
- DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
+ DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
- SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16);
+ SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
- return DAG.getNode(ISD::AND, MVT::i16,
- DAG.getNode(ISD::ADD, MVT::i16,
- DAG.getNode(ISD::SRL, MVT::i16,
+ return DAG.getNode(ISD::AND, dl, MVT::i16,
+ DAG.getNode(ISD::ADD, dl, MVT::i16,
+ DAG.getNode(ISD::SRL, dl, MVT::i16,
Tmp1, Shift1),
Tmp1),
Mask0);
@@ -2356,37 +2388,38 @@
SDValue Shift1 = DAG.getConstant(16, MVT::i32);
SDValue Shift2 = DAG.getConstant(8, MVT::i32);
- SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, vecVT, N, N);
- SDValue CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
+ SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
+ SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
// CNTB_result becomes the chain to which all of the virtual registers
// CNTB_reg, SUM1_reg become associated:
SDValue CNTB_result =
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, CNTB, Elt0);
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
SDValue CNTB_rescopy =
- DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
+ DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
SDValue Comp1 =
- DAG.getNode(ISD::SRL, MVT::i32,
- DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32), Shift1);
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
+ Shift1);
SDValue Sum1 =
- DAG.getNode(ISD::ADD, MVT::i32,
- Comp1, DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32));
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
+ DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
SDValue Sum1_rescopy =
- DAG.getCopyToReg(CNTB_result, SUM1_reg, Sum1);
+ DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1);
SDValue Comp2 =
- DAG.getNode(ISD::SRL, MVT::i32,
- DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32),
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
Shift2);
SDValue Sum2 =
- DAG.getNode(ISD::ADD, MVT::i32, Comp2,
- DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32));
+ DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
+ DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
- return DAG.getNode(ISD::AND, MVT::i32, Sum2, Mask0);
+ return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
}
case MVT::i64:
@@ -2455,6 +2488,7 @@
static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
const TargetLowering &TLI) {
CondCodeSDNode *CC = dyn_cast<CondCodeSDNode>(Op.getOperand(2));
+ DebugLoc dl = Op.getDebugLoc();
assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n");
SDValue lhs = Op.getOperand(0);
@@ -2468,62 +2502,62 @@
// Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
// selected to a NOP:
- SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, lhs);
+ SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs);
SDValue lhsHi32 =
- DAG.getNode(ISD::TRUNCATE, MVT::i32,
- DAG.getNode(ISD::SRL, IntVT,
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
+ DAG.getNode(ISD::SRL, dl, IntVT,
i64lhs, DAG.getConstant(32, MVT::i32)));
SDValue lhsHi32abs =
- DAG.getNode(ISD::AND, MVT::i32,
+ DAG.getNode(ISD::AND, dl, MVT::i32,
lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
SDValue lhsLo32 =
- DAG.getNode(ISD::TRUNCATE, MVT::i32, i64lhs);
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
// SETO and SETUO only use the lhs operand:
if (CC->get() == ISD::SETO) {
// Evaluates to true if Op0 is not [SQ]NaN - lowers to the inverse of
// SETUO
APInt ccResultAllOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
- return DAG.getNode(ISD::XOR, ccResultVT,
- DAG.getSetCC(ccResultVT,
+ return DAG.getNode(ISD::XOR, dl, ccResultVT,
+ DAG.getSetCC(dl, ccResultVT,
lhs, DAG.getConstantFP(0.0, lhsVT),
ISD::SETUO),
DAG.getConstant(ccResultAllOnes, ccResultVT));
} else if (CC->get() == ISD::SETUO) {
// Evaluates to true if Op0 is [SQ]NaN
- return DAG.getNode(ISD::AND, ccResultVT,
- DAG.getSetCC(ccResultVT,
+ return DAG.getNode(ISD::AND, dl, ccResultVT,
+ DAG.getSetCC(dl, ccResultVT,
lhsHi32abs,
DAG.getConstant(0x7ff00000, MVT::i32),
ISD::SETGE),
- DAG.getSetCC(ccResultVT,
+ DAG.getSetCC(dl, ccResultVT,
lhsLo32,
DAG.getConstant(0, MVT::i32),
ISD::SETGT));
}
- SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, rhs);
+ SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
SDValue rhsHi32 =
- DAG.getNode(ISD::TRUNCATE, MVT::i32,
- DAG.getNode(ISD::SRL, IntVT,
+ DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
+ DAG.getNode(ISD::SRL, dl, IntVT,
i64rhs, DAG.getConstant(32, MVT::i32)));
// If a value is negative, subtract from the sign magnitude constant:
SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT);
// Convert the sign-magnitude representation into 2's complement:
- SDValue lhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT,
+ SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
lhsHi32, DAG.getConstant(31, MVT::i32));
- SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64lhs);
+ SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs);
SDValue lhsSelect =
- DAG.getNode(ISD::SELECT, IntVT,
+ DAG.getNode(ISD::SELECT, dl, IntVT,
lhsSelectMask, lhsSignMag2TC, i64lhs);
- SDValue rhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT,
+ SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
rhsHi32, DAG.getConstant(31, MVT::i32));
- SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64rhs);
+ SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs);
SDValue rhsSelect =
- DAG.getNode(ISD::SELECT, IntVT,
+ DAG.getNode(ISD::SELECT, dl, IntVT,
rhsSelectMask, rhsSignMag2TC, i64rhs);
unsigned compareOp;
@@ -2554,19 +2588,20 @@
}
SDValue result =
- DAG.getSetCC(ccResultVT, lhsSelect, rhsSelect, (ISD::CondCode) compareOp);
+ DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect,
+ (ISD::CondCode) compareOp);
if ((CC->get() & 0x8) == 0) {
// Ordered comparison:
- SDValue lhsNaN = DAG.getSetCC(ccResultVT,
+ SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT,
lhs, DAG.getConstantFP(0.0, MVT::f64),
ISD::SETO);
- SDValue rhsNaN = DAG.getSetCC(ccResultVT,
+ SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT,
rhs, DAG.getConstantFP(0.0, MVT::f64),
ISD::SETO);
- SDValue ordered = DAG.getNode(ISD::AND, ccResultVT, lhsNaN, rhsNaN);
+ SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN);
- result = DAG.getNode(ISD::AND, ccResultVT, ordered, result);
+ result = DAG.getNode(ISD::AND, dl, ccResultVT, ordered, result);
}
return result;
@@ -2592,6 +2627,7 @@
SDValue trueval = Op.getOperand(2);
SDValue falseval = Op.getOperand(3);
SDValue condition = Op.getOperand(4);
+ DebugLoc dl = Op.getDebugLoc();
// NOTE: SELB's arguments: $rA, $rB, $mask
//
@@ -2604,10 +2640,10 @@
// legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up
// with another "cannot select select_cc" assert:
- SDValue compare = DAG.getNode(ISD::SETCC,
+ SDValue compare = DAG.getNode(ISD::SETCC, dl,
TLI.getSetCCResultType(Op.getValueType()),
lhs, rhs, condition);
- return DAG.getNode(SPUISD::SELB, VT, falseval, trueval, compare);
+ return DAG.getNode(SPUISD::SELB, dl, VT, falseval, trueval, compare);
}
//! Custom lower ISD::TRUNCATE
@@ -2616,6 +2652,7 @@
MVT VT = Op.getValueType();
MVT::SimpleValueType simpleVT = VT.getSimpleVT();
MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
+ DebugLoc dl = Op.getDebugLoc();
SDValue Op0 = Op.getOperand(0);
MVT Op0VT = Op0.getValueType();
@@ -2626,20 +2663,21 @@
unsigned maskHigh = 0x08090a0b;
unsigned maskLow = 0x0c0d0e0f;
// Use a shuffle to perform the truncation
- SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
+ SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
DAG.getConstant(maskHigh, MVT::i32),
DAG.getConstant(maskLow, MVT::i32),
DAG.getConstant(maskHigh, MVT::i32),
DAG.getConstant(maskLow, MVT::i32));
- SDValue PromoteScalar = DAG.getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0);
+ SDValue PromoteScalar = DAG.getNode(SPUISD::PREFSLOT2VEC, dl,
+ Op0VecVT, Op0);
- SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, Op0VecVT,
+ SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, Op0VecVT,
PromoteScalar, PromoteScalar, shufMask);
- return DAG.getNode(SPUISD::VEC2PREFSLOT, VT,
- DAG.getNode(ISD::BIT_CONVERT, VecVT, truncShuffle));
+ return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
+ DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, truncShuffle));
}
return SDValue(); // Leave the truncate unmolested
@@ -2785,6 +2823,7 @@
MVT NodeVT = N->getValueType(0); // The node's value type
MVT Op0VT = Op0.getValueType(); // The first operand's result
SDValue Result; // Initially, empty result
+ DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) {
default: break;
@@ -2835,7 +2874,7 @@
}
#endif
- return DAG.getNode(SPUISD::IndirectAddr, Op0VT,
+ return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
IndirectArg, combinedValue);
}
}
@@ -2893,7 +2932,7 @@
}
#endif
- return DAG.getNode(SPUISD::IndirectAddr, Op0VT,
+ return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
Op0.getOperand(0), Op0.getOperand(1));
}
}
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUISelLowering.h Sat Feb 14 07:20:23 2009
@@ -78,10 +78,11 @@
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
const SPUTargetMachine &TM);
- SDValue LowerSplat_v2i64(MVT OpVT, SelectionDAG &DAG, uint64_t splat);
+ SDValue LowerSplat_v2i64(MVT OpVT, SelectionDAG &DAG, uint64_t splat,
+ DebugLoc dl);
- SDValue getBorrowGenerateShufMask(SelectionDAG &DAG);
- SDValue getCarryGenerateShufMask(SelectionDAG &DAG);
+ SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl);
+ SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl);
}
class SPUTargetMachine; // forward dec'l.
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPUInstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -259,22 +259,25 @@
// we instruction select bitconvert i64 -> f64 as a noop for example, so our
// types have no specific meaning.
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
if (DestRC == SPU::R8CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R16CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R32CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R32FPRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R64CRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R64FPRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::GPRCRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::VECREGRegisterClass) {
- BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
} else {
// Attempt to copy unknown/unsupported register class!
return false;
@@ -312,15 +315,17 @@
abort();
}
- addFrameReference(BuildMI(MBB, MI, get(opc))
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ addFrameReference(BuildMI(MBB, MI, DL, get(opc))
.addReg(SrcReg, false, false, isKill), FrameIdx);
}
void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
cerr << "storeRegToAddr() invoked!\n";
abort();
@@ -344,7 +349,8 @@
assert(0 && "Unknown regclass!");
abort();
}
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
@@ -388,7 +394,9 @@
abort();
}
- addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ addFrameReference(BuildMI(MBB, MI, DL, get(opc)).addReg(DestReg), FrameIdx);
}
/*!
@@ -424,7 +432,8 @@
assert(0 && "Unknown regclass!");
abort();
}
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -495,7 +504,8 @@
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
- MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32));
+ MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
+ get(SPU::STQDr32));
MIB.addReg(InReg, false, false, isKill);
NewMI = addFrameReference(MIB, FrameIndex);
@@ -503,7 +513,7 @@
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
+ MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
MIB.addReg(OutReg, true, false, false, isDead);
Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
@@ -617,6 +627,8 @@
SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -626,14 +638,14 @@
if (FBB == 0) {
if (Cond.empty()) {
// Unconditional branch
- MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR));
+ MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR));
MIB.addMBB(TBB);
DEBUG(cerr << "Inserted one-way uncond branch: ");
DEBUG((*MIB).dump());
} else {
// Conditional branch
- MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
+ MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
DEBUG(cerr << "Inserted one-way cond branch: ");
@@ -641,8 +653,8 @@
}
return 1;
} else {
- MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
- MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR));
+ MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm()));
+ MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR));
// Two-way Conditional Branch.
MIB.addReg(Cond[1].getReg()).addMBB(TBB);
Modified: llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/CellSPU/SPURegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -428,6 +428,7 @@
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Prepare for debug frame info.
bool hasDebugInfo = MMI && MMI->hasDebugInfo();
@@ -448,38 +449,38 @@
if (hasDebugInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
// for the ABI
- BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
.addReg(SPU::R1);
if (isS10Constant(FrameSize)) {
// Spill $sp to adjusted $sp
- BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
.addReg(SPU::R1);
// Adjust $sp by required amout
- BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
.addImm(FrameSize);
} else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
// $r2 to adjust $sp:
- BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
.addImm(-16)
.addReg(SPU::R1);
- BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
.addImm(FrameSize);
- BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1)
.addReg(SPU::R2)
.addReg(SPU::R1);
- BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
.addReg(SPU::R1)
.addReg(SPU::R2);
- BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
.addReg(SPU::R2)
.addImm(16);
- BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
.addReg(SPU::R2)
.addReg(SPU::R1);
} else {
@@ -508,7 +509,7 @@
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(SPU::R1);
MachineLocation FPSrc(MachineLocation::VirtualFP);
@@ -522,7 +523,7 @@
MachineBasicBlock::iterator MBBI = prior(MBB.end());
// Insert terminator label
unsigned BranchLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId);
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId);
}
}
}
@@ -534,6 +535,7 @@
const MachineFrameInfo *MFI = MF.getFrameInfo();
int FrameSize = MFI->getStackSize();
int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
assert(MBBI->getOpcode() == SPU::RET &&
"Can only insert epilog into returning blocks");
@@ -545,30 +547,30 @@
// Reload $lr, adjust $sp by required amount
// Note: We do this to slightly improve dual issue -- not by much, but it
// is an opportunity for dual issue.
- BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
.addImm(FrameSize + LinkSlotOffset)
.addReg(SPU::R1);
- BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1)
.addReg(SPU::R1)
.addImm(FrameSize);
} else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
// $r2 to adjust $sp:
- BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
.addImm(16)
.addReg(SPU::R1);
- BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
.addImm(FrameSize);
- BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
.addReg(SPU::R1)
.addReg(SPU::R2);
- BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
.addImm(16)
.addReg(SPU::R2);
- BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2).
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
addReg(SPU::R2)
.addImm(16);
- BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
.addReg(SPU::R2)
.addReg(SPU::R1);
} else {
Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64Bundling.cpp Sat Feb 14 07:20:23 2009
@@ -104,7 +104,7 @@
if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
// there is a conflict, insert a stop and reset PendingRegWrites
- CurrentInsn = BuildMI(MBB, CurrentInsn,
+ CurrentInsn = BuildMI(MBB, CurrentInsn, CurrentInsn->getDebugLoc(),
TM.getInstrInfo()->get(IA64::STOP), 0);
PendingRegWrites=OrigWrites; // carry over current writes to next insn
Changed=true; StopBitsAdded++; // update stats
Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -106,6 +106,7 @@
SDValue Chain = N->getOperand(0);
SDValue Tmp1 = N->getOperand(0);
SDValue Tmp2 = N->getOperand(1);
+ DebugLoc dl = N->getDebugLoc();
bool isFP=false;
@@ -140,26 +141,28 @@
if(!isFP) {
// first, load the inputs into FP regs.
TmpF1 =
- SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp1), 0);
Chain = TmpF1.getValue(1);
TmpF2 =
- SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp2), 0);
Chain = TmpF2.getValue(1);
// next, convert the inputs to FP
if(isSigned) {
TmpF3 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF1), 0);
Chain = TmpF3.getValue(1);
TmpF4 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF2), 0);
Chain = TmpF4.getValue(1);
} else { // is unsigned
TmpF3 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF1),
+ 0);
Chain = TmpF3.getValue(1);
TmpF4 =
- SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
+ SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF2),
+ 0);
Chain = TmpF4.getValue(1);
}
@@ -172,11 +175,11 @@
// we start by computing an approximate reciprocal (good to 9 bits?)
// note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
if(isFP)
- TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
- TmpF3, TmpF4), 0);
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, dl, MVT::f64,
+ MVT::i1, TmpF3, TmpF4), 0);
else
- TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
- TmpF3, TmpF4), 0);
+ TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, dl, MVT::f64,
+ MVT::i1, TmpF3, TmpF4), 0);
TmpPR = TmpF5.getValue(1);
Chain = TmpF5.getValue(2);
@@ -184,7 +187,7 @@
SDValue minusB;
if(isModulus) { // for remainders, it'll be handy to have
// copies of -input_b
- minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
+ minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, dl, MVT::i64,
CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
Chain = minusB.getValue(1);
}
@@ -192,19 +195,19 @@
SDValue TmpE0, TmpY1, TmpE1, TmpY2;
SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
- TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
OpsE0, 4), 0);
Chain = TmpE0.getValue(1);
SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
- TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsY1, 4), 0);
Chain = TmpY1.getValue(1);
SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
- TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsE1, 4), 0);
Chain = TmpE1.getValue(1);
SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
- TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsY2, 4), 0);
Chain = TmpY2.getValue(1);
@@ -215,30 +218,30 @@
SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
- TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsE2, 4), 0);
Chain = TmpE2.getValue(1);
SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
- TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsY3, 4), 0);
Chain = TmpY3.getValue(1);
SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
TmpQ0 =
- SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
- OpsQ0, 4), 0);
+ SDValue(CurDAG->getTargetNode(IA64::CFMADS1, dl, // double prec!
+ MVT::f64, OpsQ0, 4), 0);
Chain = TmpQ0.getValue(1);
SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
TmpR0 =
- SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
- OpsR0, 4), 0);
+ SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, dl, // double prec!
+ MVT::f64, OpsR0, 4), 0);
Chain = TmpR0.getValue(1);
// we want Result to have the same target register as the frcpa, so
// we two-address hack it. See the comment "for this to work..." on
// page 48 of Intel application note #245415
SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
- Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
- Ops, 5);
+ Result = CurDAG->getTargetNode(IA64::TCFMADS0, dl, // d.p. s0 rndg!
+ MVT::f64, Ops, 5);
Chain = SDValue(Result, 1);
return Result; // XXX: early exit!
} else { // this is *not* an FP divide, so there's a bit left to do:
@@ -246,11 +249,11 @@
SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
- TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
+ TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
OpsQ2, 4), 0);
Chain = TmpQ2.getValue(1);
SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
- TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
+ TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
OpsR2, 4), 0);
Chain = TmpR2.getValue(1);
@@ -258,7 +261,7 @@
// should two-address hack it. See the comment "for this to work..." on page
// 48 of Intel application note #245415
SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
- TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
+ TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, dl, MVT::f64,
OpsQ3, 5), 0);
Chain = TmpQ3.getValue(1);
@@ -267,26 +270,27 @@
// arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
if(isSigned)
- TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, dl,
MVT::f64, TmpQ3), 0);
else
- TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
+ TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, dl,
MVT::f64, TmpQ3), 0);
Chain = TmpQ.getValue(1);
if(isModulus) {
SDValue FPminusB =
- SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
+ SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, minusB),
+ 0);
Chain = FPminusB.getValue(1);
SDValue Remainder =
- SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
+ SDValue(CurDAG->getTargetNode(IA64::XMAL, dl, MVT::f64,
TmpQ, FPminusB, TmpF1), 0);
Chain = Remainder.getValue(1);
- Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, Remainder);
Chain = SDValue(Result, 1);
} else { // just an integer divide
- Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
+ Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, TmpQ);
Chain = SDValue(Result, 1);
}
@@ -300,6 +304,7 @@
SDNode *N = Op.getNode();
if (N->isMachineOpcode())
return NULL; // Already selected.
+ DebugLoc dl = Op.getDebugLoc();
switch (N->getOpcode()) {
default: break;
@@ -334,22 +339,22 @@
// load the branch target's entry point [mem] and
// GP value [mem+8]
SDValue targetEntryPoint=
- SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other,
+ SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other,
FnDescriptor, CurDAG->getEntryNode()), 0);
Chain = targetEntryPoint.getValue(1);
SDValue targetGPAddr=
- SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
+ SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64,
FnDescriptor,
CurDAG->getConstant(8, MVT::i64)), 0);
Chain = targetGPAddr.getValue(1);
SDValue targetGP =
- SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other,
+ SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other,
targetGPAddr, CurDAG->getEntryNode()), 0);
Chain = targetGP.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag);
InFlag = Chain.getValue(1);
- Chain = CurDAG->getCopyToReg(Chain, IA64::B6,
+ Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6,
targetEntryPoint, InFlag); // FLAG these?
InFlag = Chain.getValue(1);
@@ -359,11 +364,11 @@
// Finally, once everything is setup, emit the call itself
if (InFlag.getNode())
- Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperand, InFlag), 0);
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
+ MVT::Flag, CallOperand, InFlag), 0);
else // there might be no arguments
- Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
- CallOperand, Chain), 0);
+ Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
+ MVT::Flag, CallOperand, Chain), 0);
InFlag = Chain.getValue(1);
std::vector<SDValue> CallResults;
@@ -378,7 +383,7 @@
case IA64ISD::GETFD: {
SDValue Input = N->getOperand(0);
- return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
+ return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input);
}
case ISD::FDIV:
@@ -394,10 +399,10 @@
SDValue V;
ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
if (N2->getValueAPF().isPosZero()) {
- V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
+ V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64);
} else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
APFloat(+1.0f) : APFloat(+1.0))) {
- V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
+ V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
} else
assert(0 && "Unexpected FP constant!");
@@ -411,7 +416,7 @@
return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
else
- return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
+ return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
@@ -421,7 +426,7 @@
Constant *C = CP->getConstVal();
SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
- return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+ return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
}
@@ -429,10 +434,10 @@
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDValue Tmp =
- SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
+ SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64), GA), 0);
- return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp,
+ return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp,
CurDAG->getEntryNode());
}
@@ -441,11 +446,11 @@
SDValue EA = CurDAG->getTargetExternalSymbol(
cast<ExternalSymbolSDNode>(N)->getSymbol(),
MVT::i64);
- SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
+ SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64),
EA);
- return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
+ return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp);
}
*/
@@ -465,9 +470,11 @@
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
- return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
- SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
- CurDAG->getRegister(IA64::r0, MVT::i64),
+ return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
+ SDValue(CurDAG->getTargetNode(Opc, dl,
+ MVT::i64,
+ Address), 0),
+ CurDAG->getRegister(IA64::r0, MVT::i64),
Chain);
}
/* otherwise, we want to load a bool into something bigger: LD1
@@ -499,12 +506,12 @@
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
// first load zero!
- SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
+ SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
SDValue Tmp = ST->getValue();
Tmp =
- SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
+ SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial,
CurDAG->getTargetConstant(1,
MVT::i64),
Tmp), 0);
Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64ISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -197,8 +197,8 @@
// FP args go into f8..f15 as needed: (hence the ++)
argPreg[count] = args_FP[used_FPArgs++];
argOpc[count] = IA64::FMOV;
- argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
- MVT::f64);
+ argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), dl,
+ argVreg[count], MVT::f64);
if (I->getType() == Type::FloatTy)
argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt,
DAG.getIntPtrConstant(0));
@@ -217,7 +217,7 @@
argPreg[count] = args_int[count];
argOpc[count] = IA64::MOV;
argt = newroot =
- DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
+ DAG.getCopyFromReg(DAG.getRoot(), dl, argVreg[count], MVT::i64);
if ( getValueType(I->getType()) != MVT::i64)
argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()),
newroot);
@@ -243,7 +243,7 @@
// Create a vreg to hold the output of (what will become)
// the "alloc" instruction
VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
- BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
+ BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
// we create a PSEUDO_ALLOC (pseudo)instruction for now
/*
BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
@@ -273,14 +273,14 @@
// here we actually do the moving of args, and store them to the stack
// too if this is a varargs function:
for (int i = 0; i < count && i < 8; ++i) {
- BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
+ BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
if(F.isVarArg()) {
// if this is a varargs function, we copy the input registers to the stack
int FI = MFI->CreateFixedObject(8, tempOffset);
tempOffset+=8; //XXX: is it safe to use r22 like this?
- BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
+ BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
// FIXME: we should use st8.spill here, one day
- BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
+ BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
}
}
@@ -423,13 +423,16 @@
SDValue InFlag;
// save the current GP, SP and RP : FIXME: do we need to do all 3 always?
- SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
+ SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r1,
+ MVT::i64, InFlag);
Chain = GPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
- SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
+ SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r12,
+ MVT::i64, InFlag);
Chain = SPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
- SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
+ SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::rp,
+ MVT::i64, InFlag);
Chain = RPBeforeCall.getValue(1);
InFlag = Chain.getValue(2);
@@ -444,8 +447,8 @@
unsigned seenConverts = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
if(RegValuesToPass[i].getValueType().isFloatingPoint()) {
- Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
- InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, IntArgRegs[i],
+ Converts[seenConverts++], InFlag);
InFlag = Chain.getValue(1);
}
}
@@ -453,7 +456,7 @@
// next copy args into the usual places, these are flagged
unsigned usedFPArgs = 0;
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain,
+ Chain = DAG.getCopyToReg(Chain, dl,
RegValuesToPass[i].getValueType().isInteger() ?
IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
InFlag = Chain.getValue(1);
@@ -486,11 +489,11 @@
InFlag = Chain.getValue(1);
// restore the GP, SP and RP after the call
- Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, IA64::r1, GPBeforeCall, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, IA64::r12, SPBeforeCall, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, IA64::rp, RPBeforeCall, InFlag);
InFlag = Chain.getValue(1);
std::vector<MVT> RetVals;
@@ -505,10 +508,12 @@
case MVT::i1: { // bools are just like other integers (returned in r8)
// we *could* fall through to the truncate below, but this saves a
// few redundant predicate ops
- SDValue boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
+ SDValue boolInR8 = DAG.getCopyFromReg(Chain, dl, IA64::r8,
+ MVT::i64,InFlag);
InFlag = boolInR8.getValue(2);
Chain = boolInR8.getValue(1);
- SDValue zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
+ SDValue zeroReg = DAG.getCopyFromReg(Chain, dl, IA64::r0,
+ MVT::i64, InFlag);
InFlag = zeroReg.getValue(2);
Chain = zeroReg.getValue(1);
@@ -518,7 +523,7 @@
case MVT::i8:
case MVT::i16:
case MVT::i32:
- RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
Chain = RetVal.getValue(1);
// keep track of whether it is sign or zero extended (todo: bools?)
@@ -529,18 +534,18 @@
RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
break;
case MVT::i64:
- RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2); // XXX dead
break;
case MVT::f32:
- RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal,
DAG.getIntPtrConstant(0));
break;
case MVT::f64:
- RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
+ RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
InFlag = RetVal.getValue(2); // XXX dead
break;
@@ -554,6 +559,7 @@
SDValue IA64TargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
default: assert(0 && "Should not custom lower this!");
case ISD::GlobalTLSAddress:
@@ -566,21 +572,21 @@
assert(0 && "Do not know how to return this many arguments!");
abort();
case 1:
- AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
- AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
+ AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
+ AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS,
AR_PFSVal);
- return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
+ return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal);
case 3: {
// Copy the result into the output register & restore ar.pfs
MVT ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8;
- AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
- Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
- SDValue());
- AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
- Copy.getValue(1));
- return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
+ AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
+ Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg,
+ Op.getOperand(1), SDValue());
+ AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl,
+ IA64::AR_PFS, AR_PFSVal, Copy.getValue(1));
+ return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other,
AR_PFSVal, AR_PFSVal.getValue(1));
}
}
@@ -589,24 +595,24 @@
case ISD::VAARG: {
MVT VT = getPointerTy();
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
+ SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1),
SV, 0);
// Increment the pointer, VAList, to the next vaarg
- SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
+ SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
VT));
// Store the incremented VAList to the legalized pointer
- VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
+ VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr,
Op.getOperand(1), SV, 0);
// Load the actual argument out of the pointer VAList
- return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
+ return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0);
}
case ISD::VASTART: {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
+ return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
}
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64InstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -55,28 +55,33 @@
IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond)const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
- BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(IA64::BRL_NOTCALL)).addMBB(TBB);
return 1;
}
bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const {
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
// Not yet supported!
return false;
}
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
// (SrcReg) DestReg = cmp.eq.unc(r0, r0)
- BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg)
+ BuildMI(MBB, MI, DL, get(IA64::PCMPEQUNC), DestReg)
.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
else // otherwise, MOV works (for both gen. regs and FP regs)
- BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(IA64::MOV), DestReg).addReg(SrcReg);
return true;
}
@@ -86,30 +91,34 @@
unsigned SrcReg, bool isKill,
int FrameIdx,
const TargetRegisterClass *RC) const{
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
+ BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
.addReg(SrcReg, false, false, isKill);
} else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx)
+ BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx)
.addReg(SrcReg, false, false, isKill);
} else if (RC == IA64::PRRegisterClass) {
/* we use IA64::r2 as a temporary register for doing this hackery. */
// first we load 0:
- BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
+ BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
// then conditionally add 1:
- BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
+ BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
.addImm(1).addReg(SrcReg, false, false, isKill);
// and then store it to the stack
- BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
+ BuildMI(MBB, MI, DL, get(IA64::ST8))
+ .addFrameIndex(FrameIdx)
+ .addReg(IA64::r2);
} else assert(0 &&
"sorry, I don't know how to store this sort of reg in the stack\n");
}
void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
if (RC == IA64::FPRegisterClass) {
@@ -123,7 +132,8 @@
"sorry, I don't know how to store this sort of reg\n");
}
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -140,28 +150,34 @@
}
void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
- unsigned DestReg, int FrameIdx,
- const TargetRegisterClass *RC)const{
+ MachineBasicBlock::iterator MI,
+ unsigned DestReg, int FrameIdx,
+ const TargetRegisterClass *RC)const{
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
+ BuildMI(MBB, MI, DL, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::GRRegisterClass) {
- BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
- } else if (RC == IA64::PRRegisterClass) {
- // first we load a byte from the stack into r2, our 'predicate hackery'
- // scratch reg
- BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
- // then we compare it to zero. If it _is_ zero, compare-not-equal to
- // r0 gives us 0, which is what we want, so that's nice.
- BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
- } else assert(0 &&
- "sorry, I don't know how to load this sort of reg from the stack\n");
+ BuildMI(MBB, MI, DL, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
+ } else if (RC == IA64::PRRegisterClass) {
+ // first we load a byte from the stack into r2, our 'predicate hackery'
+ // scratch reg
+ BuildMI(MBB, MI, DL, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
+ // then we compare it to zero. If it _is_ zero, compare-not-equal to
+ // r0 gives us 0, which is what we want, so that's nice.
+ BuildMI(MBB, MI, DL, get(IA64::CMPNE), DestReg)
+ .addReg(IA64::r2)
+ .addReg(IA64::r0);
+ } else {
+ assert(0 &&
+ "sorry, I don't know how to load this sort of reg from the stack\n");
+ }
}
void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
if (RC == IA64::FPRegisterClass) {
@@ -172,10 +188,11 @@
Opc = IA64::LD1;
} else {
assert(0 &&
- "sorry, I don't know how to store this sort of reg\n");
+ "sorry, I don't know how to load this sort of reg\n");
}
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
Modified: llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/IA64/IA64RegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -88,6 +88,7 @@
// <amt>'
MachineInstr *Old = I;
unsigned Amount = Old->getOperand(0).getImm();
+ DebugLoc dl = Old->getDebugLoc();
if (Amount != 0) {
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next
@@ -97,12 +98,12 @@
// Replace the pseudo instruction with a new instruction...
if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
- BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
- .addImm(-Amount);
+ BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12)
+ .addReg(IA64::r12).addImm(-Amount);
} else {
assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
- BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
- .addImm(Amount);
+ BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12)
+ .addReg(IA64::r12).addImm(Amount);
}
}
}
@@ -118,6 +119,7 @@
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
+ DebugLoc dl = MI.getDebugLoc();
bool FP = hasFP(MF);
@@ -146,13 +148,13 @@
// Fix up the old:
MI.getOperand(i).ChangeToRegister(IA64::r22, false);
//insert the new
- BuildMI(MBB, II, TII.get(IA64::ADDIMM22), IA64::r22)
+ BuildMI(MBB, II, dl, TII.get(IA64::ADDIMM22), IA64::r22)
.addReg(BaseRegister).addImm(Offset);
} else { // it's big
//fix up the old:
MI.getOperand(i).ChangeToRegister(IA64::r22, false);
- BuildMI(MBB, II, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
- BuildMI(MBB, II, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
+ BuildMI(MBB, II, dl, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
+ BuildMI(MBB, II, dl, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
.addReg(IA64::r22);
}
@@ -163,6 +165,7 @@
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
bool FP = hasFP(MF);
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// first, we handle the 'alloc' instruction, that should be right up the
// top of any function
@@ -205,7 +208,7 @@
}
}
- BuildMI(MBB, MBBI, TII.get(IA64::ALLOC)).
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ALLOC)).
addReg(dstRegOfPseudoAlloc).addImm(0).
addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
@@ -230,23 +233,24 @@
// adjust stack pointer: r12 -= numbytes
if (NumBytes <= 8191) {
- BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
addImm(-NumBytes);
} else { // we use r22 as a scratch register here
// first load the decrement into r22
- BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22).
+ addImm(-NumBytes);
// FIXME: MOVLSI32 expects a _u_32imm
// then add (subtract) it to r12 (stack ptr)
- BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12)
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12)
.addReg(IA64::r12).addReg(IA64::r22);
}
// now if we need to, save the old FP and set the new
if (FP) {
- BuildMI(MBB, MBBI, TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
+ BuildMI(MBB, MBBI,dl,TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
// this must be the last instr in the prolog ? (XXX: why??)
- BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
}
}
@@ -257,6 +261,7 @@
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == IA64::RET &&
"Can only insert epilog into returning blocks");
+ DebugLoc dl = DebugLoc::getUnknownLoc();
bool FP = hasFP(MF);
@@ -267,20 +272,20 @@
if (FP)
{
//copy the FP into the SP (discards allocas)
- BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
//restore the FP
- BuildMI(MBB, MBBI, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
}
if (NumBytes != 0)
{
if (NumBytes <= 8191) {
- BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
- addImm(NumBytes);
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).
+ addReg(IA64::r12).addImm(NumBytes);
} else {
- BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22).
addImm(NumBytes);
- BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
+ BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
addReg(IA64::r22);
}
}
Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsDelaySlotFiller.cpp Sat Feb 14 07:20:23 2009
@@ -62,7 +62,7 @@
if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
- BuildMI(MBB, J, TII->get(Mips::NOP));
+ BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP));
++FilledSlots;
Changed = true;
}
Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -126,8 +126,9 @@
break;
}
assert(GP && "GOT PTR not in liveins");
+ // FIXME is there a sensible place to get debug info for this?
return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
- GP, MVT::i32);
+ DebugLoc::getUnknownLoc(), GP, MVT::i32);
}
/// ComplexPattern used on MipsInstrInfo
@@ -187,6 +188,7 @@
{
SDNode *Node = N.getNode();
unsigned Opcode = Node->getOpcode();
+ DebugLoc dl = Node->getDebugLoc();
// Dump information about the Node being selected
#ifndef NDEBUG
@@ -238,8 +240,8 @@
SDValue RHS = Node->getOperand(1);
MVT VT = LHS.getValueType();
- SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
- SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
+ SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, dl, VT, Ops, 2);
+ SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT,
SDValue(Carry,0), RHS);
return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
@@ -260,13 +262,13 @@
else
Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
- SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, MVT::i32,
+ SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32,
MVT::Flag, InFlag);
InFlag = SDValue(Lo,1);
- SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
+ SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
if (!N.getValue(0).use_empty())
ReplaceUses(N.getValue(0), SDValue(Lo,0));
@@ -285,14 +287,15 @@
SDValue MulOp2 = Node->getOperand(1);
unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
- SDNode *MulNode = CurDAG->getTargetNode(MulOp, MVT::Flag, MulOp1, MulOp2);
+ SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl,
+ MVT::Flag, MulOp1, MulOp2);
SDValue InFlag = SDValue(MulNode, 0);
if (MulOp == ISD::MUL)
- return CurDAG->getTargetNode(Mips::MFLO, MVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag);
else
- return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, InFlag);
+ return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
}
/// Div/Rem operations
@@ -311,10 +314,10 @@
Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
MOp = Mips::MFHI;
}
- SDNode *Node = CurDAG->getTargetNode(Op, MVT::Flag, Op1, Op2);
+ SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
SDValue InFlag = SDValue(Node, 0);
- return CurDAG->getTargetNode(MOp, MVT::i32, InFlag);
+ return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag);
}
// Get target GOT address.
@@ -344,18 +347,18 @@
// Use load to get GOT target
SDValue Ops[] = { Callee, GPReg, Chain };
- SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, MVT::i32,
+ SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32,
MVT::Other, Ops, 3), 0);
Chain = Load.getValue(1);
// Call target must be on T9
- Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Load, InFlag);
} else
/// Indirect call
- Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag);
+ Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag);
// Emit Jump and Link Register
- SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
+ SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other,
MVT::Flag, T9Reg, Chain);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -280,6 +280,7 @@
{
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
bool isFPCmp = false;
+ DebugLoc dl = MI->getDebugLoc();
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");
@@ -317,9 +318,9 @@
Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
// Get the branch opcode from the branch code.
unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
- BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
+ BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
} else
- BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
+ BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
.addReg(Mips::ZERO).addMBB(sinkMBB);
F->insert(It, copy0MBB);
@@ -348,7 +349,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
@@ -367,22 +368,23 @@
{
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
+ DebugLoc dl = Op.getDebugLoc();
// Get a reference from Mips stack pointer
- SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32);
+ SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
// Subtract the dynamic size from the actual stack size to
// obtain the new stack size.
- SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size);
+ SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
// The Sub result contains the new stack start address, so it
// must be placed in the stack pointer register.
- Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub);
+ Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
// This node always has two return values: a new stack pointer
// value and a chain
SDValue Ops[2] = { Sub, Chain };
- return DAG.getMergeValues(Ops, 2);
+ return DAG.getMergeValues(Ops, 2, dl);
}
SDValue MipsTargetLowering::
@@ -390,19 +392,20 @@
{
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
-
+ DebugLoc dl = Op.getDebugLoc();
+
if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
return Op;
SDValue True = DAG.getConstant(1, MVT::i32);
SDValue False = DAG.getConstant(0, MVT::i32);
- SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
+ SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
LHS, True, False, LHS.getOperand(2));
- SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
+ SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
RHS, True, False, RHS.getOperand(2));
- return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL);
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
}
SDValue MipsTargetLowering::
@@ -412,6 +415,7 @@
// the block to branch to if the condition is true.
SDValue Chain = Op.getOperand(0);
SDValue Dest = Op.getOperand(2);
+ DebugLoc dl = Op.getDebugLoc();
if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
return Op;
@@ -422,7 +426,7 @@
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
- return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
+ return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Dest, CondRes);
}
@@ -433,11 +437,12 @@
// and #1) and the condition code to compare them with (op #2) as a
// CondCodeSDNode.
SDValue LHS = Op.getOperand(0);
- SDValue RHS = Op.getOperand(1);
+ SDValue RHS = Op.getOperand(1);
+ DebugLoc dl = Op.getDebugLoc();
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
- return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
+ return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
}
@@ -447,6 +452,7 @@
SDValue Cond = Op.getOperand(0);
SDValue True = Op.getOperand(1);
SDValue False = Op.getOperand(2);
+ DebugLoc dl = Op.getDebugLoc();
// if the incomming condition comes from a integer compare, the select
// operation must be SelectCC or a conditional move if the subtarget
@@ -454,20 +460,22 @@
if (Cond.getOpcode() != MipsISD::FPCmp) {
if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
return Op;
- return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
+ return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
Cond, True, False);
}
// if the incomming condition comes from fpcmp, the select
// operation must use FPSelectCC.
SDValue CCNode = Cond.getOperand(2);
- return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
+ return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
Cond, True, False, CCNode);
}
SDValue MipsTargetLowering::
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
{
+ // FIXME there isn't actually debug info here
+ DebugLoc dl = Op.getDebugLoc();
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
@@ -476,23 +484,24 @@
SDValue Ops[] = { GA };
// %gp_rel relocation
if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
- SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
- SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
- return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
+ SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, 1, Ops, 1);
+ SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
}
// %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
- SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
- return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
} else { // Abicall relocations, TODO: make this cleaner.
- SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
+ SDValue ResNode = DAG.getLoad(MVT::i32, dl,
+ DAG.getEntryNode(), GA, NULL, 0);
// On functions and global targets not internal linked only
// a load from got/GP is necessary for PIC to work.
if (!GV->hasLocalLinkage() || isa<Function>(GV))
return ResNode;
- SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
- return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
}
assert(0 && "Dont know how to handle GlobalAddress");
@@ -511,6 +520,8 @@
{
SDValue ResNode;
SDValue HiPart;
+ // FIXME there isn't actually debug info here
+ DebugLoc dl = Op.getDebugLoc();
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
@@ -519,12 +530,12 @@
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
SDValue Ops[] = { JTI };
- HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
+ HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, 1, Ops, 1);
} else // Emit Load from Global Pointer
- HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
+ HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0);
- SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
- ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
+ ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
return ResNode;
}
@@ -536,6 +547,8 @@
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Constant *C = N->getConstVal();
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
+ // FIXME there isn't actually debug info here
+ DebugLoc dl = Op.getDebugLoc();
// gp_rel relocation
// FIXME: we should reference the constant pool using small data sections,
@@ -545,12 +558,12 @@
//if (!Subtarget->hasABICall() &&
// IsInSmallSection(getTargetData()->getTypePaddedSize(C->getType()))) {
// SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
- // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
+ // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
// ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
//} else { // %hi/%lo relocation
- SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
- SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
- ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
+ SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
+ ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
//}
return ResNode;
@@ -586,6 +599,7 @@
SDValue Callee = TheCall->getCallee();
bool isVarArg = TheCall->isVarArg();
unsigned CC = TheCall->getCallingConv();
+ DebugLoc dl = TheCall->getDebugLoc();
MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -627,13 +641,13 @@
default: assert(0 && "Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
- Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::ZExt:
- Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::AExt:
- Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
break;
}
@@ -659,13 +673,13 @@
// emit ISD::STORE whichs stores the
// parameter value to a stack Location
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
}
// Transform all store nodes into one single node because all store
// nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -674,7 +688,7 @@
// stuck together.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
@@ -706,7 +720,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
- Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
+ Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node.
@@ -736,9 +750,9 @@
// Reload GP value.
FI = MipsFI->getGPFI();
SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
- SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
+ SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0);
Chain = GPLoad.getValue(1);
- Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
+ Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
GPLoad, SDValue(0,0));
InFlag = Chain.getValue(1);
}
@@ -758,6 +772,7 @@
unsigned CallingConv, SelectionDAG &DAG) {
bool isVarArg = TheCall->isVarArg();
+ DebugLoc dl = TheCall->getDebugLoc();
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
@@ -768,7 +783,7 @@
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
- Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
+ Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
RVLocs[i].getValVT(), InFlag).getValue(1);
InFlag = Chain.getValue(2);
ResultVals.push_back(Chain.getValue(0));
@@ -777,7 +792,7 @@
ResultVals.push_back(Chain);
// Merge everything together with a MERGE_VALUES node.
- return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
&ResultVals[0], ResultVals.size()).getNode();
}
@@ -796,6 +811,7 @@
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+ DebugLoc dl = Op.getDebugLoc();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
@@ -840,20 +856,20 @@
// Transform the arguments stored on
// physical registers into virtual ones
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
- SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
+ SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted
// to 32 bits. Insert an assert[sz]ext to capture this, then
// truncate to the right size.
if (VA.getLocInfo() == CCValAssign::SExt)
- ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
+ ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
else if (VA.getLocInfo() == CCValAssign::ZExt)
- ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
+ ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
if (VA.getLocInfo() != CCValAssign::Full)
- ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
+ ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
ArgValues.push_back(ArgValue);
@@ -877,7 +893,7 @@
// emit ISD::STORE whichs stores the
// parameter value to a stack Location
- ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
+ ArgValues.push_back(DAG.getStore(Root, dl, ArgValue, PtrOff, NULL, 0));
}
} else { // VA.isRegLoc()
@@ -900,7 +916,7 @@
// Create load nodes to retrieve arguments from the stack
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
+ ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
}
}
@@ -913,14 +929,14 @@
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
MipsFI->setSRetReturnReg(Reg);
}
- SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
+ SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
+ Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
}
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
}
@@ -936,6 +952,7 @@
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
+ DebugLoc dl = Op.getDebugLoc();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
@@ -962,7 +979,8 @@
// ISD::RET => ret chain, (regnum1,val1), ...
// So i*2+1 index only the regnums
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ Op.getOperand(i*2+1), Flag);
// guarantee that all emitted copies are
// stuck together, avoiding something bad
@@ -980,18 +998,18 @@
if (!Reg)
assert(0 && "sret virtual register not created in the entry block");
- SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
- Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Flag = Chain.getValue(1);
}
// Return on Mips is always a "jr $ra"
if (Flag.getNode())
- return DAG.getNode(MipsISD::Ret, MVT::Other,
+ return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
else // Return Void
- return DAG.getNode(MipsISD::Ret, MVT::Other,
+ return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Chain, DAG.getRegister(Mips::RA, MVT::i32));
}
Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsInstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -118,7 +118,9 @@
void MipsInstrInfo::
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
{
- BuildMI(MBB, MI, get(Mips::NOP));
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ BuildMI(MBB, MI, DL, get(Mips::NOP));
}
bool MipsInstrInfo::
@@ -126,22 +128,25 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (DestRC != SrcRC) {
if ((DestRC == Mips::CPURegsRegisterClass) &&
(SrcRC == Mips::FGR32RegisterClass))
- BuildMI(MBB, I, get(Mips::MFC1), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
else if ((DestRC == Mips::CPURegsRegisterClass) &&
(SrcRC == Mips::AFGR32RegisterClass))
- BuildMI(MBB, I, get(Mips::MFC1A), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::MFC1A), DestReg).addReg(SrcReg);
else if ((DestRC == Mips::FGR32RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass))
- BuildMI(MBB, I, get(Mips::MTC1), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
else if ((DestRC == Mips::AFGR32RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass))
- BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
else if ((DestRC == Mips::AFGR32RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass))
- BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
else if ((SrcRC == Mips::CCRRegisterClass) &&
(SrcReg == Mips::FCR31))
return true; // This register is used implicitly, no copy needed.
@@ -151,11 +156,11 @@
else if ((DestRC == Mips::HILORegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass)) {
unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
- BuildMI(MBB, I, get(Opc), DestReg);
+ BuildMI(MBB, I, DL, get(Opc), DestReg);
} else if ((SrcRC == Mips::HILORegisterClass) &&
(DestRC == Mips::CPURegsRegisterClass)) {
unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
- BuildMI(MBB, I, get(Opc), DestReg);
+ BuildMI(MBB, I, DL, get(Opc), DestReg);
} else
// DestRC != SrcRC, Can't copy this register
return false;
@@ -164,14 +169,14 @@
}
if (DestRC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
+ BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
.addReg(SrcReg);
else if (DestRC == Mips::FGR32RegisterClass)
- BuildMI(MBB, I, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
else if (DestRC == Mips::AFGR32RegisterClass)
- BuildMI(MBB, I, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
else if (DestRC == Mips::AFGR64RegisterClass)
- BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
else
// Can't copy this register
return false;
@@ -181,10 +186,14 @@
void MipsInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned SrcReg, bool isKill, int FI,
- const TargetRegisterClass *RC) const
+ unsigned SrcReg, bool isKill, int FI,
+ const TargetRegisterClass *RC) const
{
unsigned Opc;
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (RC == Mips::CPURegsRegisterClass)
Opc = Mips::SW;
else if (RC == Mips::FGR32RegisterClass)
@@ -196,7 +205,7 @@
else
assert(0 && "Can't store this register to stack slot");
- BuildMI(MBB, I, get(Opc)).addReg(SrcReg, false, false, isKill)
+ BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill)
.addImm(0).addFrameIndex(FI);
}
@@ -216,7 +225,8 @@
else
assert(0 && "Can't store this register");
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
@@ -248,12 +258,14 @@
else
assert(0 && "Can't load this register from stack slot");
- BuildMI(MBB, I, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+ BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
}
void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc;
if (RC == Mips::CPURegsRegisterClass)
@@ -267,7 +279,8 @@
else
assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -299,12 +312,13 @@
if (Ops[0] == 0) { // COPY -> STORE
unsigned SrcReg = MI->getOperand(2).getReg();
bool isKill = MI->getOperand(2).isKill();
- NewMI = BuildMI(MF, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
+ .addReg(SrcReg, false, false, isKill)
.addImm(0).addFrameIndex(FI);
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(Mips::LW))
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
.addReg(DstReg, true, false, false, isDead)
.addImm(0).addFrameIndex(FI);
}
@@ -331,12 +345,13 @@
if (Ops[0] == 0) { // COPY -> STORE
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = BuildMI(MF, get(StoreOpc)).addReg(SrcReg, false, false, isKill)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
+ .addReg(SrcReg, false, false, isKill)
.addImm(0).addFrameIndex(FI) ;
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(LoadOpc))
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
.addReg(DstReg, true, false, false, isDead)
.addImm(0).addFrameIndex(FI);
}
@@ -539,6 +554,8 @@
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
@@ -547,18 +564,18 @@
if (FBB == 0) { // One way branch.
if (Cond.empty()) {
// Unconditional branch?
- BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
.addReg(Cond[2].getReg())
.addMBB(TBB);
else
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
.addMBB(TBB);
}
@@ -570,12 +587,12 @@
const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
- BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
.addMBB(TBB);
else
- BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
+ BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
- BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
+ BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
return 2;
}
Modified: llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Mips/MipsRegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -391,6 +391,7 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
// Get the right frame order for Mips.
@@ -405,21 +406,21 @@
int FPOffset = MipsFI->getFPStackOffset();
int RAOffset = MipsFI->getRAStackOffset();
- BuildMI(MBB, MBBI, TII.get(Mips::NOREORDER));
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
// TODO: check need from GP here.
if (isPIC && Subtarget.isABI_O32())
- BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
- BuildMI(MBB, MBBI, TII.get(Mips::NOMACRO));
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
// Adjust stack : addi sp, sp, (-imm)
- BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP).addImm(-StackSize);
// Save the return address only if the function isnt a leaf one.
// sw $ra, stack_loc($sp)
if (MFI->hasCalls()) {
- BuildMI(MBB, MBBI, TII.get(Mips::SW))
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
}
@@ -427,17 +428,17 @@
// to point to the stack pointer
if (hasFP(MF)) {
// sw $fp,stack_loc($sp)
- BuildMI(MBB, MBBI, TII.get(Mips::SW))
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
// move $fp, $sp
- BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
.addReg(Mips::SP).addReg(Mips::ZERO);
}
// PIC speficic function prologue
if ((isPIC) && (MFI->hasCalls())) {
- BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
.addImm(MipsFI->getGPStackOffset());
}
}
@@ -448,6 +449,7 @@
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Get the number of bytes from FrameInfo
int NumBytes = (int) MFI->getStackSize();
@@ -460,24 +462,24 @@
// stack pointer
if (hasFP(MF)) {
// move $sp, $fp
- BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
.addReg(Mips::FP).addReg(Mips::ZERO);
// lw $fp,stack_loc($sp)
- BuildMI(MBB, MBBI, TII.get(Mips::LW))
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
}
// Restore the return address only if the function isnt a leaf one.
// lw $ra, stack_loc($sp)
if (MFI->hasCalls()) {
- BuildMI(MBB, MBBI, TII.get(Mips::LW))
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
}
// adjust stack : insert addi sp, sp, (imm)
if (NumBytes) {
- BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
+ BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP).addImm(NumBytes);
}
}
Modified: llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -305,14 +305,16 @@
MachineFunction &MF = DAG.getMachineFunction();
const Function *Func = MF.getFunction();
const std::string Name = Func->getName();
-
+
FrameIndexSDNode *FR = dyn_cast<FrameIndexSDNode>(SDValue(N,0));
+ // FIXME there isn't really debug info here
+ DebugLoc dl = FR->getDebugLoc();
int Index = FR->getIndex();
SDValue FI[2];
FI[0] = DAG.getTargetFrameIndex(Index, MVT::i8);
FI[1] = DAG.getTargetFrameIndex(Index + 1, MVT::i8);
- return DAG.getNode(ISD::BUILD_PAIR, N->getValueType(0), FI[0], FI[1]);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), FI[0], FI[1]);
}
@@ -323,12 +325,13 @@
SDValue Ptr = St->getBasePtr();
MVT ValueType = Src.getValueType();
unsigned StoreOffset = 0;
+ DebugLoc dl = N->getDebugLoc();
SDValue PtrLo, PtrHi;
- LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset);
+ LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl);
if (ValueType == MVT::i8) {
- return DAG.getNode (PIC16ISD::PIC16Store, MVT::Other, Chain, Src,
+ return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src,
PtrLo, PtrHi,
DAG.getConstant (0 + StoreOffset, MVT::i8));
}
@@ -341,16 +344,16 @@
ChainLo = Chain.getOperand(0);
ChainHi = Chain.getOperand(1);
}
- SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other,
+ SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
ChainLo,
SrcLo, PtrLo, PtrHi,
DAG.getConstant (0 + StoreOffset, MVT::i8));
- SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi,
+ SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi,
SrcHi, PtrLo, PtrHi,
DAG.getConstant (1 + StoreOffset, MVT::i8));
- return DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1),
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1),
getChain(Store2));
}
else if (ValueType == MVT::i32) {
@@ -378,28 +381,28 @@
ChainHi1 = ChainHi.getOperand(0);
ChainHi2 = ChainHi.getOperand(1);
}
- SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other,
+ SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other,
ChainLo1,
SrcLo1, PtrLo, PtrHi,
DAG.getConstant (0 + StoreOffset, MVT::i8));
- SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainLo2,
+ SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2,
SrcLo2, PtrLo, PtrHi,
DAG.getConstant (1 + StoreOffset, MVT::i8));
- SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi1,
+ SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1,
SrcHi1, PtrLo, PtrHi,
DAG.getConstant (2 + StoreOffset, MVT::i8));
- SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, MVT::Other, ChainHi2,
+ SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2,
SrcHi2, PtrLo, PtrHi,
DAG.getConstant (3 + StoreOffset, MVT::i8));
- SDValue RetLo = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store1),
- getChain(Store2));
- SDValue RetHi = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(Store3),
- getChain(Store4));
- return DAG.getNode(ISD::TokenFactor, MVT::Other, RetLo, RetHi);
+ SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ getChain(Store1), getChain(Store2));
+ SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ getChain(Store3), getChain(Store4));
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi);
}
else {
@@ -411,26 +414,30 @@
SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
{
ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
+ // FIXME there isn't really debug info here
+ DebugLoc dl = ES->getDebugLoc();
SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8);
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, MVT::i8, TES);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, MVT::i8, TES);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES);
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i16, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
}
// ExpandGlobalAddress -
SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
+ // FIXME there isn't really debug info here
+ DebugLoc dl = G->getDebugLoc();
SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
G->getOffset());
- SDValue Lo = DAG.getNode(PIC16ISD::Lo, MVT::i8, TGA);
- SDValue Hi = DAG.getNode(PIC16ISD::Hi, MVT::i8, TGA);
+ SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA);
+ SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA);
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i16, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
}
bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
@@ -499,9 +506,9 @@
}
void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
-
SDValue &Lo, SDValue &Hi) {
SDNode *N = Op.getNode();
+ DebugLoc dl = N->getDebugLoc();
MVT NewVT;
std::vector<SDValue> Opers;
NewVT = getTypeToTransformTo(N->getValueType(0));
@@ -509,12 +516,12 @@
// extract the lo component
Opers.push_back(Op);
Opers.push_back(DAG.getConstant(0,MVT::i8));
- Lo = DAG.getNode(ISD::EXTRACT_ELEMENT,NewVT,&Opers[0],Opers.size());
+ Lo = DAG.getNode(ISD::EXTRACT_ELEMENT,dl,NewVT,&Opers[0],Opers.size());
// extract the hi component
Opers.clear();
Opers.push_back(Op);
Opers.push_back(DAG.getConstant(1,MVT::i8));
- Hi = DAG.getNode(ISD::EXTRACT_ELEMENT,NewVT,&Opers[0],Opers.size());
+ Hi = DAG.getNode(ISD::EXTRACT_ELEMENT,dl,NewVT,&Opers[0],Opers.size());
}
// Legalize FrameIndex into ExternalSymbol and offset.
@@ -549,7 +556,7 @@
void PIC16TargetLowering:: LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
SDValue &Lo, SDValue &Hi,
- unsigned &Offset) {
+ unsigned &Offset, DebugLoc dl) {
// Offset, by default, should be 0
Offset = 0;
@@ -608,8 +615,8 @@
GetExpandedParts(Ptr, DAG, Lo, Hi);
// Put the hi and lo parts into FSR.
- Lo = DAG.getNode(PIC16ISD::MTLO, MVT::i8, Lo);
- Hi = DAG.getNode(PIC16ISD::MTHI, MVT::i8, Hi);
+ Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo);
+ Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi);
return;
}
@@ -631,6 +638,7 @@
LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
+ DebugLoc dl = LD->getDebugLoc();
SDValue Load, Offset;
SDVTList Tys;
@@ -640,7 +648,7 @@
// Legalize direct/indirect addresses. This will give the lo and hi parts
// of the address and the offset.
- LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset);
+ LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, LoadOffset, dl);
// Load from the pointer (direct address or FSR)
VT = N->getValueType(0);
@@ -653,7 +661,7 @@
// Add the pointer offset if any
Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
Tys = DAG.getVTList(MVT::i8, MVT::Other);
- Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Chain, PtrLo, PtrHi,
+ Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
Offset);
PICLoads.push_back(Load);
}
@@ -675,7 +683,7 @@
for (iter=0; iter<MemBytes; ++iter) {
// Add the pointer offset if any
Offset = DAG.getConstant(iter + LoadOffset, MVT::i8);
- Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Chain, PtrLo, PtrHi,
+ Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi,
Offset);
PICLoads.push_back(Load);
}
@@ -684,7 +692,7 @@
if (ISD::isSEXTLoad(N)) {
// For all ExtdBytes use the Right Shifted(Arithmetic) Value of the
// highest MemByte
- SDValue SRA = DAG.getNode(ISD::SRA, MVT::i8, Load,
+ SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load,
DAG.getConstant(7, MVT::i8));
for (iter=MemBytes; iter<ExtdBytes; ++iter) {
PICLoads.push_back(SRA);
@@ -704,33 +712,36 @@
return PICLoads[0];
}
else if (VT == MVT::i16) {
- BP = DAG.getNode(ISD::BUILD_PAIR, VT, PICLoads[0], PICLoads[1]);
+ BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]);
if (MemVT == MVT::i8)
Chain = getChain(PICLoads[0]);
else
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(PICLoads[0]),
- getChain(PICLoads[1]));
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ getChain(PICLoads[0]), getChain(PICLoads[1]));
} else if (VT == MVT::i32) {
SDValue BPs[2];
- BPs[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i16, PICLoads[0], PICLoads[1]);
- BPs[1] = DAG.getNode(ISD::BUILD_PAIR, MVT::i16, PICLoads[2], PICLoads[3]);
- BP = DAG.getNode(ISD::BUILD_PAIR, VT, BPs[0], BPs[1]);
+ BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
+ PICLoads[0], PICLoads[1]);
+ BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16,
+ PICLoads[2], PICLoads[3]);
+ BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]);
if (MemVT == MVT::i8)
Chain = getChain(PICLoads[0]);
else if (MemVT == MVT::i16)
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, getChain(PICLoads[0]),
- getChain(PICLoads[1]));
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ getChain(PICLoads[0]), getChain(PICLoads[1]));
else {
SDValue Chains[2];
- Chains[0] = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[0]), getChain(PICLoads[1]));
- Chains[1] = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
getChain(PICLoads[2]), getChain(PICLoads[3]));
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Chains[0], Chains[1]);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chains[0], Chains[1]);
}
}
Tys = DAG.getVTList(VT, MVT::Other);
- return DAG.getNode(ISD::MERGE_VALUES, Tys, BP, Chain);
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
}
SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
@@ -831,8 +842,8 @@
}
SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
- SelectionDAG &DAG) {
-
+ SelectionDAG &DAG,
+ DebugLoc dl) {
assert (Op.getValueType() == MVT::i8
&& "illegal value type to store on stack.");
@@ -849,7 +860,7 @@
SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8);
// Store the value to ES.
- SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, MVT::Other,
+ SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other,
DAG.getEntryNode(),
Op, ES,
DAG.getConstant (1, MVT::i8), // Banksel.
@@ -857,7 +868,7 @@
// Load the value from ES.
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other);
- SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, Tys, Store,
+ SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store,
ES, DAG.getConstant (1, MVT::i8),
DAG.getConstant (FI, MVT::i8));
@@ -871,6 +882,7 @@
SelectionDAG &DAG) {
CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
unsigned NumOps = TheCall->getNumArgs();
+ DebugLoc dl = TheCall->getDebugLoc();
std::string Name;
SDValue Arg, StoreAt;
MVT ArgVT;
@@ -885,7 +897,7 @@
SDValue PtrLo, PtrHi;
unsigned AddressOffset;
int StoreOffset = 0;
- LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset);
+ LegalizeAddress(FrameAddress, DAG, PtrLo, PtrHi, AddressOffset, dl);
SDValue StoreRet;
std::vector<SDValue> Ops;
@@ -906,7 +918,7 @@
Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
Ops.push_back(InFlag);
- StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, Tys, &Ops[0], Ops.size());
+ StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
Chain = getChain(StoreRet);
InFlag = getOutFlag(StoreRet);
@@ -926,6 +938,7 @@
SDValue InFlag,
SelectionDAG &DAG) {
CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
+ DebugLoc dl = TheCall->getDebugLoc();
// Currently handling primitive types only. They will come in
// i8 parts
unsigned RetVals = TheCall->getNumRetVals();
@@ -941,14 +954,14 @@
// Legalize the address before use
SDValue LdLo, LdHi;
unsigned LdOffset;
- LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset);
+ LegalizeAddress(FrameAddress, DAG, LdLo, LdHi, LdOffset, dl);
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag);
SDValue LoadRet;
for(unsigned i=0, Offset=0;i<RetVals;i++) {
- LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, Tys, Chain, LdLo, LdHi,
+ LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi,
DAG.getConstant(LdOffset + Offset, MVT::i8),
InFlag);
@@ -961,7 +974,7 @@
// To return use MERGE_VALUES
ResultVals.push_back(Chain);
- SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
+ SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size(), dl);
return Res;
}
@@ -977,6 +990,7 @@
CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
SDValue Chain = TheCall->getChain();
SDValue Callee = TheCall->getCallee();
+ DebugLoc dl = TheCall->getDebugLoc();
unsigned i =0;
if (Callee.getValueType() == MVT::i16 &&
Callee.getOpcode() == ISD::BUILD_PAIR) {
@@ -1005,9 +1019,9 @@
SDVTList VTs = DAG.getVTList(&NodeTys[0], NodeTys.size());
SDValue NewCall =
- DAG.getCall(TheCall->getCallingConv(), TheCall->isVarArg(),
- TheCall->isTailCall(), TheCall->isInreg(), VTs,
- &Ops[0], Ops.size());
+ DAG.getCall(TheCall->getCallingConv(), dl,
+ TheCall->isVarArg(), TheCall->isTailCall(),
+ TheCall->isInreg(), VTs, &Ops[0], Ops.size());
return NewCall;
}
@@ -1060,7 +1074,7 @@
OperFlag = getOutFlag(CallArgs);
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDValue PICCall = DAG.getNode(PIC16ISD::CALL, Tys, Chain, Callee,
+ SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee,
OperFlag);
Chain = getChain(PICCall);
OperFlag = getOutFlag(PICCall);
@@ -1107,14 +1121,15 @@
}
SDValue PIC16TargetLowering:: LowerBinOp(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself.
assert (Op.getValueType() == MVT::i8 && "illegal Op to lower");
unsigned MemOp = 1;
if (NeedToConvertToMemOp(Op, MemOp)) {
// Put one value on stack.
- SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG);
+ SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
- return DAG.getNode(Op.getOpcode(), MVT::i8, Op.getOperand(MemOp ^ 1),
+ return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1),
NewVal);
}
else {
@@ -1125,18 +1140,20 @@
SDValue PIC16TargetLowering:: LowerADD(SDValue Op, SelectionDAG &DAG) {
// We should have handled larger operands in type legalizer itself.
assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
+ DebugLoc dl = Op.getDebugLoc();
unsigned MemOp = 1;
if (NeedToConvertToMemOp(Op, MemOp)) {
// Put one value on stack.
- SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG);
+ SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl);
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
if (Op.getOpcode() == ISD::ADDE)
- return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal,
- Op.getOperand(2));
+ return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
+ NewVal, Op.getOperand(2));
else
- return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal);
+ return DAG.getNode(Op.getOpcode(), dl, Tys, Op.getOperand(MemOp ^ 1),
+ NewVal);
}
else if (Op.getOpcode() == ISD::ADD) {
return Op;
@@ -1147,6 +1164,7 @@
}
SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself.
assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
@@ -1156,14 +1174,14 @@
return SDValue();
// Put first operand on stack.
- SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG);
+ SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
if (Op.getOpcode() == ISD::SUBE)
- return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1),
+ return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
Op.getOperand(2));
else
- return DAG.getNode(Op.getOpcode(), Tys, NewVal, Op.getOperand(1));
+ return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
}
// LowerFORMAL_ARGUMENTS - In Lowering FORMAL ARGUMENTS - MERGE_VALUES nodes
@@ -1175,15 +1193,16 @@
SelectionDAG &DAG) {
SmallVector<SDValue, 8> ArgValues;
unsigned NumArgs = Op.getNumOperands() - 3;
+ DebugLoc dl = Op.getDebugLoc();
// Creating UNDEF nodes to meet the requirement of MERGE_VALUES node.
for(unsigned i = 0 ; i<NumArgs ; i++) {
- SDValue TempNode = DAG.getNode(ISD::UNDEF, Op.getNode()->getValueType(i));
+ SDValue TempNode = DAG.getUNDEF(Op.getNode()->getValueType(i));
ArgValues.push_back(TempNode);
}
ArgValues.push_back(Op.getOperand(0));
- return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0],
ArgValues.size()).getValue(Op.getResNo());
}
@@ -1248,7 +1267,7 @@
// Returns appropriate CMP insn and corresponding condition code in PIC16CC
SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
unsigned CC, SDValue &PIC16CC,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG, DebugLoc dl) {
PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
// PIC16 sub is literal - W. So Swap the operands and condition if needed.
@@ -1293,8 +1312,8 @@
// These are signed comparisons.
SDValue Mask = DAG.getConstant(128, MVT::i8);
if (isSignedComparison(CondCode)) {
- LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask);
- RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask);
+ LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask);
+ RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask);
}
SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
@@ -1304,11 +1323,11 @@
// for subwf and literal for sublw) and it is used by this operation only.
if ((LHS.getOpcode() == ISD::Constant || isDirectLoad(LHS))
&& LHS.hasOneUse())
- return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS);
+ return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
// else convert the first operand to mem.
- LHS = ConvertToMemOperand (LHS, DAG);
- return DAG.getNode(PIC16ISD::SUBCC, VTs, LHS, RHS);
+ LHS = ConvertToMemOperand (LHS, DAG, dl);
+ return DAG.getNode(PIC16ISD::SUBCC, dl, VTs, LHS, RHS);
}
@@ -1319,6 +1338,7 @@
SDValue TrueVal = Op.getOperand(2);
SDValue FalseVal = Op.getOperand(3);
unsigned ORIGCC = ~0;
+ DebugLoc dl = Op.getDebugLoc();
// If this is a select_cc of a "setcc", and if the setcc got lowered into
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
@@ -1331,9 +1351,9 @@
if (ORIGCC == ~0U) ORIGCC = IntCCToPIC16CC (CC);
SDValue PIC16CC;
- SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG);
+ SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
- return DAG.getNode (PIC16ISD::SELECT_ICC, TrueVal.getValueType(), TrueVal,
+ return DAG.getNode (PIC16ISD::SELECT_ICC, dl, TrueVal.getValueType(), TrueVal,
FalseVal, PIC16CC, Cmp.getValue(1));
}
@@ -1342,6 +1362,7 @@
MachineBasicBlock *BB) {
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
unsigned CC = (PIC16CC::CondCodes)MI->getOperand(3).getImm();
+ DebugLoc dl = MI->getDebugLoc();
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
// control-flow pattern. The incoming instruction knows the destination vreg
@@ -1360,7 +1381,7 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
+ BuildMI(BB, dl, TII.get(PIC16::pic16brcond)).addMBB(sinkMBB).addImm(CC);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
@@ -1383,7 +1404,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
@@ -1399,6 +1420,7 @@
SDValue RHS = Op.getOperand(3); // RHS of the condition.
SDValue Dest = Op.getOperand(4); // BB to jump to
unsigned ORIGCC = ~0;
+ DebugLoc dl = Op.getDebugLoc();
// If this is a br_cc of a "setcc", and if the setcc got lowered into
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
@@ -1407,9 +1429,9 @@
// Get the Compare insn and condition code.
SDValue PIC16CC;
- SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG);
+ SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl);
- return DAG.getNode(PIC16ISD::BRCOND, MVT::Other, Chain, Dest, PIC16CC,
+ return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC,
Cmp.getValue(1));
}
Modified: llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16ISelLowering.h Sat Feb 14 07:20:23 2009
@@ -88,7 +88,7 @@
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC,
- SelectionDAG &DAG);
+ SelectionDAG &DAG, DebugLoc dl);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
@@ -138,7 +138,7 @@
// addresses need Banksel and Indirect addresses need to be loaded to
// FSR first. Handle address specific cases here.
void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain,
- SDValue &NewPtr, unsigned &Offset);
+ SDValue &NewPtr, unsigned &Offset, DebugLoc dl);
// FrameIndex should be broken down into ExternalSymbol and FrameOffset.
void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES,
@@ -146,7 +146,7 @@
// We can not have both operands of a binary operation in W.
// This function is used to put one operand on stack and generate a load.
- SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG);
+ SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
// This function checks if we need to put an operand of an operation on
// stack and generate a load or not.
Modified: llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PIC16/PIC16InstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -69,6 +69,8 @@
MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
const Function *Func = MBB.getParent()->getFunction();
const std::string FuncName = Func->getName();
@@ -80,7 +82,7 @@
if (RC == PIC16::GPRRegisterClass) {
//MachineFunction &MF = *MBB.getParent();
//MachineRegisterInfo &RI = MF.getRegInfo();
- BuildMI(MBB, I, get(PIC16::movwf))
+ BuildMI(MBB, I, DL, get(PIC16::movwf))
.addReg(SrcReg, false, false, isKill)
.addImm(FI)
.addExternalSymbol(tmpName)
@@ -96,6 +98,8 @@
MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
const Function *Func = MBB.getParent()->getFunction();
const std::string FuncName = Func->getName();
@@ -107,7 +111,7 @@
if (RC == PIC16::GPRRegisterClass) {
//MachineFunction &MF = *MBB.getParent();
//MachineRegisterInfo &RI = MF.getRegInfo();
- BuildMI(MBB, I, get(PIC16::movf), DestReg)
+ BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
.addImm(FI)
.addExternalSymbol(tmpName)
.addImm(1); // Emit banksel for it.
@@ -123,13 +127,16 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (DestRC == PIC16::FSR16RegisterClass) {
- BuildMI(MBB, I, get(PIC16::copy_fsr), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg);
return true;
}
if (DestRC == PIC16::GPRRegisterClass) {
- BuildMI(MBB, I, get(PIC16::copy_w), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg);
return true;
}
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCBranchSelector.cpp Sat Feb 14 07:20:23 2009
@@ -145,13 +145,14 @@
unsigned CRReg = I->getOperand(1).getReg();
MachineInstr *OldBranch = I;
+ DebugLoc dl = OldBranch->getDebugLoc();
// Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
- BuildMI(MBB, I, TII->get(PPC::BCC))
+ BuildMI(MBB, I, dl, TII->get(PPC::BCC))
.addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
// Uncond branch to the real destination.
- I = BuildMI(MBB, I, TII->get(PPC::B)).addMBB(Dest);
+ I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
// Remove the old branch from the function.
OldBranch->eraseFromParent();
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -98,7 +98,7 @@
/// SelectCC - Select a comparison of the specified values with the
/// specified condition code, returning the CR# of the expression.
- SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
+ SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
/// SelectAddrImm - Returns true if the address N can be represented by
/// a base register plus a signed 16-bit displacement [r+imm].
@@ -243,15 +243,16 @@
const TargetInstrInfo &TII = *TM.getInstrInfo();
MachineBasicBlock &EntryBB = *Fn.begin();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Emit the following code into the entry block:
// InVRSAVE = MFVRSAVE
// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
// MTVRSAVE UpdatedVRSAVE
MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
- BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
- BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
+ BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
+ BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
UpdatedVRSAVE).addReg(InVRSAVE);
- BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
+ BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
// Find all return blocks, outputting a restore in each epilog.
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
@@ -265,7 +266,7 @@
IP = I2;
// Emit: MTVRSAVE InVRSave
- BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
+ BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
}
}
}
@@ -280,15 +281,16 @@
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
if (PPCLowering.getPointerTy() == MVT::i32) {
GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
} else {
GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
}
}
return CurDAG->getRegister(GlobalBaseReg,
@@ -418,6 +420,7 @@
SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
+ DebugLoc dl = N->getDebugLoc();
APInt LKZ, LKO, RKZ, RKO;
CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
@@ -479,7 +482,7 @@
SH &= 31;
SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
return 0;
@@ -488,7 +491,7 @@
/// SelectCC - Select a comparison of the specified values with the specified
/// condition code, returning the CR# of the expression.
SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
- ISD::CondCode CC) {
+ ISD::CondCode CC, DebugLoc dl) {
// Always select the LHS.
unsigned Opc;
@@ -498,11 +501,11 @@
if (isInt32Immediate(RHS, Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16((int)Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@@ -514,21 +517,21 @@
// xoris r0,r3,0x1234
// cmplwi cr0,r0,0x5678
// beq cr0,L6
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS,
getI32Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor,
getI32Imm(Imm & 0xFFFF)), 0);
}
Opc = PPC::CMPLW;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLW;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
getI32Imm((int)SImm & 0xFFFF)),
0);
Opc = PPC::CMPW;
@@ -539,11 +542,11 @@
if (isInt64Immediate(RHS.getNode(), Imm)) {
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
if (isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// If this is a 16-bit signed immediate, fold it.
if (isInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI32Imm(Imm & 0xFFFF)), 0);
// For non-equality comparisons, the default code would materialize the
@@ -556,22 +559,22 @@
// cmpldi cr0,r0,0x5678
// beq cr0,L6
if (isUInt32(Imm)) {
- SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
+ SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS,
getI64Imm(Imm >> 16)), 0);
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor,
getI64Imm(Imm & 0xFFFF)), 0);
}
}
Opc = PPC::CMPLD;
} else if (ISD::isUnsignedIntSetCC(CC)) {
if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
getI64Imm(Imm & 0xFFFF)), 0);
Opc = PPC::CMPLD;
} else {
short SImm;
if (isIntS16Immediate(RHS, SImm))
- return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
+ return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
getI64Imm(SImm & 0xFFFF)),
0);
Opc = PPC::CMPD;
@@ -582,7 +585,7 @@
assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
Opc = PPC::FCMPUD;
}
- return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
+ return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0);
}
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
@@ -652,6 +655,7 @@
SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
SDNode *N = Op.getNode();
+ DebugLoc dl = N->getDebugLoc();
unsigned Imm;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
if (isInt32Immediate(N->getOperand(1), Imm)) {
@@ -663,13 +667,13 @@
switch (CC) {
default: break;
case ISD::SETEQ: {
- Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
+ Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETNE: {
SDValue AD =
- SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U)), 0);
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
AD.getValue(1));
@@ -680,8 +684,8 @@
}
case ISD::SETGT: {
SDValue T =
- SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
- T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
+ SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0);
+ T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
@@ -691,30 +695,32 @@
switch (CC) {
default: break;
case ISD::SETEQ:
- Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(1)), 0);
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
- SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32,
- getI32Imm(0)), 0),
- Op.getValue(1));
+ SDValue(CurDAG->getTargetNode(PPC::LI, dl,
+ MVT::i32,
+ getI32Imm(0)), 0),
+ Op.getValue(1));
case ISD::SETNE: {
- Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
- SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
+ SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
Op, getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
Op, SDValue(AD, 1));
}
case ISD::SETLT: {
- SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
+ SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op,
getI32Imm(1)), 0);
- SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
+ SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD,
Op), 0);
SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
}
case ISD::SETGT: {
SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
- Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
+ Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
+ 0);
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
getI32Imm(1));
}
@@ -725,21 +731,21 @@
bool Inv;
int OtherCondIdx;
unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
- SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
+ SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
SDValue IntCR;
// Force the ccreg into CR7.
SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
SDValue InFlag(0, 0); // Null incoming flag value.
- CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
+ CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
InFlag).getValue(1);
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
CCReg), 0);
else
- IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
+ IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31), getI32Imm(31) };
@@ -748,7 +754,7 @@
// Get the specified bit.
SDValue Tmp =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
if (Inv) {
assert(OtherCondIdx == -1 && "Can't have split plus negation");
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
@@ -760,7 +766,7 @@
// Get the other bit of the comparison.
Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
SDValue OtherCond =
- SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
+ SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
}
@@ -770,6 +776,7 @@
// target-specific node if it hasn't already been changed.
SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
+ DebugLoc dl = Op.getDebugLoc();
if (N->isMachineOpcode())
return NULL; // Already selected.
@@ -812,17 +819,17 @@
// Simple value.
if (isInt16(Imm)) {
// Just the Lo bits.
- Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo));
+ Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
} else if (Lo) {
// Handle the Hi bits.
unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
- Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi));
// And Lo bits.
- Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Lo));
} else {
// Just the Hi bits.
- Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
+ Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
}
// If no shift, we're done.
@@ -830,18 +837,18 @@
// Shift for next step if the upper 32-bits were not zero.
if (Imm) {
- Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
+ Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64,
SDValue(Result, 0),
getI32Imm(Shift), getI32Imm(63 - Shift));
}
// Add in the last bits as required.
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Hi));
}
if ((Lo = Remainder & 0xFFFF)) {
- Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
+ Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
SDValue(Result, 0), getI32Imm(Lo));
}
@@ -862,7 +869,7 @@
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
getSmallIPtrImm(0));
- return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
+ return CurDAG->getTargetNode(Opc, dl, Op.getValueType(), TFI,
getSmallIPtrImm(0));
}
@@ -870,10 +877,10 @@
SDValue InFlag = N->getOperand(1);
// Use MFOCRF if supported.
if (PPCSubTarget.isGigaProcessor())
- return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
+ return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32,
N->getOperand(0), InFlag);
else
- return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
+ return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag);
}
case ISD::SDIV: {
@@ -887,16 +894,16 @@
SDValue N0 = N->getOperand(0);
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
+ CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(Imm)));
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1));
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
SDNode *Op =
- CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
+ CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
N0, getI32Imm(Log2_32(-Imm)));
SDValue PT =
- SDValue(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
+ SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32,
SDValue(Op, 0), SDValue(Op, 1)),
0);
return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
@@ -951,7 +958,7 @@
SDValue Base = LD->getBasePtr();
SDValue Ops[] = { Offset, Base, Chain };
// FIXME: PPC64
- return CurDAG->getTargetNode(Opcode, LD->getValueType(0),
+ return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0),
PPCLowering.getPointerTy(),
MVT::Other, Ops, 3);
} else {
@@ -995,7 +1002,7 @@
SDValue Ops[] = { N->getOperand(0).getOperand(0),
N->getOperand(0).getOperand(1),
getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
- return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
+ return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
}
}
@@ -1045,14 +1052,14 @@
// FIXME: Implement this optzn for PPC64.
N->getValueType(0) == MVT::i32) {
SDNode *Tmp =
- CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
+ CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
N->getOperand(0), getI32Imm(~0U));
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
SDValue(Tmp, 0), N->getOperand(0),
SDValue(Tmp, 1));
}
- SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
+ SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
unsigned BROpc = getPredicateForSetCC(CC);
unsigned SelectCCOp;
@@ -1086,7 +1093,7 @@
}
case ISD::BR_CC: {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
- SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
+ SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
@@ -1096,7 +1103,7 @@
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
- Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Target,
+ Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target,
Chain), 0);
return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
}
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -815,6 +815,8 @@
bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
SDValue &Base,
SelectionDAG &DAG) const {
+ // FIXME dl should come from parent load or store, not from address
+ DebugLoc dl = N.getDebugLoc();
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
return false;
@@ -882,7 +884,7 @@
Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
- Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
+ Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
return true;
}
}
@@ -927,6 +929,8 @@
bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
SDValue &Base,
SelectionDAG &DAG) const {
+ // FIXME dl should come from the parent load or store, not the address
+ DebugLoc dl = N.getDebugLoc();
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
return false;
@@ -990,10 +994,9 @@
// Otherwise, break this down into an LIS + disp.
Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
-
Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
- Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
+ Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
return true;
}
}
@@ -1072,11 +1075,13 @@
Constant *C = CP->getConstVal();
SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
SDValue Zero = DAG.getConstant(0, PtrVT);
+ // FIXME there isn't really any debug info here
+ DebugLoc dl = Op.getDebugLoc();
const TargetMachine &TM = DAG.getTarget();
- SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
- SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
+ SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
+ SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
@@ -1084,16 +1089,17 @@
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
// Generate non-pic code that has direct accesses to the constant pool.
// The address of the global is just (hi(&g)+lo(&g)).
- return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
+ return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
}
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
- Hi = DAG.getNode(ISD::ADD, PtrVT,
- DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
+ Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
+ DAG.getNode(PPCISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
- Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
+ Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
return Lo;
}
@@ -1102,11 +1108,13 @@
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDValue Zero = DAG.getConstant(0, PtrVT);
+ // FIXME there isn't really any debug loc here
+ DebugLoc dl = Op.getDebugLoc();
const TargetMachine &TM = DAG.getTarget();
- SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
- SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
+ SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
+ SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
@@ -1114,16 +1122,17 @@
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
// Generate non-pic code that has direct accesses to the constant pool.
// The address of the global is just (hi(&g)+lo(&g)).
- return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
+ return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
}
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
- Hi = DAG.getNode(ISD::ADD, PtrVT,
- DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
+ Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
+ DAG.getNode(PPCISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
- Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
+ Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
return Lo;
}
@@ -1140,11 +1149,13 @@
GlobalValue *GV = GSDN->getGlobal();
SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
SDValue Zero = DAG.getConstant(0, PtrVT);
+ // FIXME there isn't really any debug info here
+ DebugLoc dl = GSDN->getDebugLoc();
const TargetMachine &TM = DAG.getTarget();
- SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
- SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
+ SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
+ SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
// If this is a non-darwin platform, we don't support non-static relo models
// yet.
@@ -1152,27 +1163,29 @@
!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
// Generate non-pic code that has direct accesses to globals.
// The address of the global is just (hi(&g)+lo(&g)).
- return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
+ return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
}
if (TM.getRelocationModel() == Reloc::PIC_) {
// With PIC, the first instruction is actually "GR+hi(&G)".
- Hi = DAG.getNode(ISD::ADD, PtrVT,
- DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
+ Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
+ DAG.getNode(PPCISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(), PtrVT), Hi);
}
- Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
+ Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
return Lo;
// If the global is weak or external, we have to go through the lazy
// resolution stub.
- return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
+ return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
}
SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
+ DebugLoc dl = Op.getDebugLoc();
// If we're comparing for equality to zero, expose the fact that this is
// implented as a ctlz/srl pair on ppc, so that the dag combiner can
@@ -1183,13 +1196,13 @@
SDValue Zext = Op.getOperand(0);
if (VT.bitsLT(MVT::i32)) {
VT = MVT::i32;
- Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
+ Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
}
unsigned Log2b = Log2_32(VT.getSizeInBits());
- SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
- SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz,
+ SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
+ SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
DAG.getConstant(Log2b, MVT::i32));
- return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
}
// Leave comparisons against 0 and -1 alone for now, since they're usually
// optimized. FIXME: revisit this when we can custom lower all setcc
@@ -1206,9 +1219,9 @@
MVT LHSVT = Op.getOperand(0).getValueType();
if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
MVT VT = Op.getValueType();
- SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
+ SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
Op.getOperand(1));
- return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
+ return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
}
return SDValue();
}
@@ -1229,7 +1242,7 @@
SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
- DebugLoc dl = Op.getNode()->getDebugLoc();
+ DebugLoc dl = Op.getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = (PtrVT == MVT::i64);
@@ -1260,7 +1273,7 @@
SDValue Ops[] =
{ CallResult.first, CallResult.second };
- return DAG.getMergeValues(Ops, 2);
+ return DAG.getMergeValues(Ops, 2, dl);
}
SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
@@ -1269,6 +1282,7 @@
unsigned VarArgsNumGPR,
unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget) {
+ DebugLoc dl = Op.getDebugLoc();
if (Subtarget.isMachoABI()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
@@ -1276,7 +1290,7 @@
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
+ return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
}
// For ELF 32 ABI we follow the layout of the va_list struct.
@@ -1325,26 +1339,26 @@
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// Store first byte : number of int regs
- SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
+ SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR,
Op.getOperand(1), SV, 0);
uint64_t nextOffset = FPROffset;
- SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
+ SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
ConstFPROffset);
// Store second byte : number of float regs
SDValue secondStore =
- DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
+ DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset);
nextOffset += StackOffset;
- nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
+ nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
// Store second word : arguments given on stack
SDValue thirdStore =
- DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
+ DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
nextOffset += FrameOffset;
- nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
+ nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
// Store third word : arguments given in registers
- return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
+ return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
}
@@ -1398,6 +1412,7 @@
SmallVector<SDValue, 8> ArgValues;
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
+ DebugLoc dl = Op.getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
@@ -1550,8 +1565,8 @@
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
+ SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
MemOps.push_back(Store);
++GPR_idx;
@@ -1570,8 +1585,8 @@
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
++GPR_idx;
if (isMachoABI) ArgOffset += PtrByteSize;
@@ -1593,7 +1608,7 @@
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
- ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
++GPR_idx;
} else {
needsLoad = true;
@@ -1611,19 +1626,19 @@
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
- ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
+ ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
if (ObjectVT == MVT::i32) {
// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
// value to MVT::i64 and then truncate to the correct register size.
if (Flags.isSExt())
- ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
+ ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
else if (Flags.isZExt())
- ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
+ ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
- ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
+ ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
}
++GPR_idx;
@@ -1651,7 +1666,7 @@
else
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
- ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
+ ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
++FPR_idx;
} else {
needsLoad = true;
@@ -1672,7 +1687,7 @@
if (VR_idx != Num_VR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
RegInfo.addLiveIn(VR[VR_idx], VReg);
- ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
+ ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
if (isVarArg) {
while ((ArgOffset % 16) != 0) {
ArgOffset += PtrByteSize;
@@ -1706,7 +1721,7 @@
CurArgOffset + (ArgSize - ObjSize),
isImmutable);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
- ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
+ ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
@@ -1762,11 +1777,11 @@
if (isELF32_ABI) {
for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
- SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
+ SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
- FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
+ FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
}
@@ -1781,12 +1796,12 @@
VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
- SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
- FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
+ FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
// In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
@@ -1794,12 +1809,12 @@
if (isELF32_ABI) {
for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
- SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
+ SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
- FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
+ FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
@@ -1807,24 +1822,25 @@
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
- SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
- FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
+ FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
}
}
if (!MemOps.empty())
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
+ Root = DAG.getNode(ISD::TokenFactor, dl,
+ MVT::Other, &MemOps[0], MemOps.size());
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size());
}
@@ -1984,13 +2000,14 @@
StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
SDValue Chain,
const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
- SmallVector<SDValue, 8> &MemOpChains) {
+ SmallVector<SDValue, 8> &MemOpChains,
+ DebugLoc dl) {
for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
SDValue Arg = TailCallArgs[i].Arg;
SDValue FIN = TailCallArgs[i].FrameIdxOp;
int FI = TailCallArgs[i].FrameIdx;
// Store relative to framepointer.
- MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN,
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
PseudoSourceValue::getFixedStack(FI),
0));
}
@@ -2005,7 +2022,8 @@
SDValue OldFP,
int SPDiff,
bool isPPC64,
- bool isMachoABI) {
+ bool isMachoABI,
+ DebugLoc dl) {
if (SPDiff) {
// Calculate the new stack slot for the return address.
int SlotSize = isPPC64 ? 8 : 4;
@@ -2019,10 +2037,10 @@
MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
- Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
+ Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewRetAddr), 0);
SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
- Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx,
+ Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
PseudoSourceValue::getFixedStack(NewFPIdx), 0);
}
return Chain;
@@ -2050,18 +2068,19 @@
/// stack slot. Returns the chain as result and the loaded frame pointers in
/// LROpOut/FPOpout. Used when tail calling.
SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
- int SPDiff,
- SDValue Chain,
- SDValue &LROpOut,
- SDValue &FPOpOut) {
+ int SPDiff,
+ SDValue Chain,
+ SDValue &LROpOut,
+ SDValue &FPOpOut,
+ DebugLoc dl) {
if (SPDiff) {
// Load the LR and FP stack slot for later adjusting.
MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
LROpOut = getReturnAddrFrameIndex(DAG);
- LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
+ LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
Chain = SDValue(LROpOut.getNode(), 1);
FPOpOut = getFramePointerFrameIndex(DAG);
- FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
+ FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
Chain = SDValue(FPOpOut.getNode(), 1);
}
return Chain;
@@ -2076,10 +2095,10 @@
static SDValue
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
- unsigned Size) {
+ unsigned Size, DebugLoc dl) {
SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
- return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false,
- NULL, 0, NULL, 0);
+ return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
+ false, NULL, 0, NULL, 0);
}
/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
@@ -2089,7 +2108,8 @@
SDValue Arg, SDValue PtrOff, int SPDiff,
unsigned ArgOffset, bool isPPC64, bool isTailCall,
bool isVector, SmallVector<SDValue, 8> &MemOpChains,
- SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
+ SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
+ DebugLoc dl) {
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
if (!isTailCall) {
if (isVector) {
@@ -2098,10 +2118,10 @@
StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
else
StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
- PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
+ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
DAG.getConstant(ArgOffset, PtrVT));
}
- MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
// Calculate and remember argument location.
} else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
TailCallArguments);
@@ -2118,6 +2138,7 @@
&& CC == CallingConv::Fast && PerformTailCallOpt;
SDValue Callee = TheCall->getCallee();
unsigned NumOps = TheCall->getNumArgs();
+ DebugLoc dl = TheCall->getDebugLoc();
bool isMachoABI = Subtarget.isMachoABI();
bool isELF32_ABI = Subtarget.isELF32_ABI();
@@ -2161,7 +2182,7 @@
// Load the return address and frame pointer so it can be move somewhere else
// later.
SDValue LROp, FPOp;
- Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp);
+ Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
// Set up a copy of the stack pointer for use loading and storing any
// arguments that may not fit in the registers available for argument
@@ -2221,13 +2242,13 @@
else
PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
+ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
// On PPC64, promote integers to 64-bit values.
if (isPPC64 && Arg.getValueType() == MVT::i32) {
// FIXME: Should this use ANY_EXTEND if neither sext nor zext?
unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
+ Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
}
// FIXME Elf untested, what are alignment rules?
@@ -2240,7 +2261,7 @@
// Everything else is passed left-justified.
MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
- SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
NULL, 0, VT);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
@@ -2248,10 +2269,10 @@
ArgOffset += PtrByteSize;
} else {
SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
- SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
+ SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
CallSeqStart.getNode()->getOperand(0),
- Flags, DAG, Size);
+ Flags, DAG, Size, dl);
// This must go outside the CALLSEQ_START..END.
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
CallSeqStart.getNode()->getOperand(1));
@@ -2267,7 +2288,7 @@
// registers. (This is not what the doc says.)
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
CallSeqStart.getNode()->getOperand(0),
- Flags, DAG, Size);
+ Flags, DAG, Size, dl);
// This must go outside the CALLSEQ_START..END.
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
CallSeqStart.getNode()->getOperand(1));
@@ -2276,9 +2297,9 @@
// And copy the pieces of it that fit into registers.
for (unsigned j=0; j<Size; j+=PtrByteSize) {
SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
- SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
+ SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
if (GPR_idx != NumGPRs) {
- SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
+ SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
if (isMachoABI)
@@ -2302,7 +2323,7 @@
} else {
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, false, MemOpChains,
- TailCallArguments);
+ TailCallArguments, dl);
inMem = true;
}
if (inMem || isMachoABI) {
@@ -2319,20 +2340,20 @@
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
if (isVarArg) {
- SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
+ SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
// Float varargs are always shadowed in available integer registers
if (GPR_idx != NumGPRs) {
- SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
+ SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
Load));
}
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
- PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
- SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
+ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
+ SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
Load));
@@ -2352,7 +2373,7 @@
} else {
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, false, MemOpChains,
- TailCallArguments);
+ TailCallArguments, dl);
inMem = true;
}
if (inMem || isMachoABI) {
@@ -2382,12 +2403,12 @@
}
// We could elide this store in the case where the object fits
// entirely in R registers. Maybe later.
- PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
+ PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
DAG.getConstant(ArgOffset, PtrVT));
- SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
+ SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
if (VR_idx != NumVRs) {
- SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
}
@@ -2395,9 +2416,9 @@
for (unsigned i=0; i<16; i+=PtrByteSize) {
if (GPR_idx == NumGPRs)
break;
- SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
+ SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
DAG.getConstant(i, PtrVT));
- SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
+ SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
@@ -2413,7 +2434,7 @@
// We are emitting Altivec params in order.
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, true, MemOpChains,
- TailCallArguments);
+ TailCallArguments, dl);
ArgOffset += 16;
}
break;
@@ -2439,7 +2460,7 @@
// We are emitting Altivec params in order.
LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
isPPC64, isTailCall, true, MemOpChains,
- TailCallArguments);
+ TailCallArguments, dl);
ArgOffset += 16;
}
}
@@ -2447,22 +2468,22 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
- InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
// With the ELF 32 ABI, set CR6 to true if this is a vararg call.
if (isVarArg && isELF32_ABI) {
- SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
- Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
+ SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
+ Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
InFlag = Chain.getValue(1);
}
@@ -2473,27 +2494,20 @@
// Do not flag preceeding copytoreg stuff together with the following stuff.
InFlag = SDValue();
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
- MemOpChains2);
+ MemOpChains2, dl);
if (!MemOpChains2.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains2[0], MemOpChains2.size());
// Store the return address to the appropriate stack slot.
Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
- isPPC64, isMachoABI);
+ isPPC64, isMachoABI, dl);
}
// Emit callseq_end just before tailcall node.
if (isTailCall) {
- SmallVector<SDValue, 8> CallSeqOps;
- SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- CallSeqOps.push_back(Chain);
- CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true));
- CallSeqOps.push_back(DAG.getIntPtrConstant(0, true));
- if (InFlag.getNode())
- CallSeqOps.push_back(InFlag);
- Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
- CallSeqOps.size());
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), InFlag);
InFlag = Chain.getValue(1);
}
@@ -2518,14 +2532,14 @@
// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
// to do the call, we can't use PPCISD::CALL.
SDValue MTCTROps[] = {Chain, Callee, InFlag};
- Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps,
+ Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2 + (InFlag.getNode() != 0));
InFlag = Chain.getValue(1);
// Copy the callee address into R12/X12 on darwin.
if (isMachoABI) {
unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
- Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, Reg, Callee, InFlag);
InFlag = Chain.getValue(1);
}
@@ -2568,12 +2582,12 @@
if (isTailCall) {
assert(InFlag.getNode() &&
"Flag must be set. Depend on flag being set in LowerRET");
- Chain = DAG.getNode(PPCISD::TAILCALL,
+ Chain = DAG.getNode(PPCISD::TAILCALL, dl,
TheCall->getVTList(), &Ops[0], Ops.size());
return SDValue(Chain.getNode(), Op.getResNo());
}
- Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
+ Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
@@ -2593,7 +2607,8 @@
CCValAssign &VA = RVLocs[i];
MVT VT = VA.getValVT();
assert(VA.isRegLoc() && "Can only return in registers!");
- Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
+ Chain = DAG.getCopyFromReg(Chain, dl,
+ VA.getLocReg(), VT, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
InFlag = Chain.getValue(2);
}
@@ -2604,7 +2619,7 @@
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
- SDValue Res = DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
+ SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
&ResultVals[0], ResultVals.size());
return Res.getValue(Op.getResNo());
}
@@ -2614,6 +2629,7 @@
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
+ DebugLoc dl = Op.getDebugLoc();
CCState CCInfo(CC, isVarArg, TM, RVLocs);
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
@@ -2651,7 +2667,7 @@
for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
Operands.push_back(Chain.getOperand(i));
}
- return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0],
+ return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0],
Operands.size());
}
@@ -2661,19 +2677,21 @@
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ Op.getOperand(i*2+1), Flag);
Flag = Chain.getValue(1);
}
if (Flag.getNode())
- return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
+ return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
else
- return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
+ return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
}
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget) {
// When we pop the dynamic allocation we need to restore the SP link.
+ DebugLoc dl = Op.getDebugLoc();
// Get the corect type for pointers.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -2688,13 +2706,13 @@
SDValue SaveSP = Op.getOperand(1);
// Load the old link SP.
- SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
+ SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
// Restore the stack pointer.
- Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
+ Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
// Store the old link SP.
- return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
+ return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
}
@@ -2754,18 +2772,19 @@
// Get the inputs.
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
-
+ DebugLoc dl = Op.getDebugLoc();
+
// Get the corect type for pointers.
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Negate the size.
- SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT,
+ SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
DAG.getConstant(0, PtrVT), Size);
// Construct a node for the frame pointer save index.
SDValue FPSIdx = getFramePointerFrameIndex(DAG);
// Build a DYNALLOC node.
SDValue Ops[3] = { Chain, NegSize, FPSIdx };
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
- return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
+ return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
}
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
@@ -2785,6 +2804,7 @@
MVT CmpVT = Op.getOperand(0).getValueType();
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
+ DebugLoc dl = Op.getDebugLoc();
// If the RHS of the comparison is a 0.0, we don't need to do the
// subtraction at all.
@@ -2797,17 +2817,17 @@
case ISD::SETOGE:
case ISD::SETGE:
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
- LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
- return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
+ LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
+ return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETOLE:
case ISD::SETLE:
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
- LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
- return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
+ LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
+ return DAG.getNode(PPCISD::FSEL, dl, ResVT,
+ DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
}
SDValue Cmp;
@@ -2815,47 +2835,48 @@
default: break; // SETUO etc aren't handled by fsel.
case ISD::SETULT:
case ISD::SETLT:
- Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
+ Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
- return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
case ISD::SETOGE:
case ISD::SETGE:
- Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
+ Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
- return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
- Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
+ Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
- return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
case ISD::SETOLE:
case ISD::SETLE:
- Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
+ Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
- Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
- return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
+ Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
+ return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
}
return SDValue();
}
// FIXME: Split this code up when LegalizeDAGTypes lands.
-SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
+SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
+ DebugLoc dl) {
assert(Op.getOperand(0).getValueType().isFloatingPoint());
SDValue Src = Op.getOperand(0);
if (Src.getValueType() == MVT::f32)
- Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
+ Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
SDValue Tmp;
switch (Op.getValueType().getSimpleVT()) {
default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
case MVT::i32:
- Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
+ Tmp = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Src);
break;
case MVT::i64:
- Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
+ Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
break;
}
@@ -2863,26 +2884,29 @@
SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
// Emit a store to the stack slot.
- SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
+ SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
// Result is a load from the stack slot. If loading 4 bytes, make sure to
// add in a bias.
if (Op.getValueType() == MVT::i32)
- FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
+ FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
DAG.getConstant(4, FIPtr.getValueType()));
- return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
+ return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
}
SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// Don't handle ppc_fp128 here; let it be lowered to a libcall.
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
return SDValue();
if (Op.getOperand(0).getValueType() == MVT::i64) {
- SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
- SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
+ SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
+ MVT::f64, Op.getOperand(0));
+ SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
if (Op.getValueType() == MVT::f32)
- FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
+ FP = DAG.getNode(ISD::FP_ROUND, dl,
+ MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
@@ -2897,26 +2921,27 @@
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
- SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
+ SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
Op.getOperand(0));
// STD the extended value into the stack slot.
MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
MachineMemOperand::MOStore, 0, 8, 8);
- SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
+ SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
DAG.getEntryNode(), Ext64, FIdx,
DAG.getMemOperand(MO));
// Load the value as a double.
- SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
+ SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
// FCFID it and return it.
- SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
+ SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
if (Op.getValueType() == MVT::f32)
- FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
+ FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
return FP;
}
SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
/*
The rounding mode is in bits 30:31 of FPSR, and has the following
settings:
@@ -2945,41 +2970,42 @@
// Save FP Control Word to register
NodeTys.push_back(MVT::f64); // return register
NodeTys.push_back(MVT::Flag); // unused in this context
- SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
+ SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
// Save FP register to stack slot
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
- SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain,
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
StackSlot, NULL, 0);
// Load FP Control Word from low 32 bits of stack slot.
SDValue Four = DAG.getConstant(4, PtrVT);
- SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
- SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
+ SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
+ SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
// Transform as necessary
SDValue CWD1 =
- DAG.getNode(ISD::AND, MVT::i32,
+ DAG.getNode(ISD::AND, dl, MVT::i32,
CWD, DAG.getConstant(3, MVT::i32));
SDValue CWD2 =
- DAG.getNode(ISD::SRL, MVT::i32,
- DAG.getNode(ISD::AND, MVT::i32,
- DAG.getNode(ISD::XOR, MVT::i32,
+ DAG.getNode(ISD::SRL, dl, MVT::i32,
+ DAG.getNode(ISD::AND, dl, MVT::i32,
+ DAG.getNode(ISD::XOR, dl, MVT::i32,
CWD, DAG.getConstant(3, MVT::i32)),
DAG.getConstant(3, MVT::i32)),
DAG.getConstant(1, MVT::i32));
SDValue RetVal =
- DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
+ DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
return DAG.getNode((VT.getSizeInBits() < 16 ?
- ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
+ ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
}
SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
+ DebugLoc dl = Op.getDebugLoc();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
"Unexpected SHL!");
@@ -2991,22 +3017,23 @@
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
- SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
+ SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
- SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
- SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
- SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
- SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
+ SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
+ SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
+ SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
+ SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
- SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
- SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
- SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
+ SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
+ SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
+ SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
SDValue OutOps[] = { OutLo, OutHi };
- return DAG.getMergeValues(OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2, dl);
}
SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
VT == Op.getOperand(1).getValueType() &&
@@ -3019,21 +3046,22 @@
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
- SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
+ SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
- SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
- SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
- SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
- SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
+ SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
+ SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
+ SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
+ SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
- SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
- SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
- SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
+ SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
+ SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
+ SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
SDValue OutOps[] = { OutLo, OutHi };
- return DAG.getMergeValues(OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2, dl);
}
SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits();
assert(Op.getNumOperands() == 3 &&
@@ -3046,19 +3074,19 @@
SDValue Amt = Op.getOperand(2);
MVT AmtVT = Amt.getValueType();
- SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
+ SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
DAG.getConstant(BitWidth, AmtVT), Amt);
- SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
- SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
- SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
- SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
+ SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
+ SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
+ SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
+ SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
DAG.getConstant(-BitWidth, AmtVT));
- SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
- SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
- SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
+ SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
+ SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
+ SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
Tmp4, Tmp6, ISD::SETLE);
SDValue OutOps[] = { OutLo, OutHi };
- return DAG.getMergeValues(OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2, dl);
}
//===----------------------------------------------------------------------===//
@@ -3162,7 +3190,7 @@
/// BuildSplatI - Build a canonical splati of Val with an element size of
/// SplatSize. Cast the result to VT.
static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG, DebugLoc dl) {
assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
static const MVT VTys[] = { // canonical VT to use for each size.
@@ -3181,28 +3209,28 @@
SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
SmallVector<SDValue, 8> Ops;
Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
- SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
+ SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
&Ops[0], Ops.size());
- return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
}
/// BuildIntrinsicOp - Return a binary operator intrinsic node with the
/// specified intrinsic ID.
static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
- SelectionDAG &DAG,
- MVT DestVT = MVT::Other) {
+ SelectionDAG &DAG, DebugLoc dl,
+ MVT DestVT = MVT::Other) {
if (DestVT == MVT::Other) DestVT = LHS.getValueType();
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
DAG.getConstant(IID, MVT::i32), LHS, RHS);
}
/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
/// specified intrinsic ID.
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
- SDValue Op2, SelectionDAG &DAG,
- MVT DestVT = MVT::Other) {
+ SDValue Op2, SelectionDAG &DAG,
+ DebugLoc dl, MVT DestVT = MVT::Other) {
if (DestVT == MVT::Other) DestVT = Op0.getValueType();
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
}
@@ -3210,17 +3238,17 @@
/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
/// amount. The result has the specified value type.
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
- MVT VT, SelectionDAG &DAG) {
+ MVT VT, SelectionDAG &DAG, DebugLoc dl) {
// Force LHS/RHS to be the right type.
- LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
- RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
+ LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
+ RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
SDValue Ops[16];
for (unsigned i = 0; i != 16; ++i)
Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
- SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
- return DAG.getNode(ISD::BIT_CONVERT, VT, T);
+ SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, LHS, RHS,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops,16));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
}
// If this is a case we can't handle, return null and let the default
@@ -3236,6 +3264,7 @@
// zero.
uint64_t VectorBits[2];
uint64_t UndefBits[2];
+ DebugLoc dl = Op.getDebugLoc();
if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits))
return SDValue(); // Not a constant vector.
@@ -3254,8 +3283,8 @@
// Canonicalize all zero vectors to be v4i32.
if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
SDValue Z = DAG.getConstant(0, MVT::i32);
- Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
- Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
+ Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
}
return Op;
}
@@ -3263,7 +3292,7 @@
// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
if (SextVal >= -16 && SextVal <= 15)
- return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
+ return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
// Two instruction sequences.
@@ -3271,9 +3300,9 @@
// If this value is in the range [-32,30] and is even, use:
// tmp = VSPLTI[bhw], result = add tmp, tmp
if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
- SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG);
- Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+ SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
+ Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
@@ -3281,15 +3310,15 @@
// for fneg/fabs.
if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
// Make -1 and vspltisw -1:
- SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
+ SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
// Make the VSLW intrinsic, computing 0x8000_0000.
SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
- OnesV, DAG);
+ OnesV, DAG, dl);
// xor by OnesV to invert it.
- Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+ Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
// Check to see if this is a wide variety of vsplti*, binop self cases.
@@ -3310,63 +3339,63 @@
// vsplti + shl self.
if (SextVal == (i << (int)TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
Intrinsic::ppc_altivec_vslw
};
- Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+ Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
// vsplti + srl self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
Intrinsic::ppc_altivec_vsrw
};
- Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+ Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
// vsplti + sra self.
if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
- SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
Intrinsic::ppc_altivec_vsraw
};
- Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+ Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
// vsplti + rol self.
if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
- SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
+ SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
static const unsigned IIDs[] = { // Intrinsic to use for each size.
Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
Intrinsic::ppc_altivec_vrlw
};
- Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
+ Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
}
// t = vsplti c, result = vsldoi t, t, 1
if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
- SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
- return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
+ return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
}
// t = vsplti c, result = vsldoi t, t, 2
if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
- SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
- return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
+ return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
}
// t = vsplti c, result = vsldoi t, t, 3
if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
- SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
- return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
+ SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
+ return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
}
}
@@ -3374,17 +3403,17 @@
// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
if (SextVal >= 0 && SextVal <= 31) {
- SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
- SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
- LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
+ SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
+ LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
}
// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
if (SextVal >= -31 && SextVal <= 0) {
- SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
- SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
- LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
+ SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
+ SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
+ LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
}
}
@@ -3394,7 +3423,8 @@
/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
/// the specified operations to build the shuffle.
static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
- SDValue RHS, SelectionDAG &DAG) {
+ SDValue RHS, SelectionDAG &DAG,
+ DebugLoc dl) {
unsigned OpNum = (PFEntry >> 26) & 0x0F;
unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
@@ -3419,8 +3449,8 @@
}
SDValue OpLHS, OpRHS;
- OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
- OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
+ OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
+ OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
unsigned ShufIdxs[16];
switch (OpNum) {
@@ -3454,18 +3484,19 @@
ShufIdxs[i] = (i&3)+12;
break;
case OP_VSLDOI4:
- return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
+ return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
case OP_VSLDOI8:
- return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
+ return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
case OP_VSLDOI12:
- return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
+ return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
}
SDValue Ops[16];
for (unsigned i = 0; i != 16; ++i)
Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
- return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(),
+ OpLHS, OpRHS,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
}
/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
@@ -3474,6 +3505,7 @@
/// lowered into a vperm.
SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
SDValue PermMask = Op.getOperand(2);
@@ -3562,7 +3594,7 @@
// available, if this block is within a loop, we should avoid using vperm
// for 3-operation perms and use a constant pool load instead.
if (Cost < 3)
- return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
+ return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
}
// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
@@ -3587,9 +3619,9 @@
MVT::i8));
}
- SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
+ SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
&ResultMask[0], ResultMask.size());
- return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
+ return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
}
/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
@@ -3642,6 +3674,7 @@
SelectionDAG &DAG) {
// If this is a lowered altivec predicate compare, CompareOpc is set to the
// opcode number of the comparison.
+ DebugLoc dl = Op.getDebugLoc();
int CompareOpc;
bool isDot;
if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
@@ -3649,10 +3682,10 @@
// If this is a non-dot comparison, make the VCMP node and we are done.
if (!isDot) {
- SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
+ SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
Op.getOperand(1), Op.getOperand(2),
DAG.getConstant(CompareOpc, MVT::i32));
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
}
// Create the PPCISD altivec 'dot' comparison node.
@@ -3664,11 +3697,11 @@
std::vector<MVT> VTs;
VTs.push_back(Op.getOperand(2).getValueType());
VTs.push_back(MVT::Flag);
- SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
+ SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Now that we have the comparison, emit a copy from the CR to a GPR.
// This is flagged to the above dot comparison.
- SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
+ SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
DAG.getRegister(PPC::CR6, MVT::i32),
CompNode.getValue(1));
@@ -3692,21 +3725,22 @@
}
// Shift the bit into the low position.
- Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
+ Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
DAG.getConstant(8-(3-BitNo), MVT::i32));
// Isolate the bit.
- Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
+ Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
DAG.getConstant(1, MVT::i32));
// If we are supposed to, toggle the bit.
if (InvertBit)
- Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
+ Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
DAG.getConstant(1, MVT::i32));
return Flags;
}
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// Create a stack slot that is 16-byte aligned.
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(16, 16);
@@ -3714,56 +3748,58 @@
SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
// Store the input value into Value#0 of the stack slot.
- SDValue Store = DAG.getStore(DAG.getEntryNode(),
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
Op.getOperand(0), FIdx, NULL, 0);
// Load it out.
- return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
+ return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
}
SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
if (Op.getValueType() == MVT::v4i32) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
- SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
+ SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
+ SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
SDValue RHSSwap = // = vrlw RHS, 16
- BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
+ BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
// Shrinkify inputs to v8i16.
- LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
- RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
- RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
+ LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
+ RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
+ RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
// Low parts multiplied together, generating 32-bit results (we ignore the
// top parts).
SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
- LHS, RHS, DAG, MVT::v4i32);
+ LHS, RHS, DAG, dl, MVT::v4i32);
SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
- LHS, RHSSwap, Zero, DAG, MVT::v4i32);
+ LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
// Shift the high parts up 16 bits.
- HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
- return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
+ HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
+ Neg16, DAG, dl);
+ return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
} else if (Op.getValueType() == MVT::v8i16) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
- SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
+ SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
- LHS, RHS, Zero, DAG);
+ LHS, RHS, Zero, DAG, dl);
} else if (Op.getValueType() == MVT::v16i8) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
// Multiply the even 8-bit parts, producing 16-bit sums.
SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
- LHS, RHS, DAG, MVT::v8i16);
- EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
+ LHS, RHS, DAG, dl, MVT::v8i16);
+ EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
// Multiply the odd 8-bit parts, producing 16-bit sums.
SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
- LHS, RHS, DAG, MVT::v8i16);
- OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
+ LHS, RHS, DAG, dl, MVT::v8i16);
+ OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
// Merge the results together.
SDValue Ops[16];
@@ -3771,8 +3807,8 @@
Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
}
- return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
- DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, EvenParts, OddParts,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
} else {
assert(0 && "Unknown mul to lower!");
abort();
@@ -3811,7 +3847,8 @@
return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
- case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
+ case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG,
+ Op.getDebugLoc());
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
@@ -3837,6 +3874,7 @@
void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
+ DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) {
default:
assert(false && "Do not know how to custom type legalize this operation!");
@@ -3844,9 +3882,11 @@
case ISD::FP_ROUND_INREG: {
assert(N->getValueType(0) == MVT::ppcf128);
assert(N->getOperand(0).getValueType() == MVT::ppcf128);
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0),
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
+ MVT::f64, N->getOperand(0),
DAG.getIntPtrConstant(0));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0),
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
+ MVT::f64, N->getOperand(0),
DAG.getIntPtrConstant(1));
// This sequence changes FPSCR to do round-to-zero, adds the two halves
@@ -3857,7 +3897,7 @@
NodeTys.push_back(MVT::f64); // Return register
NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
- Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
+ Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
MFFSreg = Result.getValue(0);
InFlag = Result.getValue(1);
@@ -3865,14 +3905,14 @@
NodeTys.push_back(MVT::Flag); // Returns a flag
Ops[0] = DAG.getConstant(31, MVT::i32);
Ops[1] = InFlag;
- Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
+ Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
InFlag = Result.getValue(0);
NodeTys.clear();
NodeTys.push_back(MVT::Flag); // Returns a flag
Ops[0] = DAG.getConstant(30, MVT::i32);
Ops[1] = InFlag;
- Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
+ Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
InFlag = Result.getValue(0);
NodeTys.clear();
@@ -3881,7 +3921,7 @@
Ops[0] = Lo;
Ops[1] = Hi;
Ops[2] = InFlag;
- Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
+ Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
FPreg = Result.getValue(0);
InFlag = Result.getValue(1);
@@ -3891,16 +3931,17 @@
Ops[1] = MFFSreg;
Ops[2] = FPreg;
Ops[3] = InFlag;
- Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
+ Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
FPreg = Result.getValue(0);
// We know the low half is about to be thrown away, so just use something
// convenient.
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::ppcf128, FPreg, FPreg));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
+ FPreg, FPreg));
return;
}
case ISD::FP_TO_SINT:
- Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG));
+ Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG, dl));
return;
}
}
@@ -3925,6 +3966,7 @@
unsigned ptrA = MI->getOperand(1).getReg();
unsigned ptrB = MI->getOperand(2).getReg();
unsigned incr = MI->getOperand(3).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -3950,13 +3992,13 @@
// bne- loopMBB
// fallthrough --> exitMBB
BB = loopMBB;
- BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
.addReg(ptrA).addReg(ptrB);
if (BinOpcode)
- BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
- BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
BB->addSuccessor(exitMBB);
@@ -3989,6 +4031,7 @@
unsigned ptrA = MI->getOperand(1).getReg();
unsigned ptrB = MI->getOperand(2).getReg();
unsigned incr = MI->getOperand(3).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -4041,47 +4084,47 @@
if (ptrA!=PPC::R0) {
Ptr1Reg = RegInfo.createVirtualRegister(RC);
- BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
.addReg(ptrA).addReg(ptrB);
} else {
Ptr1Reg = ptrB;
}
- BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
- BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
if (is64bit)
- BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(61);
else
- BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
- BuildMI(BB, TII->get(PPC::SLW), Incr2Reg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
.addReg(incr).addReg(ShiftReg);
if (is8bit)
- BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
else {
- BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
- BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
+ BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
}
- BuildMI(BB, TII->get(PPC::SLW), MaskReg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
.addReg(Mask2Reg).addReg(ShiftReg);
BB = loopMBB;
- BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
+ BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
.addReg(PPC::R0).addReg(PtrReg);
if (BinOpcode)
- BuildMI(BB, TII->get(BinOpcode), TmpReg)
+ BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
.addReg(Incr2Reg).addReg(TmpDestReg);
- BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
.addReg(TmpDestReg).addReg(MaskReg);
- BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
.addReg(TmpReg).addReg(MaskReg);
- BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
.addReg(Tmp3Reg).addReg(Tmp2Reg);
- BuildMI(BB, TII->get(PPC::STWCX))
+ BuildMI(BB, dl, TII->get(PPC::STWCX))
.addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
BB->addSuccessor(exitMBB);
@@ -4089,7 +4132,7 @@
// exitMBB:
// ...
BB = exitMBB;
- BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
+ BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
return BB;
}
@@ -4126,7 +4169,8 @@
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
- BuildMI(BB, TII->get(PPC::BCC))
+ DebugLoc dl = MI->getDebugLoc();
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
@@ -4149,7 +4193,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
}
@@ -4225,6 +4269,7 @@
unsigned ptrB = MI->getOperand(2).getReg();
unsigned oldval = MI->getOperand(3).getReg();
unsigned newval = MI->getOperand(4).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -4253,26 +4298,26 @@
// st[wd]cx. dest, ptr
// exitBB:
BB = loop1MBB;
- BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
.addReg(ptrA).addReg(ptrB);
- BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
.addReg(oldval).addReg(dest);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
BB->addSuccessor(loop2MBB);
BB->addSuccessor(midMBB);
BB = loop2MBB;
- BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(newval).addReg(ptrA).addReg(ptrB);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
- BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
+ BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
BB->addSuccessor(loop1MBB);
BB->addSuccessor(exitMBB);
BB = midMBB;
- BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(dest).addReg(ptrA).addReg(ptrB);
BB->addSuccessor(exitMBB);
@@ -4292,6 +4337,7 @@
unsigned ptrB = MI->getOperand(2).getReg();
unsigned oldval = MI->getOperand(3).getReg();
unsigned newval = MI->getOperand(4).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -4356,69 +4402,73 @@
// srw dest, tmpDest, shift
if (ptrA!=PPC::R0) {
Ptr1Reg = RegInfo.createVirtualRegister(RC);
- BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
.addReg(ptrA).addReg(ptrB);
} else {
Ptr1Reg = ptrB;
}
- BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
- BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
if (is64bit)
- BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(61);
else
- BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
- BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
.addReg(newval).addReg(ShiftReg);
- BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
.addReg(oldval).addReg(ShiftReg);
if (is8bit)
- BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
else {
- BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
- BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
+ BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
+ .addReg(Mask3Reg).addImm(65535);
}
- BuildMI(BB, TII->get(PPC::SLW), MaskReg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
.addReg(Mask2Reg).addReg(ShiftReg);
- BuildMI(BB, TII->get(PPC::AND), NewVal3Reg)
+ BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
.addReg(NewVal2Reg).addReg(MaskReg);
- BuildMI(BB, TII->get(PPC::AND), OldVal3Reg)
+ BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
.addReg(OldVal2Reg).addReg(MaskReg);
BB = loop1MBB;
- BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
+ BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
.addReg(PPC::R0).addReg(PtrReg);
- BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg);
- BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0)
+ BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
+ .addReg(TmpDestReg).addReg(MaskReg);
+ BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
.addReg(TmpReg).addReg(OldVal3Reg);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
BB->addSuccessor(loop2MBB);
BB->addSuccessor(midMBB);
BB = loop2MBB;
- BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg);
- BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg);
- BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
+ BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
+ .addReg(TmpDestReg).addReg(MaskReg);
+ BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
+ .addReg(Tmp2Reg).addReg(NewVal3Reg);
+ BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
.addReg(PPC::R0).addReg(PtrReg);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
- BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
+ BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
BB->addSuccessor(loop1MBB);
BB->addSuccessor(exitMBB);
BB = midMBB;
- BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg)
+ BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
.addReg(PPC::R0).addReg(PtrReg);
BB->addSuccessor(exitMBB);
// exitMBB:
// ...
BB = exitMBB;
- BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
+ BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
} else {
assert(0 && "Unexpected instr type to insert");
}
@@ -4435,6 +4485,7 @@
DAGCombinerInfo &DCI) const {
TargetMachine &TM = getTargetMachine();
SelectionDAG &DAG = DCI.DAG;
+ DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) {
default: break;
case PPCISD::SHL:
@@ -4467,16 +4518,16 @@
N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
SDValue Val = N->getOperand(0).getOperand(0);
if (Val.getValueType() == MVT::f32) {
- Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
}
- Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
if (N->getValueType(0) == MVT::f32) {
- Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
+ Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
DAG.getIntPtrConstant(0));
DCI.AddToWorklist(Val.getNode());
}
@@ -4497,13 +4548,13 @@
N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
SDValue Val = N->getOperand(1).getOperand(0);
if (Val.getValueType() == MVT::f32) {
- Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
}
- Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
+ Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
DCI.AddToWorklist(Val.getNode());
- Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
+ Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
N->getOperand(2), N->getOperand(3));
DCI.AddToWorklist(Val.getNode());
return Val;
@@ -4517,10 +4568,10 @@
SDValue BSwapOp = N->getOperand(1).getOperand(0);
// Do an any-extend to 32-bits if this is a half-word input.
if (BSwapOp.getValueType() == MVT::i16)
- BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
+ BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
- return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
- N->getOperand(2), N->getOperand(3),
+ return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
+ BSwapOp, N->getOperand(2), N->getOperand(3),
DAG.getValueType(N->getOperand(1).getValueType()));
}
break;
@@ -4542,12 +4593,12 @@
MO, // MemOperand
DAG.getValueType(N->getValueType(0)) // VT
};
- SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
+ SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
// If this is an i16 load, insert the truncate.
SDValue ResVal = BSLoad;
if (N->getValueType(0) == MVT::i16)
- ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
+ ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
// First, combine the bswap away. This makes the value produced by the
// load dead.
@@ -4635,7 +4686,7 @@
if (CC == ISD::SETEQ) // Cond never true, remove branch.
return N->getOperand(0);
// Always !=, turn it into an unconditional branch.
- return DAG.getNode(ISD::BR, MVT::Other,
+ return DAG.getNode(ISD::BR, dl, MVT::Other,
N->getOperand(0), N->getOperand(4));
}
@@ -4650,7 +4701,7 @@
};
VTs.push_back(LHS.getOperand(2).getValueType());
VTs.push_back(MVT::Flag);
- SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
+ SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Unpack the result based on how the target uses it.
PPC::Predicate CompOpc;
@@ -4670,7 +4721,7 @@
break;
}
- return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
+ return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
DAG.getConstant(CompOpc, MVT::i32),
DAG.getRegister(PPC::CR6, MVT::i32),
N->getOperand(4), CompNode.getValue(1));
@@ -4887,6 +4938,7 @@
}
SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
@@ -4900,10 +4952,12 @@
// Make sure the function really does not optimize away the store of the RA
// to the stack.
FuncInfo->setLRStoreRequired();
- return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
+ return DAG.getLoad(getPointerTy(), dl,
+ DAG.getEntryNode(), RetAddrFI, NULL, 0);
}
SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
@@ -4917,10 +4971,10 @@
&& MFI->getStackSize();
if (isPPC64)
- return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
+ return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
MVT::i64);
else
- return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,
+ return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
MVT::i32);
}
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCISelLowering.h Sat Feb 14 07:20:23 2009
@@ -340,10 +340,11 @@
SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
- int SPDiff,
- SDValue Chain,
- SDValue &LROpOut,
- SDValue &FPOpOut);
+ int SPDiff,
+ SDValue Chain,
+ SDValue &LROpOut,
+ SDValue &FPOpOut,
+ DebugLoc dl);
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
@@ -374,7 +375,7 @@
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget);
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
- SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -174,7 +174,7 @@
// Create a new instruction.
unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
bool Reg0IsDead = MI->getOperand(0).isDead();
- return BuildMI(MF, MI->getDesc())
+ return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
.addReg(Reg0, true, false, false, Reg0IsDead)
.addReg(Reg2, false, false, Reg2IsKill)
.addReg(Reg1, false, false, Reg1IsKill)
@@ -197,7 +197,10 @@
void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
- BuildMI(MBB, MI, get(PPC::NOP));
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
+ BuildMI(MBB, MI, DL, get(PPC::NOP));
}
@@ -289,6 +292,8 @@
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -297,17 +302,17 @@
// One-way branch.
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch
- BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
else // Conditional branch
- BuildMI(&MBB, get(PPC::BCC))
+ BuildMI(&MBB, dl, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return 1;
}
// Two-way Conditional Branch.
- BuildMI(&MBB, get(PPC::BCC))
+ BuildMI(&MBB, dl, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
- BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
+ BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
return 2;
}
@@ -321,20 +326,23 @@
return false;
}
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
if (DestRC == PPC::GPRCRegisterClass) {
- BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (DestRC == PPC::G8RCRegisterClass) {
- BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (DestRC == PPC::F4RCRegisterClass) {
- BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
} else if (DestRC == PPC::F8RCRegisterClass) {
- BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
} else if (DestRC == PPC::CRRCRegisterClass) {
- BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
} else if (DestRC == PPC::VRRCRegisterClass) {
- BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (DestRC == PPC::CRBITRCRegisterClass) {
- BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
// Attempt to copy register that is not GPR or FPR
return false;
@@ -349,43 +357,44 @@
int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const{
+ DebugLoc DL = DebugLoc::getUnknownLoc();
if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
.addReg(SrcReg, false, false, isKill),
FrameIdx));
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack.
- NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
.addReg(PPC::R11, false, false, isKill),
FrameIdx));
}
} else if (RC == PPC::G8RCRegisterClass) {
if (SrcReg != PPC::LR8) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
.addReg(SrcReg, false, false, isKill), FrameIdx));
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack.
- NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
.addReg(PPC::X11, false, false, isKill), FrameIdx));
}
} else if (RC == PPC::F8RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
.addReg(SrcReg, false, false, isKill), FrameIdx));
} else if (RC == PPC::F4RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
.addReg(SrcReg, false, false, isKill), FrameIdx));
} else if (RC == PPC::CRRCRegisterClass) {
if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
(EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
// FIXME (64-bit): Enable
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
.addReg(SrcReg, false, false, isKill),
FrameIdx));
return true;
@@ -393,18 +402,18 @@
// FIXME: We use R0 here, because it isn't available for RA. We need to
// store the CR in the low 4-bits of the saved value. First, issue a MFCR
// to save all of the CRBits.
- NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0));
// If the saved register wasn't CR0, shift the bits left so that they are
// in CR0's slot.
if (SrcReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
// rlwinm r0, r0, ShiftBits, 0, 31.
- NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
}
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
.addReg(PPC::R0, false, false, isKill),
FrameIdx));
}
@@ -440,9 +449,9 @@
// STVX VAL, 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0));
- NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
} else {
assert(0 && "Unknown regclass!");
@@ -484,6 +493,7 @@
return;
}
+ DebugLoc DL = DebugLoc::getUnknownLoc();
unsigned Opc = 0;
if (RC == PPC::GPRCRegisterClass) {
Opc = PPC::STW;
@@ -499,7 +509,7 @@
assert(0 && "Unknown regclass!");
abort();
}
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
@@ -515,37 +525,37 @@
}
void
-PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
+PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs)const{
if (RC == PPC::GPRCRegisterClass) {
if (DestReg != PPC::LR) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
- FrameIdx));
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
+ DestReg), FrameIdx));
} else {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
- FrameIdx));
- NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
+ PPC::R11), FrameIdx));
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
}
} else if (RC == PPC::G8RCRegisterClass) {
if (DestReg != PPC::LR8) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
FrameIdx));
} else {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
- FrameIdx));
- NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
+ PPC::R11), FrameIdx));
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
}
} else if (RC == PPC::F8RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
FrameIdx));
} else if (RC == PPC::F4RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
FrameIdx));
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0),
FrameIdx));
// If the reloaded register isn't CR0, shift the bits right so that they are
@@ -553,11 +563,11 @@
if (DestReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
- NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
}
- NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
} else if (RC == PPC::CRBITRCRegisterClass) {
unsigned Reg = 0;
@@ -578,7 +588,7 @@
else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
Reg = PPC::CR7;
- return LoadRegFromStackSlot(MF, Reg, FrameIdx,
+ return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
PPC::CRRCRegisterClass, NewMIs);
} else if (RC == PPC::VRRCRegisterClass) {
@@ -587,9 +597,9 @@
// Dest = LVX 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0));
- NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
.addReg(PPC::R0));
} else {
assert(0 && "Unknown regclass!");
@@ -604,7 +614,9 @@
const TargetRegisterClass *RC) const {
MachineFunction &MF = *MBB.getParent();
SmallVector<MachineInstr*, 4> NewMIs;
- LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
MBB.insert(MI, NewMIs[i]);
}
@@ -614,7 +626,8 @@
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs)const{
if (Addr[0].isFI()) {
- LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
+ LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(),
+ DestReg, Addr[0].getIndex(), RC, NewMIs);
return;
}
@@ -635,7 +648,8 @@
assert(0 && "Unknown regclass!");
abort();
}
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -668,13 +682,13 @@
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
.addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
.addReg(OutReg, true, false, false, isDead),
FrameIndex);
}
@@ -683,13 +697,13 @@
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
.addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
.addReg(OutReg, true, false, false, isDead),
FrameIndex);
}
@@ -697,13 +711,13 @@
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
.addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
.addReg(OutReg, true, false, false, isDead),
FrameIndex);
}
@@ -711,13 +725,13 @@
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
.addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
+ NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
.addReg(OutReg, true, false, false, isDead),
FrameIndex);
}
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCInstrInfo.h Sat Feb 14 07:20:23 2009
@@ -69,7 +69,7 @@
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
- void LoadRegFromStackSlot(MachineFunction &MF,
+ void LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
Modified: llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -426,18 +426,20 @@
unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
+ MachineInstr *MI = I;
+ DebugLoc dl = MI->getDebugLoc();
if (isInt16(CalleeAmt)) {
- BuildMI(MBB, I, TII.get(ADDIInstr), StackReg).addReg(StackReg).
+ BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
addImm(CalleeAmt);
} else {
MachineBasicBlock::iterator MBBI = I;
- BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
.addImm(CalleeAmt >> 16);
- BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
.addReg(TmpReg, false, false, true)
.addImm(CalleeAmt & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(ADDInstr))
+ BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
.addReg(StackReg)
.addReg(StackReg)
.addReg(TmpReg);
@@ -481,6 +483,7 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
// Determine whether 64-bit pointers are used.
bool LP64 = Subtarget.isPPC64();
+ DebugLoc dl = MI.getDebugLoc();
// Get the maximum call stack size.
unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
@@ -511,20 +514,20 @@
Reg = PPC::R0;
if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
- BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
.addReg(PPC::R31)
.addImm(FrameSize);
} else if (LP64) {
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
- BuildMI(MBB, II, TII.get(PPC::LD), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
.addImm(0)
.addReg(PPC::X1);
else
- BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
+ BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
.addImm(0)
.addReg(PPC::X1);
} else {
- BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
.addImm(0)
.addReg(PPC::R1);
}
@@ -533,39 +536,39 @@
// address of new allocated space.
if (LP64) {
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
- BuildMI(MBB, II, TII.get(PPC::STDUX))
+ BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(Reg, false, false, true)
.addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg());
else
- BuildMI(MBB, II, TII.get(PPC::STDUX))
+ BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(PPC::X0, false, false, true)
.addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
- BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
.addReg(PPC::X1)
.addImm(maxCallFrameSize);
else
// Implicitly kill the register.
- BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
.addReg(PPC::X1)
.addImm(maxCallFrameSize)
.addReg(MI.getOperand(1).getReg(), false, true, true);
} else {
- BuildMI(MBB, II, TII.get(PPC::STWUX))
+ BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
.addReg(Reg, false, false, true)
.addReg(PPC::R1)
.addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
- BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
.addReg(PPC::R1)
.addImm(maxCallFrameSize);
else
// Implicitly kill the register.
- BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
.addReg(PPC::R1)
.addImm(maxCallFrameSize)
.addReg(MI.getOperand(1).getReg(), false, true, true);
@@ -590,6 +593,7 @@
MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
// Get the instruction's basic block.
MachineBasicBlock &MBB = *MI.getParent();
+ DebugLoc dl = MI.getDebugLoc();
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
@@ -599,10 +603,10 @@
// We need to store the CR in the low 4-bits of the saved value. First, issue
// an MFCR to save all of the CRBits. Add an implicit kill of the CR.
if (!MI.getOperand(0).isKill())
- BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
+ BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg);
else
// Implicitly kill the CR register.
- BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
.addReg(MI.getOperand(0).getReg(), false, true, true);
// If the saved register wasn't CR0, shift the bits left so that they are in
@@ -610,13 +614,13 @@
unsigned SrcReg = MI.getOperand(0).getReg();
if (SrcReg != PPC::CR0)
// rlwinm rA, rA, ShiftBits, 0, 31.
- BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
.addReg(Reg, false, false, true)
.addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
.addImm(0)
.addImm(31);
- addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
+ addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
.addReg(Reg, false, false, MI.getOperand(1).getImm()),
FrameIndex);
@@ -636,6 +640,7 @@
MachineFunction &MF = *MBB.getParent();
// Get the frame info.
MachineFrameInfo *MFI = MF.getFrameInfo();
+ DebugLoc dl = MI.getDebugLoc();
// Find out which operand is the frame index.
unsigned FIOperandNo = 0;
@@ -727,9 +732,9 @@
SReg = PPC::R0;
// Insert a set of rA with the full offset value before the ld, st, or add
- BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
+ BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
.addImm(Offset >> 16);
- BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
+ BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
.addReg(SReg, false, false, true)
.addImm(Offset);
@@ -815,6 +820,7 @@
// transform this into the appropriate ORI instruction.
static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
MachineFunction *MF = MI->getParent()->getParent();
+ DebugLoc dl = MI->getDebugLoc();
unsigned UsedRegMask = 0;
for (unsigned i = 0; i != 32; ++i)
@@ -850,33 +856,33 @@
if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
if (DstReg != SrcReg)
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(SrcReg)
.addImm(UsedRegMask);
else
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(SrcReg, false, false, true)
.addImm(UsedRegMask);
} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
if (DstReg != SrcReg)
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg)
.addImm(UsedRegMask >> 16);
else
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg, false, false, true)
.addImm(UsedRegMask >> 16);
} else {
if (DstReg != SrcReg)
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg)
.addImm(UsedRegMask >> 16);
else
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg, false, false, true)
.addImm(UsedRegMask >> 16);
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(DstReg, false, false, true)
.addImm(UsedRegMask & 0xFFFF);
}
@@ -997,6 +1003,7 @@
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
!MF.getFunction()->doesNotThrow() ||
UnwindTablesMandatory;
@@ -1037,31 +1044,31 @@
if (IsPPC64) {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::STD))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
.addReg(PPC::X31)
.addImm(FPOffset/4)
.addReg(PPC::X1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::STD))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
.addReg(PPC::X0)
.addImm(LROffset / 4)
.addReg(PPC::X1);
} else {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::STW))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
.addReg(PPC::R31)
.addImm(FPOffset)
.addReg(PPC::R1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::STW))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
.addReg(PPC::R0)
.addImm(LROffset)
.addReg(PPC::R1);
@@ -1077,7 +1084,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer: r1 += NegFrameSize.
@@ -1088,30 +1095,30 @@
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
- BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R1)
.addImm(0)
.addImm(32 - Log2_32(MaxAlign))
.addImm(31);
- BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
.addReg(PPC::R0, false, false, true)
.addImm(NegFrameSize);
- BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
.addReg(PPC::R1)
.addReg(PPC::R1)
.addReg(PPC::R0);
} else if (isInt16(NegFrameSize)) {
- BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
.addReg(PPC::R1)
.addImm(NegFrameSize)
.addReg(PPC::R1);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
.addImm(NegFrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
.addReg(PPC::R0, false, false, true)
.addImm(NegFrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
.addReg(PPC::R1)
.addReg(PPC::R1)
.addReg(PPC::R0);
@@ -1121,29 +1128,29 @@
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
- BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
.addReg(PPC::X1)
.addImm(0)
.addImm(64 - Log2_32(MaxAlign));
- BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
.addReg(PPC::X0)
.addImm(NegFrameSize);
- BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
.addReg(PPC::X1)
.addReg(PPC::X1)
.addReg(PPC::X0);
} else if (isInt16(NegFrameSize)) {
- BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
.addReg(PPC::X1)
.addImm(NegFrameSize / 4)
.addReg(PPC::X1);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
.addImm(NegFrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
.addReg(PPC::X0, false, false, true)
.addImm(NegFrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
.addReg(PPC::X1)
.addReg(PPC::X1)
.addReg(PPC::X0);
@@ -1186,7 +1193,7 @@
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));
@@ -1197,11 +1204,11 @@
// If there is a frame pointer, copy R1 into R31
if (HasFP) {
if (!IsPPC64) {
- BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
.addReg(PPC::R1)
.addReg(PPC::R1);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
.addReg(PPC::X1)
.addReg(PPC::X1);
}
@@ -1212,6 +1219,7 @@
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
unsigned RetOpcode = MBBI->getOpcode();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
assert( (RetOpcode == PPC::BLR ||
RetOpcode == PPC::TCRETURNri ||
@@ -1274,73 +1282,75 @@
// value of R31 in this case.
if (FI->hasFastCall() && isInt16(FrameSize)) {
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
.addReg(PPC::R31).addImm(FrameSize);
} else if(FI->hasFastCall()) {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
.addImm(FrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
.addReg(PPC::R0, false, false, true)
.addImm(FrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::ADD4))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
.addReg(PPC::R1)
.addReg(PPC::R31)
.addReg(PPC::R0);
} else if (isInt16(FrameSize) &&
(!ALIGN_STACK || TargetAlign >= MaxAlign) &&
!MFI->hasVarSizedObjects()) {
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
.addReg(PPC::R1).addImm(FrameSize);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
+ .addImm(0).addReg(PPC::R1);
}
} else {
if (FI->hasFastCall() && isInt16(FrameSize)) {
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
.addReg(PPC::X31).addImm(FrameSize);
} else if(FI->hasFastCall()) {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
.addImm(FrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
.addReg(PPC::X0, false, false, true)
.addImm(FrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::ADD8))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
.addReg(PPC::X1)
.addReg(PPC::X31)
.addReg(PPC::X0);
} else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
!MFI->hasVarSizedObjects()) {
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
.addReg(PPC::X1).addImm(FrameSize);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
+ .addImm(0).addReg(PPC::X1);
}
}
}
if (IsPPC64) {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
.addImm(LROffset/4).addReg(PPC::X1);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
.addImm(FPOffset/4).addReg(PPC::X1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
} else {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
.addImm(LROffset).addReg(PPC::R1);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
.addImm(FPOffset).addReg(PPC::R1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
}
// Callee pop calling convention. Pop parameter/linkage area. Used for tail
@@ -1358,15 +1368,15 @@
unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
- BuildMI(MBB, MBBI, TII.get(ADDIInstr), StackReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
.addReg(StackReg).addImm(CallerAllocatedAmt);
} else {
- BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
.addImm(CallerAllocatedAmt >> 16);
- BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
.addReg(TmpReg, false, false, true)
.addImm(CallerAllocatedAmt & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(ADDInstr))
+ BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
.addReg(StackReg)
.addReg(FPReg)
.addReg(TmpReg);
@@ -1374,31 +1384,31 @@
} else if (RetOpcode == PPC::TCRETURNdi) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILB)).
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
} else if (RetOpcode == PPC::TCRETURNri) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
assert(JumpTarget.isReg() && "Expecting register operand.");
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR));
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
} else if (RetOpcode == PPC::TCRETURNai) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
} else if (RetOpcode == PPC::TCRETURNdi8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILB8)).
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
} else if (RetOpcode == PPC::TCRETURNri8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
assert(JumpTarget.isReg() && "Expecting register operand.");
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8));
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
} else if (RetOpcode == PPC::TCRETURNai8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
}
}
Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Sparc/DelaySlotFiller.cpp Sat Feb 14 07:20:23 2009
@@ -68,7 +68,7 @@
if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
- BuildMI(MBB, J, TII->get(SP::NOP));
+ BuildMI(MBB, J, DebugLoc::getUnknownLoc(), TII->get(SP::NOP));
++FilledSlots;
Changed = true;
}
Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Sparc/FPMover.cpp Sat Feb 14 07:20:23 2009
@@ -84,6 +84,7 @@
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
MachineInstr *MI = I++;
+ DebugLoc dl = MI->getDebugLoc();
if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
MI->getOpcode() == SP::FpNEGD) {
Changed = true;
@@ -114,7 +115,7 @@
DOUT << "FPMover: the modified instr is: " << *MI;
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
- MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
+ MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
.addReg(OddSrcReg);
DOUT << "FPMover: the inserted instr is: " << *MI;
}
Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -141,6 +141,7 @@
SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
+ DebugLoc dl = N->getDebugLoc();
if (N->isMachineOpcode())
return NULL; // Already selected.
@@ -155,12 +156,12 @@
// Set the Y register to the high-part.
SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) {
- TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
+ TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS,
CurDAG->getTargetConstant(31, MVT::i32)), 0);
} else {
TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
}
- TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
+ TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart,
CurDAG->getRegister(SP::G0, MVT::i32)), 0);
// FIXME: Handle div by immediate.
@@ -174,7 +175,7 @@
SDValue MulLHS = N->getOperand(0);
SDValue MulRHS = N->getOperand(1);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
- SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
+ SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Sparc/SparcISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -36,6 +36,7 @@
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
+ DebugLoc dl = Op.getDebugLoc();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
@@ -61,15 +62,16 @@
// ISD::RET => ret chain, (regnum1,val1), ...
// So i*2+1 index only the regnums.
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ Op.getOperand(i*2+1), Flag);
// Guarantee that all emitted copies are stuck together with flags.
Flag = Chain.getValue(1);
}
if (Flag.getNode())
- return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
- return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
+ return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
+ return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
}
/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
@@ -103,16 +105,16 @@
case MVT::i32:
if (I->use_empty()) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
- ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
+ ArgValues.push_back(DAG.getUNDEF(ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
if (ObjectVT != MVT::i32) {
unsigned AssertOp = ISD::AssertSext;
- Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
+ Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
DAG.getValueType(ObjectVT));
- Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
+ Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
}
ArgValues.push_back(Arg);
} else {
@@ -120,17 +122,17 @@
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load;
if (ObjectVT == MVT::i32) {
- Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
+ Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
} else {
ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
// Sparc is big endian, so add an offset based on the ObjectVT.
unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
- FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
+ FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
DAG.getConstant(Offset, MVT::i32));
- Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
+ Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr,
NULL, 0, ObjectVT);
- Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
+ Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
}
ArgValues.push_back(Load);
}
@@ -140,19 +142,19 @@
case MVT::f32:
if (I->use_empty()) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
- ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
+ ArgValues.push_back(DAG.getUNDEF(ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
// FP value is passed in an integer register.
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
- SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
- Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
ArgValues.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
+ SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0);
ArgValues.push_back(Load);
}
ArgOffset += 4;
@@ -163,37 +165,37 @@
if (I->use_empty()) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
if (CurArgReg < ArgRegEnd) ++CurArgReg;
- ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
+ ArgValues.push_back(DAG.getUNDEF(ObjectVT));
} else {
SDValue HiVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
- HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
+ HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
+ HiVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
}
SDValue LoVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
- LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
+ LoVal = DAG.getCopyFromReg(Root, dl, VRegLo, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
+ LoVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
SDValue WholeValue =
- DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
+ DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
// If we want a double, do a bit convert.
if (ObjectVT == MVT::f64)
- WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
+ WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
ArgValues.push_back(WholeValue);
}
@@ -210,18 +212,18 @@
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
- SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
+ SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
+ OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
ArgOffset += 4;
}
}
if (!OutChains.empty())
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size()));
}
@@ -231,6 +233,7 @@
SDValue Chain = TheCall->getChain();
SDValue Callee = TheCall->getCallee();
bool isVarArg = TheCall->isVarArg();
+ DebugLoc dl = TheCall->getDebugLoc();
#if 0
// Analyze operands of the call, assigning locations to each operand.
@@ -344,7 +347,7 @@
ValToStore = Val;
} else {
// Convert this to a FP value in an int reg.
- Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
+ Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
}
break;
@@ -358,14 +361,15 @@
// Break into top and bottom parts by storing to the stack and loading
// out the parts as integers. Top part goes in a reg.
SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
- SDValue Store = DAG.getStore(DAG.getEntryNode(), Val, StackPtr, NULL, 0);
+ SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
+ Val, StackPtr, NULL, 0);
// Sparc is big-endian, so the high part comes first.
- SDValue Hi = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0);
+ SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
// Increment the pointer to the other half.
- StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
+ StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
DAG.getIntPtrConstant(4));
// Load the low part.
- SDValue Lo = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0);
+ SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
@@ -386,9 +390,9 @@
}
// Split the value into top and bottom part. Top part goes in a reg.
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
DAG.getConstant(1, MVT::i32));
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
DAG.getConstant(0, MVT::i32));
RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
@@ -406,8 +410,9 @@
if (ValToStore.getNode()) {
SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
- MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
+ MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
+ PtrOff, NULL, 0));
}
ArgOffset += ObjSize;
}
@@ -415,7 +420,7 @@
// Emit all stores, make sure the occur before any copies into physregs.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -429,7 +434,7 @@
if (Reg >= SP::I0 && Reg <= SP::I7)
Reg = Reg-SP::I0+SP::O0;
- Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
@@ -445,7 +450,7 @@
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
SDValue Ops[] = { Chain, Callee, InFlag };
- Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
+ Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
InFlag = Chain.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
@@ -467,7 +472,7 @@
if (Reg >= SP::I0 && Reg <= SP::I7)
Reg = Reg-SP::I0+SP::O0;
- Chain = DAG.getCopyFromReg(Chain, Reg,
+ Chain = DAG.getCopyFromReg(Chain, dl, Reg,
RVLocs[i].getValVT(), InFlag).getValue(1);
InFlag = Chain.getValue(2);
ResultVals.push_back(Chain.getValue(0));
@@ -476,7 +481,8 @@
ResultVals.push_back(Chain);
// Merge everything together with a MERGE_VALUES node.
- return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0],
+ return DAG.getNode(ISD::MERGE_VALUES, dl,
+ TheCall->getVTList(), &ResultVals[0],
ResultVals.size());
}
@@ -730,33 +736,39 @@
static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
+ // FIXME there isn't really any debug info here
+ DebugLoc dl = Op.getDebugLoc();
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
- SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
- SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
- return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
+ SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
+ SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
}
static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
+ // FIXME there isn't really any debug info here
+ DebugLoc dl = Op.getDebugLoc();
Constant *C = N->getConstVal();
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
- SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
- SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
- return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
+ SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
+ SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
}
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// Convert the fp value to integer in an FP register.
assert(Op.getValueType() == MVT::i32);
- Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
- return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+ Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
}
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
assert(Op.getOperand(0).getValueType() == MVT::i32);
- SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
+ SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
- return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
+ return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
}
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
@@ -765,6 +777,7 @@
SDValue LHS = Op.getOperand(2);
SDValue RHS = Op.getOperand(3);
SDValue Dest = Op.getOperand(4);
+ DebugLoc dl = Op.getDebugLoc();
unsigned Opc, SPCC = ~0U;
// If this is a br_cc of a "setcc", and if the setcc got lowered into
@@ -778,15 +791,15 @@
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
SDValue Ops[2] = { LHS, RHS };
- CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
+ CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = SPISD::BRICC;
} else {
- CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
+ CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
Opc = SPISD::BRFCC;
}
- return DAG.getNode(Opc, MVT::Other, Chain, Dest,
+ return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
@@ -796,6 +809,7 @@
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDValue TrueVal = Op.getOperand(2);
SDValue FalseVal = Op.getOperand(3);
+ DebugLoc dl = Op.getDebugLoc();
unsigned Opc, SPCC = ~0U;
// If this is a select_cc of a "setcc", and if the setcc got lowered into
@@ -808,15 +822,15 @@
VTs.push_back(LHS.getValueType()); // subcc returns a value
VTs.push_back(MVT::Flag);
SDValue Ops[2] = { LHS, RHS };
- CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
+ CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
Opc = SPISD::SELECT_ICC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
} else {
- CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
+ CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
Opc = SPISD::SELECT_FCC;
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
}
- return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
+ return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
}
@@ -824,12 +838,13 @@
SparcTargetLowering &TLI) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
- SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32,
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(TLI.getVarArgsFrameOffset(),
MVT::i32));
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
+ return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0);
}
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
@@ -838,45 +853,47 @@
SDValue InChain = Node->getOperand(0);
SDValue VAListPtr = Node->getOperand(1);
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
+ DebugLoc dl = Node->getDebugLoc();
+ SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0);
// Increment the pointer, VAList, to the next vaarg
- SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
+ SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
DAG.getConstant(VT.getSizeInBits()/8,
MVT::i32));
// Store the incremented VAList to the legalized pointer
- InChain = DAG.getStore(VAList.getValue(1), NextPtr,
+ InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
VAListPtr, SV, 0);
// Load the actual argument out of the pointer VAList, unless this is an
// f64 load.
if (VT != MVT::f64)
- return DAG.getLoad(VT, InChain, VAList, NULL, 0);
+ return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0);
// Otherwise, load it as i64, then do a bitconvert.
- SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
+ SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0);
// Bit-Convert the value to f64.
SDValue Ops[2] = {
- DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
V.getValue(1)
};
- return DAG.getMergeValues(Ops, 2);
+ return DAG.getMergeValues(Ops, 2, dl);
}
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
SDValue Chain = Op.getOperand(0); // Legalize the chain.
SDValue Size = Op.getOperand(1); // Legalize the size.
+ DebugLoc dl = Op.getDebugLoc();
unsigned SPReg = SP::O6;
- SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
- SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
- Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
+ SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
+ SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
+ Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
// The resultant pointer is actually 16 words from the bottom of the stack,
// to provide a register spill area.
- SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
+ SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
DAG.getConstant(96, MVT::i32));
SDValue Ops[2] = { NewVal, Chain };
- return DAG.getMergeValues(Ops, 2);
+ return DAG.getMergeValues(Ops, 2, dl);
}
@@ -909,6 +926,7 @@
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
unsigned BROpcode;
unsigned CC;
+ DebugLoc dl = MI->getDebugLoc();
// Figure out the conditional branch opcode to use for this select_cc.
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SELECT_CC!");
@@ -943,7 +961,7 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
+ BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
// Update machine-CFG edges by transferring all successors of the current
@@ -965,7 +983,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/SparcInstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Sparc/SparcInstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -107,28 +107,33 @@
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond)const{
+ // FIXME this should probably take a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
- BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
return 1;
}
bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *DestRC,
- const TargetRegisterClass *SrcRC) const {
+ MachineBasicBlock::iterator I,
+ unsigned DestReg, unsigned SrcReg,
+ const TargetRegisterClass *DestRC,
+ const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
// Not yet supported!
return false;
}
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (DestRC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
else if (DestRC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg);
else if (DestRC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
+ BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
.addReg(SrcReg);
else
// Can't copy this register
@@ -141,26 +146,30 @@
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0)
+ BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, false, false, isKill);
else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0)
+ BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, false, false, isKill);
else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
+ BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg, false, false, isKill);
else
assert(0 && "Can't store this register to stack slot");
}
void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ bool isKill,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
+ DebugLoc DL = DebugLoc::getUnknownLoc();
if (RC == SP::IntRegsRegisterClass)
Opc = SP::STri;
else if (RC == SP::FPRegsRegisterClass)
@@ -169,7 +178,7 @@
Opc = SP::STDFri;
else
assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -190,19 +199,22 @@
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
else
assert(0 && "Can't load this register from stack slot");
}
void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineOperand> &Addr,
+ const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
if (RC == SP::IntRegsRegisterClass)
@@ -213,7 +225,8 @@
Opc = SP::LDDFri;
else
assert(0 && "Can't load this register");
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
@@ -243,11 +256,15 @@
if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
if (OpNum == 0) // COPY -> STORE
- NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
- .addReg(MI->getOperand(2).getReg());
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addReg(MI->getOperand(2).getReg());
else // COPY -> LOAD
- NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg())
- .addFrameIndex(FI).addImm(0);
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
+ MI->getOperand(0).getReg())
+ .addFrameIndex(FI)
+ .addImm(0);
}
break;
case SP::FMOVS:
@@ -257,13 +274,19 @@
if (OpNum == 0) { // COPY -> STORE
unsigned SrcReg = MI->getOperand(1).getReg();
bool isKill = MI->getOperand(1).isKill();
- NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri))
- .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill);
+ NewMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isFloat ? SP::STFri : SP::STDFri))
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addReg(SrcReg, false, false, isKill);
} else { // COPY -> LOAD
unsigned DstReg = MI->getOperand(0).getReg();
bool isDead = MI->getOperand(0).isDead();
- NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri))
- .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0);
+ NewMI = BuildMI(MF, MI->getDebugLoc(),
+ get(isFloat ? SP::LDFri : SP::LDDFri))
+ .addReg(DstReg, true, false, false, isDead)
+ .addFrameIndex(FI)
+ .addImm(0);
}
break;
}
Modified: llvm/branches/Apple/Dib/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/Sparc/SparcRegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -66,11 +66,12 @@
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
MachineInstr &MI = *I;
+ DebugLoc dl = MI.getDebugLoc();
int Size = MI.getOperand(0).getImm();
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
- BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
+ BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
MBB.erase(I);
}
@@ -80,6 +81,7 @@
unsigned i = 0;
MachineInstr &MI = *II;
+ DebugLoc dl = MI.getDebugLoc();
while (!MI.getOperand(i).isFI()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
@@ -102,9 +104,9 @@
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
unsigned OffHi = (unsigned)Offset >> 10U;
- BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
- BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
+ BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
.addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
MI.getOperand(i).ChangeToRegister(SP::G1, false);
@@ -118,6 +120,7 @@
void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Get the number of bytes to allocate from the FrameInfo
int NumBytes = (int) MFI->getStackSize();
@@ -136,18 +139,18 @@
NumBytes = -NumBytes;
if (NumBytes >= -4096) {
- BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
+ BuildMI(MBB, MBB.begin(), dl, TII.get(SP::SAVEri),
SP::O6).addReg(SP::O6).addImm(NumBytes);
} else {
MachineBasicBlock::iterator InsertPt = MBB.begin();
// Emit this the hard way. This clobbers G1 which we always know is
// available here.
unsigned OffHi = (unsigned)NumBytes >> 10U;
- BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
+ BuildMI(MBB, InsertPt, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
- BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
+ BuildMI(MBB, InsertPt, dl, TII.get(SP::ORri), SP::G1)
.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
- BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
+ BuildMI(MBB, InsertPt, dl, TII.get(SP::SAVErr), SP::O6)
.addReg(SP::O6).addReg(SP::G1);
}
}
@@ -155,9 +158,10 @@
void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
+ DebugLoc dl = DebugLoc::getUnknownLoc();
assert(MBBI->getOpcode() == SP::RETL &&
"Can only put epilog before 'retl' instruction!");
- BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
+ BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
.addReg(SP::G0);
}
Modified: llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp Sat Feb 14 07:20:23 2009
@@ -207,6 +207,7 @@
///
bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
const Function *F = MF.getFunction();
+ this->MF = &MF;
unsigned CC = F->getCallingConv();
SetupMachineFunction(MF);
@@ -718,12 +719,24 @@
return false;
}
-/// printMachineInstruction -- Print out a single X86 LLVM instruction
-/// MI in AT&T syntax to the current output stream.
+/// printMachineInstruction -- Print out a single X86 LLVM instruction MI in
+/// AT&T syntax to the current output stream.
///
void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
++EmittedInsts;
+ if (TAI->doesSupportDebugInformation()) {
+ static DebugLoc PrevDL = DebugLoc::getUnknownLoc();
+ DebugLoc CurDL = MI->getDebugLoc();
+
+ if (!CurDL.isInvalid() && !CurDL.isUnknown() && PrevDL != CurDL) {
+ DebugLocTuple DLT = MF->getDebugLocTuple(CurDL);
+ printLabel(DW->RecordSourceLine(DLT.Line, DLT.Col, DLT.Src));
+ }
+
+ PrevDL = CurDL;
+ }
+
// Call the autogenerated instruction printer routines.
printInstruction(MI);
}
Modified: llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h Sat Feb 14 07:20:23 2009
@@ -29,6 +29,7 @@
struct MachineJumpTableInfo;
struct VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter {
+ MachineFunction *MF;
DwarfWriter *DW;
MachineModuleInfo *MMI;
const X86Subtarget *Subtarget;
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp Sat Feb 14 07:20:23 2009
@@ -231,7 +231,7 @@
}
ResultReg = createResultReg(RC);
- addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
+ addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
return true;
}
@@ -259,7 +259,7 @@
break;
}
- addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
+ addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
return true;
}
@@ -285,7 +285,8 @@
}
if (Opc) {
- addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addImm(CI->getSExtValue());
+ addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
+ .addImm(CI->getSExtValue());
return true;
}
}
@@ -463,7 +464,7 @@
StubAM.Base.Reg = AM.Base.Reg;
StubAM.GV = AM.GV;
unsigned ResultReg = createResultReg(RC);
- addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM);
+ addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM);
// Now construct the final address. Note that the Disp, Scale,
// and Index values may already be set here.
@@ -568,7 +569,7 @@
// CMPri, otherwise use CMPrr.
if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
- BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg)
+ BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
.addImm(Op1C->getSExtValue());
return true;
}
@@ -579,7 +580,7 @@
unsigned Op1Reg = getRegForValue(Op1);
if (Op1Reg == 0) return false;
- BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
return true;
}
@@ -601,9 +602,10 @@
unsigned EReg = createResultReg(&X86::GR8RegClass);
unsigned NPReg = createResultReg(&X86::GR8RegClass);
- BuildMI(MBB, TII.get(X86::SETEr), EReg);
- BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
- BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
+ BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
+ BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
+ BuildMI(MBB, DL,
+ TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
UpdateValueMap(I, ResultReg);
return true;
}
@@ -613,9 +615,9 @@
unsigned NEReg = createResultReg(&X86::GR8RegClass);
unsigned PReg = createResultReg(&X86::GR8RegClass);
- BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
- BuildMI(MBB, TII.get(X86::SETPr), PReg);
- BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
+ BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
+ BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
+ BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
UpdateValueMap(I, ResultReg);
return true;
}
@@ -654,7 +656,7 @@
if (!X86FastEmitCompare(Op0, Op1, VT))
return false;
- BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
+ BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
UpdateValueMap(I, ResultReg);
return true;
}
@@ -737,12 +739,12 @@
if (!X86FastEmitCompare(Op0, Op1, VT))
return false;
- BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB);
+ BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
if (Predicate == CmpInst::FCMP_UNE) {
// X86 requires a second branch to handle UNE (and OEQ,
// which is mapped to UNE above).
- BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB);
+ BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB);
}
FastEmitBranch(FalseMBB);
@@ -816,7 +818,7 @@
unsigned OpCode = SetMI->getOpcode();
if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
- BuildMI(MBB, TII.get((OpCode == X86::SETOr) ?
+ BuildMI(MBB, DL, TII.get((OpCode == X86::SETOr) ?
X86::JO : X86::JB)).addMBB(TrueMBB);
FastEmitBranch(FalseMBB);
MBB->addSuccessor(TrueMBB);
@@ -833,8 +835,8 @@
unsigned OpReg = getRegForValue(BI->getCondition());
if (OpReg == 0) return false;
- BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
- BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
+ BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
+ BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB);
FastEmitBranch(FalseMBB);
MBB->addSuccessor(TrueMBB);
return true;
@@ -893,7 +895,7 @@
// Fold immediate in shl(x,3).
if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
unsigned ResultReg = createResultReg(RC);
- BuildMI(MBB, TII.get(OpImm),
+ BuildMI(MBB, DL, TII.get(OpImm),
ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
UpdateValueMap(I, ResultReg);
return true;
@@ -907,11 +909,11 @@
// of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
// we're doing here.
if (CReg != X86::CL)
- BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
+ BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
.addReg(CReg).addImm(X86::SUBREG_8BIT);
unsigned ResultReg = createResultReg(RC);
- BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
+ BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
UpdateValueMap(I, ResultReg);
return true;
}
@@ -943,9 +945,9 @@
unsigned Op2Reg = getRegForValue(I->getOperand(2));
if (Op2Reg == 0) return false;
- BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
+ BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
unsigned ResultReg = createResultReg(RC);
- BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
+ BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
UpdateValueMap(I, ResultReg);
return true;
}
@@ -958,7 +960,7 @@
unsigned OpReg = getRegForValue(V);
if (OpReg == 0) return false;
unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
- BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
+ BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
UpdateValueMap(I, ResultReg);
return true;
}
@@ -975,7 +977,7 @@
unsigned OpReg = getRegForValue(V);
if (OpReg == 0) return false;
unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
- BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
+ BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
UpdateValueMap(I, ResultReg);
return true;
}
@@ -1008,7 +1010,7 @@
const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
unsigned CopyReg = createResultReg(CopyRC);
- BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
+ BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
// Then issue an extract_subreg.
unsigned ResultReg = FastEmitInst_extractsubreg(DstVT.getSimpleVT(),
@@ -1083,11 +1085,11 @@
return false;
unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
- BuildMI(MBB, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
+ BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
UpdateValueMap(&I, ResultReg);
ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
- BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
+ BuildMI(MBB, DL, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
X86::SETOr : X86::SETBr), ResultReg);
return true;
}
@@ -1204,7 +1206,7 @@
// Issue CALLSEQ_START
unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
- BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
+ BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
// Process argument: walk the register/memloc assignments, inserting
// copies / loads.
@@ -1291,8 +1293,8 @@
? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
: (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
MachineInstrBuilder MIB = CalleeOp
- ? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
- : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
+ ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp)
+ : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV);
// Add an implicit use GOT pointer in EBX.
if (!Subtarget->is64Bit() &&
@@ -1306,7 +1308,7 @@
// Issue CALLSEQ_END
unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
- BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
+ BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
// Now handle call return value (if any).
if (RetVT.getSimpleVT() != MVT::isVoid) {
@@ -1344,18 +1346,19 @@
unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
unsigned MemSize = ResVT.getSizeInBits()/8;
int FI = MFI.CreateStackObject(MemSize, MemSize);
- addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg);
+ addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
DstRC = ResVT == MVT::f32
? X86::FR32RegisterClass : X86::FR64RegisterClass;
Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
ResultReg = createResultReg(DstRC);
- addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
+ addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
}
if (AndToI1) {
// Mask out all but lowest bit for some call which produces an i1.
unsigned AndResult = createResultReg(X86::GR8RegisterClass);
- BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
+ BuildMI(MBB, DL,
+ TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
ResultReg = AndResult;
}
@@ -1461,7 +1464,7 @@
else
Opc = X86::LEA64r;
unsigned ResultReg = createResultReg(RC);
- addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
+ addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
return ResultReg;
}
return 0;
@@ -1484,7 +1487,7 @@
// Create the load from the constant pool.
unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
unsigned ResultReg = createResultReg(RC);
- addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset,
+ addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), MCPOffset,
PICBase);
return ResultReg;
@@ -1507,7 +1510,7 @@
unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
unsigned ResultReg = createResultReg(RC);
- addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
+ addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
return ResultReg;
}
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPoint.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPoint.cpp Sat Feb 14 07:20:23 2009
@@ -115,6 +115,8 @@
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
+ MachineInstr *MI = I;
+ DebugLoc dl = MI->getDebugLoc();
if (isAtTop(RegNo)) return;
unsigned STReg = getSTReg(RegNo);
@@ -128,15 +130,16 @@
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Emit an fxch to update the runtime processors version of the state.
- BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
+ BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
NumFXCH++;
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
+ DebugLoc dl = I->getDebugLoc();
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
- BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
+ BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
}
// popStackAfter - Pop the current value off of the top of the FP stack
@@ -549,6 +552,8 @@
/// instruction if it was modified in place.
///
void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
+ MachineInstr* MI = I;
+ DebugLoc dl = MI->getDebugLoc();
ASSERT_SORTED(PopTable);
assert(StackTop > 0 && "Cannot pop empty stack!");
RegMap[Stack[--StackTop]] = ~0; // Update state
@@ -560,7 +565,7 @@
if (Opcode == X86::UCOM_FPPr)
I->RemoveOperand(0);
} else { // Insert an explicit pop
- I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
+ I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
}
}
@@ -584,7 +589,9 @@
RegMap[TopReg] = OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
- I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
+ MachineInstr *MI = I;
+ DebugLoc dl = MI->getDebugLoc();
+ I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg);
}
@@ -788,6 +795,7 @@
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
+ DebugLoc dl = MI->getDebugLoc();
unsigned TOS = getStackEntry(0);
@@ -853,7 +861,7 @@
// Replace the old instruction with a new instruction
MBB->remove(I++);
- I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
+ I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
@@ -935,6 +943,7 @@
///
void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
+ DebugLoc dl = MI->getDebugLoc();
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SpecialFP instruction!");
case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
@@ -985,6 +994,19 @@
assert(StackTop == 1 && "Stack should have one element on it to return!");
--StackTop; // "Forget" we have something on the top of stack!
break;
+ case X86::FpSET_ST1_32:
+ case X86::FpSET_ST1_64:
+ case X86::FpSET_ST1_80:
+ // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
+ if (StackTop == 1) {
+ BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
+ NumFXCH++;
+ StackTop = 0;
+ break;
+ }
+ assert(StackTop == 2 && "Stack should have two element on it to return!");
+ --StackTop; // "Forget" we have something on the top of stack!
+ break;
case X86::MOV_Fp3232:
case X86::MOV_Fp3264:
case X86::MOV_Fp6432:
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPointRegKill.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPointRegKill.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPointRegKill.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86FloatingPointRegKill.cpp Sat Feb 14 07:20:23 2009
@@ -128,7 +128,7 @@
}
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
if (ContainsFPCode) {
- BuildMI(*MBB, MBBI->getFirstTerminator(),
+ BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc::getUnknownLoc(),
MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
++NumFPKill;
Changed = true;
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -441,7 +441,8 @@
else
Ops.push_back(Chain.getOperand(i));
SDValue NewChain =
- CurDAG->getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
+ CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
+ MVT::Other, &Ops[0], Ops.size());
Ops.clear();
Ops.push_back(NewChain);
}
@@ -658,12 +659,13 @@
MemVT = SrcIsSSE ? SrcVT : DstVT;
SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
+ DebugLoc dl = N->getDebugLoc();
// FIXME: optimize the case where the src/dest is a load or store?
- SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(),
+ SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
N->getOperand(0),
MemTmp, NULL, 0, MemVT);
- SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
+ SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
NULL, 0, MemVT);
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
@@ -713,7 +715,8 @@
MachineFrameInfo *MFI) {
const TargetInstrInfo *TII = TM.getInstrInfo();
if (Subtarget->isTargetCygMing())
- BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
+ BuildMI(BB, DebugLoc::getUnknownLoc(),
+ TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
}
void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
@@ -729,6 +732,7 @@
bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
bool isRoot, unsigned Depth) {
bool is64Bit = Subtarget->is64Bit();
+ DebugLoc dl = N.getDebugLoc();
DOUT << "MatchAddress: "; DEBUG(AM.dump());
// Limit recursion.
if (Depth > 5)
@@ -950,10 +954,11 @@
// Get the new AND mask, this folds to a constant.
SDValue X = Shift.getOperand(0);
- SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
+ SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
SDValue(C2, 0), SDValue(C1, 0));
- SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(), X, NewANDMask);
- SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, N.getValueType(),
+ SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
+ NewANDMask);
+ SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
NewAND, SDValue(C1, 0));
// Insert the new nodes into the topological ordering.
@@ -1164,6 +1169,7 @@
assert(!Subtarget->is64Bit() &&
"getTruncateTo8Bit is only needed on x86-32!");
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
+ DebugLoc dl = N0.getDebugLoc();
// Ensure that the source register has an 8-bit subreg on 32-bit targets
unsigned Opc;
@@ -1180,8 +1186,8 @@
// The use of MVT::Flag here is not strictly accurate, but it helps
// scheduling in some cases.
- N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
- return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ N0 = SDValue(CurDAG->getTargetNode(Opc, dl, N0VT, MVT::Flag, N0), 0);
+ return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
MVT::i8, N0, SRIdx, N0.getValue(1));
}
@@ -1195,7 +1201,8 @@
return NULL;
SDValue LSI = Node->getOperand(4); // MemOperand
const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
- return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8);
+ return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
+ MVT::i32, MVT::i32, MVT::Other, Ops, 8);
}
SDNode *X86DAGToDAGISel::Select(SDValue N) {
@@ -1203,7 +1210,8 @@
MVT NVT = Node->getValueType(0);
unsigned Opc, MOpc;
unsigned Opcode = Node->getOpcode();
-
+ DebugLoc dl = Node->getDebugLoc();
+
#ifndef NDEBUG
DOUT << std::string(Indent, ' ') << "Selecting: ";
DEBUG(Node->dump(CurDAG));
@@ -1282,24 +1290,24 @@
std::swap(N0, N1);
}
- SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
+ SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
N0, SDValue()).getValue(1);
if (foldedLoad) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6);
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the low half of the result, if it is needed.
if (!N.getValue(0).use_empty()) {
- SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
@@ -1315,17 +1323,18 @@
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
- Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
+ Result,
CurDAG->getTargetConstant(8, MVT::i8)), 0);
// Then truncate it down to i8.
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
- Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
MVT::i8, Result, SRIdx), 0);
} else {
- Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
InFlag = Result.getValue(2);
}
@@ -1405,29 +1414,30 @@
if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
- Ops, 5), 0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
+ MVT::Other, Ops, 5), 0);
Chain = Move.getValue(1);
ReplaceUses(N0.getValue(1), Chain);
} else {
Move =
- SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
+ SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
Chain = CurDAG->getEntryNode();
}
- Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
+ Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
InFlag = Chain.getValue(1);
} else {
InFlag =
- CurDAG->getCopyToReg(CurDAG->getEntryNode(),
+ CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
LoReg, N0, SDValue()).getValue(1);
if (isSigned && !signBitIsZero) {
// Sign extend the low part into the high part.
InFlag =
- SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
} else {
// Zero out the high part, effectively zero extending the input.
- SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
- InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
+ SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT),
+ 0);
+ InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg,
ClrNode, InFlag).getValue(1);
}
}
@@ -1435,18 +1445,18 @@
if (foldedLoad) {
SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
SDNode *CNode =
- CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
+ CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6);
InFlag = SDValue(CNode, 1);
// Update the chain.
ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
} else {
InFlag =
- SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
+ SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
}
// Copy the division (low) result, if it is needed.
if (!N.getValue(0).use_empty()) {
- SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
LoReg, NVT, InFlag);
InFlag = Result.getValue(2);
ReplaceUses(N.getValue(0), Result);
@@ -1462,17 +1472,19 @@
if (HiReg == X86::AH && Subtarget->is64Bit()) {
// Prevent use of AH in a REX instruction by referencing AX instead.
// Shift it down 8 bits.
- Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
X86::AX, MVT::i16, InFlag);
InFlag = Result.getValue(2);
- Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
- CurDAG->getTargetConstant(8, MVT::i8)), 0);
+ Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
+ Result,
+ CurDAG->getTargetConstant(8, MVT::i8)),
+ 0);
// Then truncate it down to i8.
SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
- Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
+ Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
MVT::i8, Result, SRIdx), 0);
} else {
- Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+ Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
HiReg, NVT, InFlag);
InFlag = Result.getValue(2);
}
@@ -1508,7 +1520,7 @@
break;
}
- SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
+ SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, NVT, TruncOp);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";
@@ -1563,7 +1575,7 @@
SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
TLI.getPointerTy());
SDValue Ops[] = { Tmp1, Tmp2, Chain };
- return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
+ return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
MVT::Other, Ops, 3);
break;
}
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -45,7 +45,7 @@
DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
// Forward declarations.
-static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
+static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl);
X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
: TargetLowering(TM) {
@@ -900,9 +900,12 @@
SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const {
if (usesGlobalOffsetTable())
- return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
+ return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
if (!Subtarget->isPICStyleRIPRel())
- return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
+ // This doesn't have DebugLoc associated with it, but is not really the
+ // same as a Register.
+ return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
+ getPointerTy());
return Table;
}
@@ -914,6 +917,7 @@
/// LowerRET - Lower an ISD::RET node.
SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
SmallVector<CCValAssign, 16> RVLocs;
@@ -955,7 +959,7 @@
for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
Operands.push_back(Chain.getOperand(i));
}
- return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
+ return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
Operands.size());
}
@@ -980,13 +984,13 @@
// If this is a copy from an xmm register to ST(0), use an FPExtend to
// change the value to the FP stack register class.
if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
- ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
RetOps.push_back(ValToCopy);
// Don't emit a copytoreg.
continue;
}
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
Flag = Chain.getValue(1);
}
@@ -1003,9 +1007,9 @@
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
- SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
- Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
Flag = Chain.getValue(1);
}
@@ -1015,7 +1019,8 @@
if (Flag.getNode())
RetOps.push_back(Flag);
- return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
+ return DAG.getNode(X86ISD::RET_FLAG, dl,
+ MVT::Other, &RetOps[0], RetOps.size());
}
@@ -1027,7 +1032,8 @@
SDNode *X86TargetLowering::
LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
-
+
+ DebugLoc dl = TheCall->getDebugLoc();
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
bool isVarArg = TheCall->isVarArg();
@@ -1057,7 +1063,7 @@
CopyVT = MVT::f80;
}
- Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
+ Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
CopyVT, InFlag).getValue(1);
SDValue Val = Chain.getValue(0);
InFlag = Chain.getValue(2);
@@ -1065,7 +1071,7 @@
if (CopyVT != RVLocs[i].getValVT()) {
// Round the F80 the right size, which also moves to the appropriate xmm
// register.
- Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
+ Val = DAG.getNode(ISD::FP_ROUND, dl, RVLocs[i].getValVT(), Val,
// This truncation won't change the value.
DAG.getIntPtrConstant(1));
}
@@ -1075,8 +1081,8 @@
// Merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
- return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0],
- ResultVals.size()).getNode();
+ return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
+ &ResultVals[0], ResultVals.size()).getNode();
}
@@ -1196,9 +1202,10 @@
/// function parameter.
static SDValue
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
- ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
+ ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
+ DebugLoc dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
- return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
+ return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
/*AlwaysInline=*/true, NULL, 0, NULL, 0);
}
@@ -1222,7 +1229,7 @@
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
if (Flags.isByVal())
return FIN;
- return DAG.getLoad(VA.getValVT(), Root, FIN,
+ return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
PseudoSourceValue::getFixedStack(FI), 0);
}
@@ -1230,6 +1237,7 @@
X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
+ DebugLoc dl = Op.getDebugLoc();
const Function* Fn = MF.getFunction();
if (Fn->hasExternalLinkage() &&
@@ -1298,29 +1306,29 @@
}
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
- SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
+ SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted to 32
// bits. Insert an assert[sz]ext to capture this, then truncate to the
// right size.
if (VA.getLocInfo() == CCValAssign::SExt)
- ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
+ ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
else if (VA.getLocInfo() == CCValAssign::ZExt)
- ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
+ ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
DAG.getValueType(VA.getValVT()));
if (VA.getLocInfo() != CCValAssign::Full)
- ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
+ ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
// Handle MMX values passed in GPRs.
if (Is64Bit && RegVT != VA.getLocVT()) {
if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
- ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
else if (RC == X86::VR128RegisterClass) {
- ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
- DAG.getConstant(0, MVT::i64));
- ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
+ ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
+ ArgValue, DAG.getConstant(0, MVT::i64));
+ ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
}
}
@@ -1342,8 +1350,8 @@
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
FuncInfo->setSRetReturnReg(Reg);
}
- SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
+ SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
+ Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
}
unsigned StackSize = CCInfo.getNextStackOffset();
@@ -1408,36 +1416,36 @@
// Store the integer parameter registers.
SmallVector<SDValue, 8> MemOps;
SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
- SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
+ SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
DAG.getIntPtrConstant(VarArgsGPOffset));
for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
X86::GR64RegisterClass);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
SDValue Store =
- DAG.getStore(Val.getValue(1), Val, FIN,
+ DAG.getStore(Val.getValue(1), dl, Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
MemOps.push_back(Store);
- FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
DAG.getIntPtrConstant(8));
}
// Now store the XMM (fp + vector) parameter registers.
- FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
DAG.getIntPtrConstant(VarArgsFPOffset));
for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
X86::VR128RegisterClass);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
SDValue Store =
- DAG.getStore(Val.getValue(1), Val, FIN,
+ DAG.getStore(Val.getValue(1), dl, Val, FIN,
PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
MemOps.push_back(Store);
- FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
DAG.getIntPtrConstant(16));
}
if (!MemOps.empty())
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
}
}
@@ -1465,7 +1473,7 @@
FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
// Return the new list of results.
- return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
}
@@ -1475,13 +1483,14 @@
const CCValAssign &VA,
SDValue Chain,
SDValue Arg, ISD::ArgFlagsTy Flags) {
+ DebugLoc dl = TheCall->getDebugLoc();
unsigned LocMemOffset = VA.getLocMemOffset();
SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
- PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
+ PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
if (Flags.isByVal()) {
- return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
+ return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
}
- return DAG.getStore(Chain, Arg, PtrOff,
+ return DAG.getStore(Chain, dl, Arg, PtrOff,
PseudoSourceValue::getStack(), LocMemOffset);
}
@@ -1493,7 +1502,8 @@
SDValue Chain,
bool IsTailCall,
bool Is64Bit,
- int FPDiff) {
+ int FPDiff,
+ DebugLoc dl) {
if (!IsTailCall || FPDiff==0) return Chain;
// Adjust the Return address stack slot.
@@ -1501,7 +1511,7 @@
OutRetAddr = getReturnAddressFrameIndex(DAG);
// Load the "old" Return address.
- OutRetAddr = DAG.getLoad(VT, Chain, OutRetAddr, NULL, 0);
+ OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
return SDValue(OutRetAddr.getNode(), 1);
}
@@ -1510,7 +1520,7 @@
static SDValue
EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
SDValue Chain, SDValue RetAddrFrIdx,
- bool Is64Bit, int FPDiff) {
+ bool Is64Bit, int FPDiff, DebugLoc dl) {
// Store the return address to the appropriate stack slot.
if (!FPDiff) return Chain;
// Calculate the new stack slot for the return address.
@@ -1519,7 +1529,7 @@
MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
- Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
+ Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
return Chain;
}
@@ -1535,6 +1545,7 @@
SDValue Callee = TheCall->getCallee();
bool Is64Bit = Subtarget->is64Bit();
bool IsStructRet = CallIsStructReturn(TheCall);
+ DebugLoc dl = TheCall->getDebugLoc();
assert(!(isVarArg && CC == CallingConv::Fast) &&
"Var args not supported with calling convention fastcc");
@@ -1567,7 +1578,7 @@
SDValue RetAddrFrIdx;
// Load return adress for tail calls.
Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
- FPDiff);
+ FPDiff, dl);
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
@@ -1586,13 +1597,13 @@
default: assert(0 && "Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
- Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::ZExt:
- Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::AExt:
- Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
break;
}
@@ -1606,17 +1617,17 @@
case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
case X86::R8: {
// Special case: passing MMX values in GPR registers.
- Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
break;
}
case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
// Special case: passing MMX values in XMM registers.
- Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
- Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
- Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
- DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
- getMOVLMask(2, DAG));
+ Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
+ Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
+ Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
+ DAG.getUNDEF(MVT::v2i64), Arg,
+ getMOVLMask(2, DAG, dl));
break;
}
}
@@ -1626,7 +1637,7 @@
if (!IsTailCall || (IsTailCall && isByVal)) {
assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
- StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
+ StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
Chain, Arg, Flags));
@@ -1635,7 +1646,7 @@
}
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
@@ -1645,16 +1656,18 @@
// tail call optimization the copies to registers are lowered later.
if (!IsTailCall)
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
- InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
// ELF / PIC requires GOT in the EBX register before function calls via PLT
// GOT pointer.
if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
- Chain = DAG.getCopyToReg(Chain, X86::EBX,
- DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
+ Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
+ DAG.getNode(X86ISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(),
+ getPointerTy()),
InFlag);
InFlag = Chain.getValue(1);
}
@@ -1693,7 +1706,7 @@
assert((Subtarget->hasSSE1() || !NumXMMRegs)
&& "SSE registers cannot be used when SSE is disabled");
- Chain = DAG.getCopyToReg(Chain, X86::AL,
+ Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
InFlag = Chain.getValue(1);
}
@@ -1722,35 +1735,36 @@
// Copy relative to framepointer.
SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
if (StackPtr.getNode() == 0)
- StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
- Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
+ StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
+ getPointerTy());
+ Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
- Flags, DAG));
+ Flags, DAG, dl));
} else {
// Store relative to framepointer.
MemOpChains2.push_back(
- DAG.getStore(Chain, Arg, FIN,
+ DAG.getStore(Chain, dl, Arg, FIN,
PseudoSourceValue::getFixedStack(FI), 0));
}
}
}
if (!MemOpChains2.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains2[0], MemOpChains2.size());
// Copy arguments to their registers.
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
- InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+ RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
InFlag =SDValue();
// Store the return address to the appropriate stack slot.
Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
- FPDiff);
+ FPDiff, dl);
}
// If the callee is a GlobalAddress node (quite common, every direct call is)
@@ -1767,7 +1781,7 @@
} else if (IsTailCall) {
unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
- Chain = DAG.getCopyToReg(Chain,
+ Chain = DAG.getCopyToReg(Chain, dl,
DAG.getRegister(Opc, getPointerTy()),
Callee,InFlag);
Callee = DAG.getRegister(Opc, getPointerTy());
@@ -1780,12 +1794,8 @@
SmallVector<SDValue, 8> Ops;
if (IsTailCall) {
- Ops.push_back(Chain);
- Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
- Ops.push_back(DAG.getIntPtrConstant(0, true));
- if (InFlag.getNode())
- Ops.push_back(InFlag);
- Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+ DAG.getIntPtrConstant(0, true), InFlag);
InFlag = Chain.getValue(1);
// Returns a chain & a flag for retval copy to use.
@@ -1821,13 +1831,13 @@
if (IsTailCall) {
assert(InFlag.getNode() &&
"Flag must be set. Depend on flag being set in LowerRET");
- Chain = DAG.getNode(X86ISD::TAILCALL,
+ Chain = DAG.getNode(X86ISD::TAILCALL, dl,
TheCall->getVTList(), &Ops[0], Ops.size());
return SDValue(Chain.getNode(), Op.getResNo());
}
- Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
+ Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node.
@@ -2715,11 +2725,12 @@
MVT EltVT = MaskVT.getVectorElementType();
unsigned NumElems = Mask.getNumOperands();
SmallVector<SDValue, 8> MaskVec;
+ DebugLoc dl = Op.getDebugLoc();
for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
- MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
+ MaskVec.push_back(DAG.getUNDEF(EltVT));
continue;
}
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
@@ -2731,14 +2742,14 @@
}
std::swap(V1, V2);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
}
/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
/// the two vector operands have swapped position.
static
-SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
+SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) {
MVT MaskVT = Mask.getValueType();
MVT EltVT = MaskVT.getVectorElementType();
unsigned NumElems = Mask.getNumOperands();
@@ -2746,7 +2757,7 @@
for (unsigned i = 0; i != NumElems; ++i) {
SDValue Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
- MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
+ MaskVec.push_back(DAG.getUNDEF(EltVT));
continue;
}
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
@@ -2756,7 +2767,7 @@
else
MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
}
- return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
}
@@ -2898,7 +2909,8 @@
/// getZeroVector - Returns a vector of specified type with all zero elements.
///
-static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
+static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
+ DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
// Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
@@ -2906,20 +2918,20 @@
SDValue Vec;
if (VT.getSizeInBits() == 64) { // MMX
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
} else if (HasSSE2) { // SSE2
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
} else { // SSE1
SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
- Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
}
- return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
/// getOnesVector - Returns a vector of specified type with all bits set.
///
-static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
+static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
// Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
@@ -2927,10 +2939,10 @@
SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
SDValue Vec;
if (VT.getSizeInBits() == 64) // MMX
- Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
else // SSE
- Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
- return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2955,14 +2967,15 @@
}
if (Changed)
- Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
+ Mask.getValueType(),
&MaskVec[0], MaskVec.size());
return Mask;
}
/// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
/// operation of specified width.
-static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
+static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
@@ -2970,12 +2983,14 @@
MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
MaskVec.push_back(DAG.getConstant(i, BaseVT));
- return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
/// of specified width.
-static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
+static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
+ DebugLoc dl) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
SmallVector<SDValue, 8> MaskVec;
@@ -2983,12 +2998,14 @@
MaskVec.push_back(DAG.getConstant(i, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
}
- return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
/// of specified width.
-static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
+static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG,
+ DebugLoc dl) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
unsigned Half = NumElems/2;
@@ -2997,14 +3014,15 @@
MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
}
- return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
/// element #0 of a vector with the specified index, leaving the rest of the
/// elements in place.
static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG, DebugLoc dl) {
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT BaseVT = MaskVT.getVectorElementType();
SmallVector<SDValue, 8> MaskVec;
@@ -3012,7 +3030,8 @@
MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
- return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
@@ -3025,6 +3044,7 @@
SDValue Mask = Op.getOperand(2);
unsigned MaskNumElems = Mask.getNumOperands();
unsigned NumElems = MaskNumElems;
+ DebugLoc dl = Op.getDebugLoc();
// Special handling of v4f32 -> v4i32.
if (VT != MVT::v4f32) {
// Find which element we want to splat.
@@ -3033,22 +3053,22 @@
// unpack elements to the correct location
while (NumElems > 4) {
if (EltNo < NumElems/2) {
- Mask = getUnpacklMask(MaskNumElems, DAG);
+ Mask = getUnpacklMask(MaskNumElems, DAG, dl);
} else {
- Mask = getUnpackhMask(MaskNumElems, DAG);
+ Mask = getUnpackhMask(MaskNumElems, DAG, dl);
EltNo -= NumElems/2;
}
- V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
+ V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, Mask);
NumElems >>= 1;
}
SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
}
- V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
- SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
- DAG.getNode(ISD::UNDEF, PVT), Mask);
- return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
+ V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
+ SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
+ DAG.getUNDEF(PVT), Mask);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
}
/// isVectorLoad - Returns true if the node is a vector load, a scalar
@@ -3074,21 +3094,23 @@
MVT VT = Op.getValueType();
if (VT == PVT)
return Op;
+ DebugLoc dl = Op.getDebugLoc();
unsigned NumElems = PVT.getVectorNumElements();
if (NumElems == 2) {
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
} else {
assert(NumElems == 4);
SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
- Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ Cst0, Cst1, Cst0, Cst1);
}
- V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
- SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
- DAG.getNode(ISD::UNDEF, PVT), Mask);
- return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
+ V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
+ SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
+ DAG.getUNDEF(PVT), Mask);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
}
/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
@@ -3098,9 +3120,10 @@
static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
bool isZero, bool HasSSE2,
SelectionDAG &DAG) {
+ DebugLoc dl = V2.getDebugLoc();
MVT VT = V2.getValueType();
SDValue V1 = isZero
- ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
+ ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT);
unsigned NumElems = V2.getValueType().getVectorNumElements();
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT EVT = MaskVT.getVectorElementType();
@@ -3110,9 +3133,9 @@
MaskVec.push_back(DAG.getConstant(NumElems, EVT));
else
MaskVec.push_back(DAG.getConstant(i, EVT));
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
}
/// getNumOfConsecutiveZeros - Return the number of elements in a result of
@@ -3187,15 +3210,16 @@
if (NumNonZero > 8)
return SDValue();
+ DebugLoc dl = Op.getDebugLoc();
SDValue V(0, 0);
bool First = true;
for (unsigned i = 0; i < 16; ++i) {
bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
if (ThisIsNonZero && First) {
if (NumZero)
- V = getZeroVector(MVT::v8i16, true, DAG);
+ V = getZeroVector(MVT::v8i16, true, DAG, dl);
else
- V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
+ V = DAG.getUNDEF(MVT::v8i16);
First = false;
}
@@ -3203,24 +3227,25 @@
SDValue ThisElt(0, 0), LastElt(0, 0);
bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
if (LastIsNonZero) {
- LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
+ LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
+ MVT::i16, Op.getOperand(i-1));
}
if (ThisIsNonZero) {
- ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
- ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
+ ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
+ ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
ThisElt, DAG.getConstant(8, MVT::i8));
if (LastIsNonZero)
- ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
+ ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
} else
ThisElt = LastElt;
if (ThisElt.getNode())
- V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
+ V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
DAG.getIntPtrConstant(i/2));
}
}
- return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
}
/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
@@ -3231,6 +3256,7 @@
if (NumNonZero > 4)
return SDValue();
+ DebugLoc dl = Op.getDebugLoc();
SDValue V(0, 0);
bool First = true;
for (unsigned i = 0; i < 8; ++i) {
@@ -3238,12 +3264,13 @@
if (isNonZero) {
if (First) {
if (NumZero)
- V = getZeroVector(MVT::v8i16, true, DAG);
+ V = getZeroVector(MVT::v8i16, true, DAG, dl);
else
- V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
+ V = DAG.getUNDEF(MVT::v8i16);
First = false;
}
- V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
+ V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
+ MVT::v8i16, V, Op.getOperand(i),
DAG.getIntPtrConstant(i));
}
}
@@ -3255,18 +3282,19 @@
///
static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
unsigned NumBits, SelectionDAG &DAG,
- const TargetLowering &TLI) {
+ const TargetLowering &TLI, DebugLoc dl) {
bool isMMX = VT.getSizeInBits() == 64;
MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
- SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
- return DAG.getNode(ISD::BIT_CONVERT, VT,
- DAG.getNode(Opc, ShVT, SrcOp,
+ SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ DAG.getNode(Opc, dl, ShVT, SrcOp,
DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
}
SDValue
X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// All zero's are handled with pxor, all one's are handled with pcmpeqd.
if (ISD::isBuildVectorAllZeros(Op.getNode())
|| ISD::isBuildVectorAllOnes(Op.getNode())) {
@@ -3277,8 +3305,8 @@
return Op;
if (ISD::isBuildVectorAllOnes(Op.getNode()))
- return getOnesVector(Op.getValueType(), DAG);
- return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
+ return getOnesVector(Op.getValueType(), DAG, dl);
+ return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
}
MVT VT = Op.getValueType();
@@ -3309,7 +3337,7 @@
if (NumNonZero == 0) {
// All undef vector. Return an UNDEF. All zero vectors were handled above.
- return DAG.getNode(ISD::UNDEF, VT);
+ return DAG.getUNDEF(VT);
}
// Special case for single non-zero, non-undef, element.
@@ -3331,8 +3359,8 @@
// Truncate the value (which may itself be a constant) to i32, and
// convert it to a vector with movd (S2V+shuffle to zero extend).
- Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
- Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
+ Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
+ Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
Item = getShuffleVectorZeroOrUndef(Item, 0, true,
Subtarget->hasSSE2(), DAG);
@@ -3340,12 +3368,12 @@
// a vector. If Idx != 0, swizzle it into place.
if (Idx != 0) {
SDValue Ops[] = {
- Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
- getSwapEltZeroMask(VecElts, Idx, DAG)
+ Item, DAG.getUNDEF(Item.getValueType()),
+ getSwapEltZeroMask(VecElts, Idx, DAG, dl)
};
- Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
+ Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3);
}
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
}
}
@@ -3357,7 +3385,7 @@
if (Idx == 0 &&
// Don't do this for i64 values on x86-32.
(EVT != MVT::i64 || Subtarget->is64Bit())) {
- Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
+ Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
// Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
Subtarget->hasSSE2(), DAG);
@@ -3368,8 +3396,9 @@
isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
unsigned NumBits = VT.getSizeInBits();
return getVShift(true, VT,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
- NumBits/2, DAG, *this);
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
+ VT, Op.getOperand(1)),
+ NumBits/2, DAG, *this, dl);
}
if (IsAllConstants) // Otherwise, it's better to do a constpool load.
@@ -3381,7 +3410,7 @@
// movd/movss) to move this into the low element, then shuffle it into
// place.
if (EVTBits == 32) {
- Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
+ Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
// Turn it into a shuffle of zero and zero-extended scalar to vector.
Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
@@ -3391,10 +3420,10 @@
SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i < NumElems; i++)
MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
- DAG.getNode(ISD::UNDEF, VT), Mask);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item,
+ DAG.getUNDEF(VT), Mask);
}
}
@@ -3412,7 +3441,7 @@
if (NumNonZero == 1) {
// One half is zero or undef.
unsigned Idx = CountTrailingZeros_32(NonZeros);
- SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
+ SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
Op.getOperand(Idx));
return getShuffleVectorZeroOrUndef(V2, Idx, true,
Subtarget->hasSSE2(), DAG);
@@ -3440,9 +3469,9 @@
for (unsigned i = 0; i < 4; ++i) {
bool isZero = !(NonZeros & (1 << i));
if (isZero)
- V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
+ V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
else
- V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
+ V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
}
for (unsigned i = 0; i < 2; ++i) {
@@ -3452,16 +3481,16 @@
V[i] = V[i*2]; // Must be a zero vector.
break;
case 1:
- V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
- getMOVLMask(NumElems, DAG));
+ V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2+1], V[i*2],
+ getMOVLMask(NumElems, DAG, dl));
break;
case 2:
- V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
- getMOVLMask(NumElems, DAG));
+ V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
+ getMOVLMask(NumElems, DAG, dl));
break;
case 3:
- V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
- getUnpacklMask(NumElems, DAG));
+ V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
+ getUnpacklMask(NumElems, DAG, dl));
break;
}
}
@@ -3481,9 +3510,9 @@
MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
else
MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
- SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size());
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask);
}
if (Values.size() > 2) {
@@ -3492,13 +3521,13 @@
// Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
// Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
- SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
+ SDValue UnpckMask = getUnpacklMask(NumElems, DAG, dl);
for (unsigned i = 0; i < NumElems; ++i)
- V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
+ V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
NumElems >>= 1;
while (NumElems != 0) {
for (unsigned i = 0; i < NumElems; ++i)
- V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
+ V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i], V[i + NumElems],
UnpckMask);
NumElems >>= 1;
}
@@ -3511,7 +3540,7 @@
static
SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
SDValue PermMask, SelectionDAG &DAG,
- TargetLowering &TLI) {
+ TargetLowering &TLI, DebugLoc dl) {
SDValue NewV;
MVT MaskVT = MVT::getIntVectorWithNumElements(8);
MVT MaskEVT = MaskVT.getVectorElementType();
@@ -3574,11 +3603,11 @@
else
MaskVec.push_back(DAG.getConstant(1, MVT::i32));
- SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
- NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
- NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
+ SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, &MaskVec[0],2);
+ NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), Mask);
+ NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
// Now sort high and low parts separately.
BitVector InOrder(8);
@@ -3608,8 +3637,10 @@
if (AnyOutOrder) {
for (unsigned i = 4; i != 8; ++i)
MaskVec.push_back(DAG.getConstant(i, MaskEVT));
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
- NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], 8);
+ NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
+ NewV, NewV, Mask);
}
}
@@ -3641,8 +3672,10 @@
}
if (AnyOutOrder) {
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
- NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MaskVT, &MaskVec[0], 8);
+ NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
+ NewV, NewV, Mask);
}
}
@@ -3655,11 +3688,11 @@
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
SDValue ExtOp = (EltIdx < 8)
- ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
+ ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
DAG.getConstant(EltIdx, PtrVT))
- : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
+ : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
DAG.getConstant(EltIdx - 8, PtrVT));
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
DAG.getConstant(i, PtrVT));
}
@@ -3705,7 +3738,7 @@
}
if (V2InOrder > V1InOrder) {
- PermMask = CommuteVectorShuffleMask(PermMask, DAG);
+ PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl);
std::swap(V1, V2);
std::swap(V1Elts, V2Elts);
std::swap(V1FromV1, V2FromV2);
@@ -3720,17 +3753,17 @@
for (unsigned i = 0; i < 8; ++i) {
SDValue Elt = V1Elts[i];
if (Elt.getOpcode() == ISD::UNDEF) {
- MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
+ MaskVec.push_back(DAG.getUNDEF(MaskEVT));
continue;
}
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (EltIdx >= 8)
- MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
+ MaskVec.push_back(DAG.getUNDEF(MaskEVT));
else
MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
}
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
- V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], 8);
+ V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, V1, V1, Mask);
}
NewV = V1;
@@ -3741,9 +3774,9 @@
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
if (EltIdx < 8)
continue;
- SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
+ SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
DAG.getConstant(EltIdx - 8, PtrVT));
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
DAG.getConstant(i, PtrVT));
}
return NewV;
@@ -3755,9 +3788,9 @@
if (Elt.getOpcode() == ISD::UNDEF)
continue;
unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
- SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
+ SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
DAG.getConstant(EltIdx, PtrVT));
- NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
+ NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
DAG.getConstant(i, PtrVT));
}
return NewV;
@@ -3773,7 +3806,7 @@
SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
MVT VT,
SDValue PermMask, SelectionDAG &DAG,
- TargetLowering &TLI) {
+ TargetLowering &TLI, DebugLoc dl) {
unsigned NumElems = PermMask.getNumOperands();
unsigned NewWidth = (NumElems == 4) ? 2 : 4;
MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
@@ -3808,15 +3841,15 @@
return SDValue();
}
if (StartIdx == ~0U)
- MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
+ MaskVec.push_back(DAG.getUNDEF(MaskEltVT));
else
MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
}
- V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
- V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
- return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
+ V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskVec[0], MaskVec.size()));
}
@@ -3824,7 +3857,7 @@
///
static SDValue getVZextMovL(MVT VT, MVT OpVT,
SDValue SrcOp, SelectionDAG &DAG,
- const X86Subtarget *Subtarget) {
+ const X86Subtarget *Subtarget, DebugLoc dl) {
if (VT == MVT::v2f64 || VT == MVT::v4f32) {
LoadSDNode *LD = NULL;
if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
@@ -3839,30 +3872,33 @@
SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
// PR2108
OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
- return DAG.getNode(ISD::BIT_CONVERT, VT,
- DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
+ OpVT,
SrcOp.getOperand(0)
.getOperand(0))));
}
}
}
- return DAG.getNode(ISD::BIT_CONVERT, VT,
- DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
- DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
+ DAG.getNode(ISD::BIT_CONVERT, dl,
+ OpVT, SrcOp)));
}
/// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
/// shuffles.
static SDValue
LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
- SDValue PermMask, MVT VT, SelectionDAG &DAG) {
+ SDValue PermMask, MVT VT, SelectionDAG &DAG,
+ DebugLoc dl) {
MVT MaskVT = PermMask.getValueType();
MVT MaskEVT = MaskVT.getVectorElementType();
SmallVector<std::pair<int, int>, 8> Locs;
Locs.resize(4);
- SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+ SmallVector<SDValue, 8> Mask1(4, DAG.getUNDEF(MaskEVT));
unsigned NumHi = 0;
unsigned NumLo = 0;
for (unsigned i = 0; i != 4; ++i) {
@@ -3890,11 +3926,11 @@
// implemented with two shuffles. First shuffle gather the elements.
// The second shuffle, which takes the first shuffle as both of its
// vector operands, put the elements into the right order.
- V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&Mask1[0], Mask1.size()));
- SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+ SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT));
for (unsigned i = 0; i != 4; ++i) {
if (Locs[i].first == -1)
continue;
@@ -3905,8 +3941,8 @@
}
}
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&Mask2[0], Mask2.size()));
} else if (NumLo == 3 || NumHi == 3) {
// Otherwise, we must have three elements from one vector, call it X, and
@@ -3918,7 +3954,7 @@
// from X.
if (NumHi == 3) {
// Normalize it so the 3 elements come from V1.
- PermMask = CommuteVectorShuffleMask(PermMask, DAG);
+ PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl);
std::swap(V1, V2);
}
@@ -3934,19 +3970,20 @@
}
Mask1[0] = PermMask.getOperand(HiIndex);
- Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
+ Mask1[1] = DAG.getUNDEF(MaskEVT);
Mask1[2] = PermMask.getOperand(HiIndex^1);
- Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
- V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
+ Mask1[3] = DAG.getUNDEF(MaskEVT);
+ V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4));
if (HiIndex >= 2) {
Mask1[0] = PermMask.getOperand(0);
Mask1[1] = PermMask.getOperand(1);
Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MaskVT, &Mask1[0], 4));
} else {
Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
@@ -3960,15 +3997,16 @@
Mask1[3] =
DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
MaskEVT);
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1,
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MaskVT, &Mask1[0], 4));
}
}
// Break it into (shuffle shuffle_hi, shuffle_lo).
Locs.clear();
- SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
- SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+ SmallVector<SDValue,8> LoMask(4, DAG.getUNDEF(MaskEVT));
+ SmallVector<SDValue,8> HiMask(4, DAG.getUNDEF(MaskEVT));
SmallVector<SDValue,8> *MaskPtr = &LoMask;
unsigned MaskIdx = 0;
unsigned LoIdx = 0;
@@ -3994,23 +4032,23 @@
}
}
- SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&LoMask[0], LoMask.size()));
- SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&HiMask[0], HiMask.size()));
SmallVector<SDValue, 8> MaskOps;
for (unsigned i = 0; i != 4; ++i) {
if (Locs[i].first == -1) {
- MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
+ MaskOps.push_back(DAG.getUNDEF(MaskEVT));
} else {
unsigned Idx = Locs[i].first * 4 + Locs[i].second;
MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
}
}
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
- DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&MaskOps[0], MaskOps.size()));
}
@@ -4020,6 +4058,7 @@
SDValue V2 = Op.getOperand(1);
SDValue PermMask = Op.getOperand(2);
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
unsigned NumElems = PermMask.getNumOperands();
bool isMMX = VT.getSizeInBits() == 64;
bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
@@ -4028,10 +4067,10 @@
bool V2IsSplat = false;
if (isUndefShuffle(Op.getNode()))
- return DAG.getNode(ISD::UNDEF, VT);
+ return DAG.getUNDEF(VT);
if (isZeroShuffle(Op.getNode()))
- return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
+ return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
if (isIdentityMask(PermMask.getNode()))
return V1;
@@ -4053,30 +4092,33 @@
// If the shuffle can be profitably rewritten as a narrower shuffle, then
// do it!
if (VT == MVT::v8i16 || VT == MVT::v16i8) {
- SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
+ SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG,
+ *this, dl);
if (NewOp.getNode())
- return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ LowerVECTOR_SHUFFLE(NewOp, DAG));
} else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
// FIXME: Figure out a cleaner way to do this.
// Try to make use of movq to zero out the top part.
if (ISD::isBuildVectorAllZeros(V2.getNode())) {
SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
- DAG, *this);
+ DAG, *this, dl);
if (NewOp.getNode()) {
SDValue NewV1 = NewOp.getOperand(0);
SDValue NewV2 = NewOp.getOperand(1);
SDValue NewMask = NewOp.getOperand(2);
if (isCommutedMOVL(NewMask.getNode(), true, false)) {
NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
- return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
+ return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget,
+ dl);
}
}
} else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
- DAG, *this);
+ DAG, *this, dl);
if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
- DAG, Subtarget);
+ DAG, Subtarget, dl);
}
}
@@ -4090,14 +4132,14 @@
// v_set0 + movlhps or movhlps, etc.
MVT EVT = VT.getVectorElementType();
ShAmt *= EVT.getSizeInBits();
- return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
+ return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
}
if (X86::isMOVLMask(PermMask.getNode())) {
if (V1IsUndef)
return V2;
if (ISD::isBuildVectorAllZeros(V1.getNode()))
- return getVZextMovL(VT, VT, V2, DAG, Subtarget);
+ return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
if (!isMMX)
return Op;
}
@@ -4117,7 +4159,7 @@
// No better options. Use a vshl / vsrl.
MVT EVT = VT.getVectorElementType();
ShAmt *= EVT.getSizeInBits();
- return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
+ return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
}
bool Commuted = false;
@@ -4142,9 +4184,9 @@
// V2 is a splat, so the mask may be malformed. That is, it may point
// to any V2 element. The instruction selectior won't like this. Get
// a corrected mask and commute to form a proper MOVS{S|D}.
- SDValue NewMask = getMOVLMask(NumElems, DAG);
+ SDValue NewMask = getMOVLMask(NumElems, DAG, dl);
if (NewMask.getNode() != PermMask.getNode())
- Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
+ Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
}
return Op;
}
@@ -4162,11 +4204,11 @@
SDValue NewMask = NormalizeMask(PermMask, DAG);
if (NewMask.getNode() != PermMask.getNode()) {
if (X86::isUNPCKLMask(NewMask.getNode(), true)) {
- SDValue NewMask = getUnpacklMask(NumElems, DAG);
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
+ SDValue NewMask = getUnpacklMask(NumElems, DAG, dl);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
} else if (X86::isUNPCKHMask(NewMask.getNode(), true)) {
- SDValue NewMask = getUnpackhMask(NumElems, DAG);
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
+ SDValue NewMask = getUnpackhMask(NumElems, DAG, dl);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
}
}
}
@@ -4190,8 +4232,8 @@
// possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
if (V2.getOpcode() != ISD::UNDEF)
- return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
- DAG.getNode(ISD::UNDEF, VT), PermMask);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1,
+ DAG.getUNDEF(VT), PermMask);
return Op;
}
@@ -4203,14 +4245,14 @@
MVT RVT = VT;
if (VT == MVT::v4f32) {
RVT = MVT::v4i32;
- Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
- DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
- DAG.getNode(ISD::UNDEF, RVT), PermMask);
+ Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT,
+ DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1),
+ DAG.getUNDEF(RVT), PermMask);
} else if (V2.getOpcode() != ISD::UNDEF)
- Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
- DAG.getNode(ISD::UNDEF, RVT), PermMask);
+ Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1,
+ DAG.getUNDEF(RVT), PermMask);
if (RVT != VT)
- Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op);
return Op;
}
@@ -4222,14 +4264,14 @@
// Handle v8i16 specifically since SSE can do byte extraction and insertion.
if (VT == MVT::v8i16) {
- SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
+ SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this, dl);
if (NewOp.getNode())
return NewOp;
}
// Handle all 4 wide cases with a number of shuffles except for MMX.
if (NumElems == 4 && !isMMX)
- return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
+ return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG, dl);
return SDValue();
}
@@ -4238,26 +4280,28 @@
X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
SelectionDAG &DAG) {
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
if (VT.getSizeInBits() == 8) {
- SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
DAG.getValueType(VT));
- return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+ return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
} else if (VT.getSizeInBits() == 16) {
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
// If Idx is 0, it's cheaper to do a move instead of a pextrw.
if (Idx == 0)
- return DAG.getNode(ISD::TRUNCATE, MVT::i16,
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl,
+ MVT::v4i32,
Op.getOperand(0)),
Op.getOperand(1)));
- SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
DAG.getValueType(VT));
- return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+ return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
} else if (VT == MVT::f32) {
// EXTRACTPS outputs to a GPR32 register which will require a movd to copy
// the result back to FR32 register. It's only worth matching if the
@@ -4273,10 +4317,11 @@
(User->getOpcode() != ISD::BIT_CONVERT ||
User->getValueType(0) != MVT::i32))
return SDValue();
- SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
- Op.getOperand(1));
- return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
+ SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
+ Op.getOperand(0)),
+ Op.getOperand(1));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
} else if (VT == MVT::i32) {
// ExtractPS works with constant index.
if (isa<ConstantSDNode>(Op.getOperand(1)))
@@ -4298,22 +4343,24 @@
}
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
// TODO: handle v16i8.
if (VT.getSizeInBits() == 16) {
SDValue Vec = Op.getOperand(0);
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Idx == 0)
- return DAG.getNode(ISD::TRUNCATE, MVT::i16,
- DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
+ return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl,
+ MVT::v4i32, Vec),
Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result.
MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
- SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
+ SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
Op.getOperand(0), Op.getOperand(1));
- SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
+ SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
DAG.getValueType(VT));
- return DAG.getNode(ISD::TRUNCATE, VT, Assert);
+ return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
} else if (VT.getSizeInBits() == 32) {
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
if (Idx == 0)
@@ -4324,17 +4371,17 @@
IdxVec.
push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
IdxVec.
- push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
+ push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
IdxVec.
- push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
+ push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
IdxVec.
- push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&IdxVec[0], IdxVec.size());
SDValue Vec = Op.getOperand(0);
- Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
- Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
+ Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
+ Vec, DAG.getUNDEF(Vec.getValueType()), Mask);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
DAG.getIntPtrConstant(0));
} else if (VT.getSizeInBits() == 64) {
// FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
@@ -4351,13 +4398,14 @@
SmallVector<SDValue, 8> IdxVec;
IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
IdxVec.
- push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
- SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&IdxVec[0], IdxVec.size());
SDValue Vec = Op.getOperand(0);
- Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
- Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
+ Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
+ Vec, DAG.getUNDEF(Vec.getValueType()),
+ Mask);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
DAG.getIntPtrConstant(0));
}
@@ -4368,6 +4416,7 @@
X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
MVT VT = Op.getValueType();
MVT EVT = VT.getVectorElementType();
+ DebugLoc dl = Op.getDebugLoc();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
@@ -4380,10 +4429,10 @@
// Transform it so it match pinsr{b,w} which expects a GR32 as its second
// argument.
if (N1.getValueType() != MVT::i32)
- N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
+ N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
- return DAG.getNode(Opc, VT, N0, N1, N2);
+ return DAG.getNode(Opc, dl, VT, N0, N1, N2);
} else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
// Bits [7:6] of the constant are the source select. This will always be
// zero here. The DAG Combiner may combine an extract_elt index into these
@@ -4394,7 +4443,7 @@
// Bits [3:0] of the constant are the zero mask. The DAG Combiner may
// combine either bitwise AND or insert of float 0.0 to set these bits.
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
- return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
+ return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
} else if (EVT == MVT::i32) {
// InsertPS works with constant index.
if (isa<ConstantSDNode>(N2))
@@ -4414,6 +4463,7 @@
if (EVT == MVT::i8)
return SDValue();
+ DebugLoc dl = Op.getDebugLoc();
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
@@ -4422,23 +4472,24 @@
// Transform it so it match pinsrw which expects a 16-bit value in a GR32
// as its second argument.
if (N1.getValueType() != MVT::i32)
- N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
+ N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
- return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
+ return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
}
return SDValue();
}
SDValue
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
if (Op.getValueType() == MVT::v2f32)
- return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
- DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
+ return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
Op.getOperand(0))));
- SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
+ SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
MVT VT = MVT::v2i32;
switch (Op.getValueType().getSimpleVT()) {
default: break;
@@ -4447,8 +4498,8 @@
VT = MVT::v4i32;
break;
}
- return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
- DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
}
// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
@@ -4460,15 +4511,19 @@
SDValue
X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
+ // FIXME there isn't really any debug info here, should come from the parent
+ DebugLoc dl = CP->getDebugLoc();
SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
getPointerTy(),
CP->getAlignment());
- Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->isPICStyleRIPRel()) {
- Result = DAG.getNode(ISD::ADD, getPointerTy(),
- DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
+ Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ DAG.getNode(X86ISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(),
+ getPointerTy()),
Result);
}
@@ -4476,7 +4531,7 @@
}
SDValue
-X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
+X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
int64_t Offset,
SelectionDAG &DAG) const {
bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
@@ -4491,12 +4546,12 @@
Offset = 0;
} else
Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
- Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (IsPic && !Subtarget->isPICStyleRIPRel()) {
- Result = DAG.getNode(ISD::ADD, getPointerTy(),
- DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
+ Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
Result);
}
@@ -4506,13 +4561,13 @@
// the GV offset field. Platform check is inside GVRequiresExtraLoad() call
// The same applies for external symbols during PIC codegen
if (ExtraLoadRequired)
- Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
+ Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
PseudoSourceValue::getGOT(), 0);
// If there was a non-zero offset that we didn't fold, create an explicit
// addition for it.
if (Offset != 0)
- Result = DAG.getNode(ISD::ADD, getPointerTy(), Result,
+ Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
DAG.getConstant(Offset, getPointerTy()));
return Result;
@@ -4522,7 +4577,7 @@
X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
- return LowerGlobalAddress(GV, Offset, DAG);
+ return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
@@ -4530,8 +4585,10 @@
LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
const MVT PtrVT) {
SDValue InFlag;
- SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
+ DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
+ SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
DAG.getNode(X86ISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(),
PtrVT), InFlag);
InFlag = Chain.getValue(1);
@@ -4541,13 +4598,13 @@
GA->getValueType(0),
GA->getOffset());
SDValue Ops[] = { Chain, TGA, InFlag };
- SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
+ SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
InFlag = Result.getValue(2);
Chain = Result.getValue(1);
// call ___tls_get_addr. This function receives its argument in
// the register EAX.
- Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Result, InFlag);
InFlag = Chain.getValue(1);
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
@@ -4557,10 +4614,10 @@
DAG.getRegister(X86::EAX, PtrVT),
DAG.getRegister(X86::EBX, PtrVT),
InFlag };
- Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
+ Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 5);
InFlag = Chain.getValue(1);
- return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
+ return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag);
}
// Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
@@ -4568,6 +4625,7 @@
LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
const MVT PtrVT) {
SDValue InFlag, Chain;
+ DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
// emit leaq symbol at TLSGD(%rip), %rdi
SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
@@ -4575,13 +4633,13 @@
GA->getValueType(0),
GA->getOffset());
SDValue Ops[] = { DAG.getEntryNode(), TGA};
- SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
+ SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
Chain = Result.getValue(1);
InFlag = Result.getValue(2);
// call __tls_get_addr. This function receives its argument in
// the register RDI.
- Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, X86::RDI, Result, InFlag);
InFlag = Chain.getValue(1);
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
@@ -4590,32 +4648,34 @@
PtrVT),
DAG.getRegister(X86::RDI, PtrVT),
InFlag };
- Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
+ Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 4);
InFlag = Chain.getValue(1);
- return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
+ return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag);
}
// Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
// "local exec" model.
static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
const MVT PtrVT) {
+ DebugLoc dl = GA->getDebugLoc();
// Get the Thread Pointer
- SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
+ SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
+ DebugLoc::getUnknownLoc(), PtrVT);
// emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
// exec)
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
GA->getValueType(0),
GA->getOffset());
- SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
+ SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
- Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
+ Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
PseudoSourceValue::getGOT(), 0);
// The address of the thread local variable is the add of the thread
// pointer with the offset of the variable.
- return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
+ return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
}
SDValue
@@ -4639,14 +4699,18 @@
SDValue
X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
+ // FIXME there isn't really any debug info here
+ DebugLoc dl = Op.getDebugLoc();
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
- Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->isPICStyleRIPRel()) {
- Result = DAG.getNode(ISD::ADD, getPointerTy(),
- DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
+ Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ DAG.getNode(X86ISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(),
+ getPointerTy()),
Result);
}
@@ -4655,13 +4719,17 @@
SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
+ // FIXME there isn't really any debug into here
+ DebugLoc dl = JT->getDebugLoc();
SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
- Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
// With PIC, the address is actually $g + Offset.
if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
!Subtarget->isPICStyleRIPRel()) {
- Result = DAG.getNode(ISD::ADD, getPointerTy(),
- DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
+ Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ DAG.getNode(X86ISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(),
+ getPointerTy()),
Result);
}
@@ -4674,26 +4742,28 @@
assert(Op.getNumOperands() == 3 && "Not a double-shift!");
MVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits();
+ DebugLoc dl = Op.getDebugLoc();
bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
SDValue Tmp1 = isSRA ?
- DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
+ DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
+ DAG.getConstant(VTBits - 1, MVT::i8)) :
DAG.getConstant(0, VT);
SDValue Tmp2, Tmp3;
if (Op.getOpcode() == ISD::SHL_PARTS) {
- Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
- Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
+ Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
+ Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
} else {
- Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
- Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
+ Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
+ Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
}
- SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
+ SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
DAG.getConstant(VTBits, MVT::i8));
- SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
+ SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
AndNode, DAG.getConstant(0, MVT::i8));
SDValue Hi, Lo;
@@ -4702,15 +4772,15 @@
SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
if (Op.getOpcode() == ISD::SHL_PARTS) {
- Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
- Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
+ Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
+ Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
} else {
- Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
- Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
+ Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
+ Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
}
SDValue Ops[2] = { Lo, Hi };
- return DAG.getMergeValues(Ops, 2);
+ return DAG.getMergeValues(Ops, 2, dl);
}
SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
@@ -4725,11 +4795,12 @@
Subtarget->is64Bit())
return SDValue();
+ DebugLoc dl = Op.getDebugLoc();
unsigned Size = SrcVT.getSizeInBits()/8;
MachineFunction &MF = DAG.getMachineFunction();
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
+ SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0);
@@ -4744,7 +4815,7 @@
Ops.push_back(Chain);
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(SrcVT));
- SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
+ SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
Tys, &Ops[0], Ops.size());
if (useSSE) {
@@ -4764,8 +4835,8 @@
Ops.push_back(StackSlot);
Ops.push_back(DAG.getValueType(Op.getValueType()));
Ops.push_back(InFlag);
- Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
- Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
+ Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
+ Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0);
}
@@ -4808,6 +4879,8 @@
}
*/
+ DebugLoc dl = Op.getDebugLoc();
+
// Build some magic constants.
std::vector<Constant*> CV0;
CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
@@ -4828,82 +4901,83 @@
MaskVec.push_back(DAG.getConstant(4, MVT::i32));
MaskVec.push_back(DAG.getConstant(1, MVT::i32));
MaskVec.push_back(DAG.getConstant(5, MVT::i32));
- SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0],
- MaskVec.size());
+ SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ &MaskVec[0], MaskVec.size());
SmallVector<SDValue, 4> MaskVec2;
MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
- SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0],
- MaskVec2.size());
+ SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
+ &MaskVec2[0], MaskVec2.size());
- SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(1)));
- SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(0)));
- SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
+ SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
XR1, XR2, UnpcklMask);
- SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0,
+ SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
+ SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
Unpck1, CLod0, UnpcklMask);
- SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2);
- SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1,
+ SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
+ SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
// Add the halves; easiest way is to swap them into another reg first.
- SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64,
+ SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2f64,
Sub, Sub, ShufMask);
- SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub);
- return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add,
+ SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
DAG.getIntPtrConstant(0));
}
// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// FP constant to bias correct the final result.
SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
MVT::f64);
// Load the 32-bit value into an XMM register.
- SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
- DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
+ DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Op.getOperand(0),
DAG.getIntPtrConstant(0)));
- Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Load),
+ Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
DAG.getIntPtrConstant(0));
// Or the load with the bias.
- SDValue Or = DAG.getNode(ISD::OR, MVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
- DAG.getNode(ISD::SCALAR_TO_VECTOR,
+ SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
MVT::v2f64, Load)),
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
- DAG.getNode(ISD::SCALAR_TO_VECTOR,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
MVT::v2f64, Bias)));
- Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Or),
+ Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
DAG.getIntPtrConstant(0));
// Subtract the bias.
- SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Or, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
// Handle final rounding.
MVT DestVT = Op.getValueType();
if (DestVT.bitsLT(MVT::f64)) {
- return DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
+ return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
} else if (DestVT.bitsGT(MVT::f64)) {
- return DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
+ return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
// Handle final rounding.
@@ -4912,12 +4986,13 @@
SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
SDValue N0 = Op.getOperand(0);
+ DebugLoc dl = Op.getDebugLoc();
// Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
// optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
// the optimization here.
if (DAG.SignBitIsZero(N0))
- return DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), N0);
+ return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
MVT SrcVT = N0.getValueType();
if (SrcVT == MVT::i64) {
@@ -4936,6 +5011,7 @@
std::pair<SDValue,SDValue> X86TargetLowering::
FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
Op.getValueType().getSimpleVT() >= MVT::i16 &&
"Unknown FP_TO_SINT to lower!");
@@ -4967,13 +5043,13 @@
SDValue Value = Op.getOperand(0);
if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
- Chain = DAG.getStore(Chain, Value, StackSlot,
+ Chain = DAG.getStore(Chain, dl, Value, StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0);
SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
SDValue Ops[] = {
Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
};
- Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
+ Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
Chain = Value.getValue(1);
SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
@@ -4981,7 +5057,7 @@
// Build the FP_TO_INT*_IN_MEM
SDValue Ops[] = { Chain, Value, StackSlot };
- SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
+ SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
return std::make_pair(FIST, StackSlot);
}
@@ -4992,10 +5068,12 @@
if (FIST.getNode() == 0) return SDValue();
// Load the result.
- return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
+ return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
+ FIST, StackSlot, NULL, 0);
}
SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
MVT EltVT = VT;
if (VT.isVector())
@@ -5014,13 +5092,14 @@
}
Constant *C = ConstantVector::get(CV);
SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
+ return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
}
SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
MVT EltVT = VT;
unsigned EltNum = 1;
@@ -5042,33 +5121,35 @@
}
Constant *C = ConstantVector::get(CV);
SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
if (VT.isVector()) {
- return DAG.getNode(ISD::BIT_CONVERT, VT,
- DAG.getNode(ISD::XOR, MVT::v2i64,
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
- DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ DAG.getNode(ISD::XOR, dl, MVT::v2i64,
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
+ Op.getOperand(0)),
+ DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
} else {
- return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
+ return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
}
}
SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
+ DebugLoc dl = Op.getDebugLoc();
MVT VT = Op.getValueType();
MVT SrcVT = Op1.getValueType();
// If second operand is smaller, extend it first.
if (SrcVT.bitsLT(VT)) {
- Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
+ Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
SrcVT = VT;
}
// And if it is bigger, shrink it first.
if (SrcVT.bitsGT(VT)) {
- Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
+ Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
SrcVT = VT;
}
@@ -5088,19 +5169,19 @@
}
Constant *C = ConstantVector::get(CV);
SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
+ SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
+ SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
// Shift sign bit right or left if the two operands have different types.
if (SrcVT.bitsGT(VT)) {
// Op0 is MVT::f32, Op1 is MVT::f64.
- SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
- SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
+ SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
+ SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
DAG.getConstant(32, MVT::i32));
- SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
- SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
+ SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
+ SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
DAG.getIntPtrConstant(0));
}
@@ -5117,19 +5198,20 @@
}
C = ConstantVector::get(CV);
CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
- SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
+ SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, 16);
- SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
+ SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
// Or the value with the sign bit.
- return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
+ return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
}
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
+ DebugLoc dl = Op.getDebugLoc();
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
// Lower (X & (1 << N)) == 0 to BT(X, N).
@@ -5170,16 +5252,16 @@
// that doing a bittest on the i16 value is ok. We extend to i32 because
// the encoding for the i16 version is larger than the i32 version.
if (LHS.getValueType() == MVT::i8)
- LHS = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, LHS);
+ LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
// If the operand types disagree, extend the shift amount to match. Since
// BT ignores high bits (like shifts) we can use anyextend.
if (LHS.getValueType() != RHS.getValueType())
- RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
+ RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
- SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
+ SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
- return DAG.getNode(X86ISD::SETCC, MVT::i8,
+ return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
DAG.getConstant(Cond, MVT::i8), BT);
}
}
@@ -5187,8 +5269,8 @@
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
- SDValue Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
- return DAG.getNode(X86ISD::SETCC, MVT::i8,
+ SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
+ return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
DAG.getConstant(X86CC, MVT::i8), Cond);
}
@@ -5200,6 +5282,7 @@
MVT VT = Op.getValueType();
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
+ DebugLoc dl = Op.getDebugLoc();
if (isFP) {
unsigned SSECC = 8;
@@ -5236,20 +5319,20 @@
if (SSECC == 8) {
if (SetCCOpcode == ISD::SETUEQ) {
SDValue UNORD, EQ;
- UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
- EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
- return DAG.getNode(ISD::OR, VT, UNORD, EQ);
+ UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
+ EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
+ return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
}
else if (SetCCOpcode == ISD::SETONE) {
SDValue ORD, NEQ;
- ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
- NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
- return DAG.getNode(ISD::AND, VT, ORD, NEQ);
+ ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
+ NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
+ return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
}
assert(0 && "Illegal FP comparison");
}
// Handle all other FP comparisons here.
- return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
+ return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
}
// We are handling one of the integer comparisons here. Since SSE only has
@@ -5289,17 +5372,17 @@
SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
EltVT);
std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
- SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
+ SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
SignBits.size());
- Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
- Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
+ Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
+ Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
}
- SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
+ SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
// If the logical-not of the result is required, perform that now.
if (Invert)
- Result = DAG.getNOT(Op.getDebugLoc(), Result, VT);
+ Result = DAG.getNOT(dl, Result, VT);
return Result;
}
@@ -5312,6 +5395,7 @@
SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
bool addTest = true;
SDValue Cond = Op.getOperand(0);
+ DebugLoc dl = Op.getDebugLoc();
SDValue CC;
if (Cond.getOpcode() == ISD::SETCC)
@@ -5339,7 +5423,8 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
+ Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
+ DAG.getConstant(0, MVT::i8));
}
const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
@@ -5351,7 +5436,7 @@
Ops.push_back(Op.getOperand(1));
Ops.push_back(CC);
Ops.push_back(Cond);
- return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
+ return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size());
}
// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
@@ -5385,6 +5470,7 @@
SDValue Chain = Op.getOperand(0);
SDValue Cond = Op.getOperand(1);
SDValue Dest = Op.getOperand(2);
+ DebugLoc dl = Op.getDebugLoc();
SDValue CC;
if (Cond.getOpcode() == ISD::SETCC)
@@ -5433,7 +5519,7 @@
if (Cmp == Cond.getOperand(1).getOperand(1) &&
isX86LogicalCmp(Opc)) {
CC = Cond.getOperand(0).getOperand(0);
- Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
+ Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Chain, Dest, CC, Cmp);
CC = Cond.getOperand(1).getOperand(0);
Cond = Cmp;
@@ -5463,7 +5549,7 @@
assert(NewBR == User);
Dest = FalseBB;
- Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
+ Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Chain, Dest, CC, Cmp);
X86::CondCode CCode =
(X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
@@ -5489,9 +5575,10 @@
if (addTest) {
CC = DAG.getConstant(X86::COND_NE, MVT::i8);
- Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
+ Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
+ DAG.getConstant(0, MVT::i8));
}
- return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
+ return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
Chain, Dest, CC, Cond);
}
@@ -5506,6 +5593,7 @@
SelectionDAG &DAG) {
assert(Subtarget->isTargetCygMing() &&
"This should be used only on Cygwin/Mingw targets");
+ DebugLoc dl = Op.getDebugLoc();
// Get the inputs.
SDValue Chain = Op.getOperand(0);
@@ -5519,7 +5607,7 @@
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
- Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
Flag = Chain.getValue(1);
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
@@ -5528,7 +5616,7 @@
DAG.getRegister(X86::EAX, IntPtr),
DAG.getRegister(X86StackPtr, SPTy),
Flag };
- Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
+ Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
Flag = Chain.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain,
@@ -5536,14 +5624,14 @@
DAG.getIntPtrConstant(0, true),
Flag);
- Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
+ Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
SDValue Ops1[2] = { Chain.getValue(0), Chain };
- return DAG.getMergeValues(Ops1, 2);
+ return DAG.getMergeValues(Ops1, 2, dl);
}
SDValue
-X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
+X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
@@ -5574,12 +5662,10 @@
Args.push_back(Entry);
Entry.Node = Size;
Args.push_back(Entry);
- // FIXME provide DebugLoc info
std::pair<SDValue,SDValue> CallResult =
LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
CallingConv::C, false,
- DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG,
- DebugLoc::getUnknownLoc());
+ DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
return CallResult.second;
}
@@ -5629,20 +5715,22 @@
BytesLeft = SizeVal % UBytes;
}
- Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
+ Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
InFlag);
InFlag = Chain.getValue(1);
} else {
AVT = MVT::i8;
Count = DAG.getIntPtrConstant(SizeVal);
- Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
+ Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
InFlag = Chain.getValue(1);
}
- Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
+ X86::ECX,
Count, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
+ X86::EDI,
Dst, InFlag);
InFlag = Chain.getValue(1);
@@ -5651,15 +5739,16 @@
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
Ops.push_back(InFlag);
- Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
+ Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
if (TwoRepStos) {
InFlag = Chain.getValue(1);
Count = Size;
MVT CVT = Count.getValueType();
- SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
+ SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
- Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
+ Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
+ X86::ECX,
Left, InFlag);
InFlag = Chain.getValue(1);
Tys = DAG.getVTList(MVT::Other, MVT::Flag);
@@ -5667,15 +5756,15 @@
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(MVT::i8));
Ops.push_back(InFlag);
- Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
+ Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
} else if (BytesLeft) {
// Handle the last 1 - 7 bytes.
unsigned Offset = SizeVal - BytesLeft;
MVT AddrVT = Dst.getValueType();
MVT SizeVT = Size.getValueType();
- Chain = DAG.getMemset(Chain,
- DAG.getNode(ISD::ADD, AddrVT, Dst,
+ Chain = DAG.getMemset(Chain, dl,
+ DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
DAG.getConstant(Offset, AddrVT)),
Src,
DAG.getConstant(BytesLeft, SizeVT),
@@ -5687,7 +5776,7 @@
}
SDValue
-X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
+X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
bool AlwaysInline,
@@ -5717,13 +5806,16 @@
unsigned BytesLeft = SizeVal % UBytes;
SDValue InFlag(0, 0);
- Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
+ X86::ECX,
Count, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
+ X86::EDI,
Dst, InFlag);
InFlag = Chain.getValue(1);
- Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
+ Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
+ X86::ESI,
Src, InFlag);
InFlag = Chain.getValue(1);
@@ -5732,7 +5824,7 @@
Ops.push_back(Chain);
Ops.push_back(DAG.getValueType(AVT));
Ops.push_back(InFlag);
- SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
+ SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
SmallVector<SDValue, 4> Results;
Results.push_back(RepMovs);
@@ -5742,10 +5834,10 @@
MVT DstVT = Dst.getValueType();
MVT SrcVT = Src.getValueType();
MVT SizeVT = Size.getValueType();
- Results.push_back(DAG.getMemcpy(Chain,
- DAG.getNode(ISD::ADD, DstVT, Dst,
+ Results.push_back(DAG.getMemcpy(Chain, dl,
+ DAG.getNode(ISD::ADD, dl, DstVT, Dst,
DAG.getConstant(Offset, DstVT)),
- DAG.getNode(ISD::ADD, SrcVT, Src,
+ DAG.getNode(ISD::ADD, dl, SrcVT, Src,
DAG.getConstant(Offset, SrcVT)),
DAG.getConstant(BytesLeft, SizeVT),
Align, AlwaysInline,
@@ -5753,17 +5845,19 @@
SrcSV, SrcSVOff + Offset));
}
- return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &Results[0], Results.size());
}
SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
+ DebugLoc dl = Op.getDebugLoc();
if (!Subtarget->is64Bit()) {
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
- return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
+ return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
}
// __va_list_tag:
@@ -5774,30 +5868,34 @@
SmallVector<SDValue, 8> MemOps;
SDValue FIN = Op.getOperand(1);
// Store gp_offset
- SDValue Store = DAG.getStore(Op.getOperand(0),
+ SDValue Store = DAG.getStore(Op.getOperand(0), dl,
DAG.getConstant(VarArgsGPOffset, MVT::i32),
FIN, SV, 0);
MemOps.push_back(Store);
// Store fp_offset
- FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
- Store = DAG.getStore(Op.getOperand(0),
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ FIN, DAG.getIntPtrConstant(4));
+ Store = DAG.getStore(Op.getOperand(0), dl,
DAG.getConstant(VarArgsFPOffset, MVT::i32),
FIN, SV, 0);
MemOps.push_back(Store);
// Store ptr to overflow_arg_area
- FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ FIN, DAG.getIntPtrConstant(4));
SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
- Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
+ Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
MemOps.push_back(Store);
// Store ptr to reg_save_area.
- FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
+ FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ FIN, DAG.getIntPtrConstant(8));
SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
- Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
+ Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
MemOps.push_back(Store);
- return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &MemOps[0], MemOps.size());
}
SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
@@ -5820,14 +5918,16 @@
SDValue SrcPtr = Op.getOperand(2);
const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
+ DebugLoc dl = Op.getDebugLoc();
- return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
+ return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
DAG.getIntPtrConstant(24), 8, false,
DstSV, 0, SrcSV, 0);
}
SDValue
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
@@ -5925,10 +6025,10 @@
SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);
unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
- SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
- SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
+ SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
+ SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
DAG.getConstant(X86CC, MVT::i8), Cond);
- return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
+ return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
}
// Fix vector shift instructions where the last operand is a non-immediate
@@ -6013,9 +6113,9 @@
}
}
MVT VT = Op.getValueType();
- ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
- DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(NewIntNo, MVT::i32),
Op.getOperand(1), ShAmt);
}
@@ -6024,31 +6124,35 @@
SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+ DebugLoc dl = Op.getDebugLoc();
if (Depth > 0) {
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
SDValue Offset =
DAG.getConstant(TD->getPointerSize(),
Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
- return DAG.getLoad(getPointerTy(), DAG.getEntryNode(),
- DAG.getNode(ISD::ADD, getPointerTy(), FrameAddr, Offset),
+ return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
+ DAG.getNode(ISD::ADD, dl, getPointerTy(),
+ FrameAddr, Offset),
NULL, 0);
}
// Just load the return address.
SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
- return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
+ return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
+ RetAddrFI, NULL, 0);
}
SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true);
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
- SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
+ SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
while (Depth--)
- FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
+ FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
return FrameAddr;
}
@@ -6063,19 +6167,20 @@
SDValue Chain = Op.getOperand(0);
SDValue Offset = Op.getOperand(1);
SDValue Handler = Op.getOperand(2);
+ DebugLoc dl = Op.getDebugLoc();
SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
getPointerTy());
unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
- SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
+ SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
DAG.getIntPtrConstant(-TD->getPointerSize()));
- StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
- Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
- Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
+ StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
+ Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
+ Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
MF.getRegInfo().addLiveOut(StoreAddrReg);
- return DAG.getNode(X86ISD::EH_RETURN,
+ return DAG.getNode(X86ISD::EH_RETURN, dl,
MVT::Other,
Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
}
@@ -6086,6 +6191,7 @@
SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
+ DebugLoc dl = Op.getDebugLoc();
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
@@ -6108,36 +6214,41 @@
// Load the pointer to the nested function into R11.
unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
SDValue Addr = Trmp;
- OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
- TrmpAddr, 0);
+ OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
+ Addr, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
- OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(2, MVT::i64));
+ OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
// Load the 'nest' parameter value into R10.
// R10 is specified in X86CallingConv.td
OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
- Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
- OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
- TrmpAddr, 10);
-
- Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
- OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(10, MVT::i64));
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
+ Addr, TrmpAddr, 10);
+
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(12, MVT::i64));
+ OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
// Jump to the nested function.
OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
- Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
- OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
- TrmpAddr, 20);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(20, MVT::i64));
+ OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
+ Addr, TrmpAddr, 20);
unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
- Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
- OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(22, MVT::i64));
+ OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
TrmpAddr, 22);
SDValue Ops[] =
- { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
- return DAG.getMergeValues(Ops, 2);
+ { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
+ return DAG.getMergeValues(Ops, 2, dl);
} else {
const Function *Func =
cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
@@ -6185,28 +6296,33 @@
SDValue OutChains[4];
SDValue Addr, Disp;
- Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
- Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(10, MVT::i32));
+ Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
- OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
+ OutChains[0] = DAG.getStore(Root, dl,
+ DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Trmp, TrmpAddr, 0);
- Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
- OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(1, MVT::i32));
+ OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
- Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
- OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(5, MVT::i32));
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
TrmpAddr, 5, false, 1);
- Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
- OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
+ DAG.getConstant(6, MVT::i32));
+ OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
SDValue Ops[] =
- { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
- return DAG.getMergeValues(Ops, 2);
+ { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
+ return DAG.getMergeValues(Ops, 2, dl);
}
}
@@ -6235,56 +6351,58 @@
const TargetFrameInfo &TFI = *TM.getFrameInfo();
unsigned StackAlignment = TFI.getStackAlignment();
MVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
// Save FP Control Word to stack slot
int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
- SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
+ SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
DAG.getEntryNode(), StackSlot);
// Load FP Control Word from stack slot
- SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
+ SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
// Transform as necessary
SDValue CWD1 =
- DAG.getNode(ISD::SRL, MVT::i16,
- DAG.getNode(ISD::AND, MVT::i16,
+ DAG.getNode(ISD::SRL, dl, MVT::i16,
+ DAG.getNode(ISD::AND, dl, MVT::i16,
CWD, DAG.getConstant(0x800, MVT::i16)),
DAG.getConstant(11, MVT::i8));
SDValue CWD2 =
- DAG.getNode(ISD::SRL, MVT::i16,
- DAG.getNode(ISD::AND, MVT::i16,
+ DAG.getNode(ISD::SRL, dl, MVT::i16,
+ DAG.getNode(ISD::AND, dl, MVT::i16,
CWD, DAG.getConstant(0x400, MVT::i16)),
DAG.getConstant(9, MVT::i8));
SDValue RetVal =
- DAG.getNode(ISD::AND, MVT::i16,
- DAG.getNode(ISD::ADD, MVT::i16,
- DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
+ DAG.getNode(ISD::AND, dl, MVT::i16,
+ DAG.getNode(ISD::ADD, dl, MVT::i16,
+ DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
DAG.getConstant(1, MVT::i16)),
DAG.getConstant(3, MVT::i16));
return DAG.getNode((VT.getSizeInBits() < 16 ?
- ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
+ ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
}
SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
+ DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
if (VT == MVT::i8) {
// Zero extend to i32 since there is not an i8 bsr.
OpVT = MVT::i32;
- Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
+ Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
}
// Issue a bsr (scan bits in reverse) which also sets EFLAGS.
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
- Op = DAG.getNode(X86ISD::BSR, VTs, Op);
+ Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
// If src is zero (i.e. bsr sets ZF), returns NumBits.
SmallVector<SDValue, 4> Ops;
@@ -6292,13 +6410,13 @@
Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
Ops.push_back(Op.getValue(1));
- Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
+ Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
// Finally xor with NumBits-1.
- Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
+ Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
if (VT == MVT::i8)
- Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
+ Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
return Op;
}
@@ -6306,16 +6424,17 @@
MVT VT = Op.getValueType();
MVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits();
+ DebugLoc dl = Op.getDebugLoc();
Op = Op.getOperand(0);
if (VT == MVT::i8) {
OpVT = MVT::i32;
- Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
+ Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
}
// Issue a bsf (scan bits forward) which also sets EFLAGS.
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
- Op = DAG.getNode(X86ISD::BSF, VTs, Op);
+ Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
// If src is zero (i.e. bsf sets ZF), returns NumBits.
SmallVector<SDValue, 4> Ops;
@@ -6323,16 +6442,17 @@
Ops.push_back(DAG.getConstant(NumBits, OpVT));
Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
Ops.push_back(Op.getValue(1));
- Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
+ Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
if (VT == MVT::i8)
- Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
+ Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
return Op;
}
SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
+ DebugLoc dl = Op.getDebugLoc();
// ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
// ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
@@ -6347,29 +6467,29 @@
SDValue A = Op.getOperand(0);
SDValue B = Op.getOperand(1);
- SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
A, DAG.getConstant(32, MVT::i32));
- SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
B, DAG.getConstant(32, MVT::i32));
- SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
A, B);
- SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
A, Bhi);
- SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
Ahi, B);
- AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
AloBhi, DAG.getConstant(32, MVT::i32));
- AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
AhiBlo, DAG.getConstant(32, MVT::i32));
- SDValue Res = DAG.getNode(ISD::ADD, VT, AloBlo, AloBhi);
- Res = DAG.getNode(ISD::ADD, VT, Res, AhiBlo);
+ SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
+ Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
return Res;
}
@@ -6384,6 +6504,7 @@
SDValue RHS = N->getOperand(1);
unsigned BaseOp = 0;
unsigned Cond = 0;
+ DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
default: assert(0 && "Unknown ovf instruction!");
@@ -6415,10 +6536,10 @@
// Also sets EFLAGS.
SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
- SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS);
+ SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
SDValue SetCC =
- DAG.getNode(X86ISD::SETCC, N->getValueType(1),
+ DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
@@ -6427,6 +6548,7 @@
SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
MVT T = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
unsigned Reg = 0;
unsigned size = 0;
switch(T.getSimpleVT()) {
@@ -6440,7 +6562,7 @@
Reg = X86::RAX; size = 8;
break;
}
- SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
+ SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
Op.getOperand(2), SDValue());
SDValue Ops[] = { cpIn.getValue(0),
Op.getOperand(1),
@@ -6448,9 +6570,9 @@
DAG.getTargetConstant(size, MVT::i8),
cpIn.getValue(1) };
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
+ SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
SDValue cpOut =
- DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
+ DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
return cpOut;
}
@@ -6459,25 +6581,27 @@
assert(Subtarget->is64Bit() && "Result not type legalized?");
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue TheChain = Op.getOperand(0);
- SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
- SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
- SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64,
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
+ SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
+ SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
rax.getValue(2));
- SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
+ SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
DAG.getConstant(32, MVT::i8));
SDValue Ops[] = {
- DAG.getNode(ISD::OR, MVT::i64, rax, Tmp),
+ DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
rdx.getValue(1)
};
- return DAG.getMergeValues(Ops, 2);
+ return DAG.getMergeValues(Ops, 2, dl);
}
SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
MVT T = Node->getValueType(0);
- SDValue negOp = DAG.getNode(ISD::SUB, T,
+ SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
DAG.getConstant(0, T), Node->getOperand(2));
- return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD,
+ return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
cast<AtomicSDNode>(Node)->getMemoryVT(),
Node->getOperand(0),
Node->getOperand(1), negOp,
@@ -6547,22 +6671,23 @@
ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG, unsigned NewOp) {
MVT T = Node->getValueType(0);
+ DebugLoc dl = Node->getDebugLoc();
assert (T == MVT::i64 && "Only know how to expand i64 atomics");
SDValue Chain = Node->getOperand(0);
SDValue In1 = Node->getOperand(1);
- SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Node->getOperand(2), DAG.getIntPtrConstant(0));
- SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
Node->getOperand(2), DAG.getIntPtrConstant(1));
// This is a generalized SDNode, not an AtomicSDNode, so it doesn't
// have a MemOperand. Pass the info through as a normal operand.
SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
- SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
+ SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
Results.push_back(Result.getValue(2));
}
@@ -6571,6 +6696,7 @@
void X86TargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
+ DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) {
default:
assert(false && "Do not know how to custom type legalize this operation!");
@@ -6581,20 +6707,21 @@
if (FIST.getNode() != 0) {
MVT VT = N->getValueType(0);
// Return a load from the stack slot.
- Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0));
+ Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
}
return;
}
case ISD::READCYCLECOUNTER: {
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue TheChain = N->getOperand(0);
- SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
- SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
- SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32,
+ SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
+ SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
+ rd.getValue(1));
+ SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
eax.getValue(2));
// Use a buildpair to merge the two 32-bit values into a 64-bit one.
SDValue Ops[] = { eax, edx };
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
Results.push_back(edx.getValue(1));
return;
}
@@ -6602,33 +6729,33 @@
MVT T = N->getValueType(0);
assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
SDValue cpInL, cpInH;
- cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
+ cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
DAG.getConstant(0, MVT::i32));
- cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
+ cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
DAG.getConstant(1, MVT::i32));
- cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue());
- cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH,
+ cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
+ cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
cpInL.getValue(1));
SDValue swapInL, swapInH;
- swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
+ swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
DAG.getConstant(0, MVT::i32));
- swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
+ swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
DAG.getConstant(1, MVT::i32));
- swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL,
+ swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
cpInH.getValue(1));
- swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH,
+ swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
swapInL.getValue(1));
SDValue Ops[] = { swapInH.getValue(0),
N->getOperand(1),
swapInH.getValue(1) };
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
- SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
- SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
- Result.getValue(1));
- SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
- cpOutL.getValue(2));
+ SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
+ SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
+ MVT::i32, Result.getValue(1));
+ SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
+ MVT::i32, cpOutL.getValue(2));
SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
- Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
+ Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
Results.push_back(cpOutH.getValue(1));
return;
}
@@ -6891,6 +7018,7 @@
// Insert instructions into newMBB based on incoming instruction
assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
+ DebugLoc dl = bInstr->getDebugLoc();
MachineOperand& destOper = bInstr->getOperand(0);
MachineOperand* argOpers[6];
int numArgs = bInstr->getNumOperands() - 1;
@@ -6902,13 +7030,13 @@
int valArgIndx = 4;
unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
- MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
+ MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
unsigned tt = F->getRegInfo().createVirtualRegister(RC);
if (invSrc) {
- MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
+ MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
}
else
tt = t1;
@@ -6918,27 +7046,27 @@
argOpers[valArgIndx]->isImm()) &&
"invalid operand");
if (argOpers[valArgIndx]->isReg())
- MIB = BuildMI(newMBB, TII->get(regOpc), t2);
+ MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
else
- MIB = BuildMI(newMBB, TII->get(immOpc), t2);
+ MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
MIB.addReg(tt);
(*MIB).addOperand(*argOpers[valArgIndx]);
- MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
MIB.addReg(t1);
- MIB = BuildMI(newMBB, TII->get(CXchgOpc));
+ MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
MIB.addReg(t2);
assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
(*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
- MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
MIB.addReg(EAXreg);
// insert branch
- BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
+ BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
return nextMBB;
@@ -6995,6 +7123,7 @@
newMBB->addSuccessor(nextMBB);
newMBB->addSuccessor(newMBB);
+ DebugLoc dl = bInstr->getDebugLoc();
// Insert instructions into newMBB based on incoming instruction
// There are 8 "real" operands plus 9 implicit def/uses, ignored here.
assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
@@ -7008,11 +7137,11 @@
int lastAddrIndx = 3; // [0,3]
unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
- MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
+ MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
- MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
+ MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
// add 4 to displacement.
for (int i=0; i <= lastAddrIndx-1; ++i)
(*MIB).addOperand(*argOpers[i]);
@@ -7026,16 +7155,16 @@
// t3/4 are defined later, at the bottom of the loop
unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
- BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
+ BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
.addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
- BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
+ BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
.addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
if (invSrc) {
- MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
- MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
+ MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
+ MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
} else {
tt1 = t1;
tt2 = t2;
@@ -7046,46 +7175,46 @@
unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
if (argOpers[4]->isReg())
- MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
+ MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
else
- MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
+ MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
if (regOpcL != X86::MOV32rr)
MIB.addReg(tt1);
(*MIB).addOperand(*argOpers[4]);
assert(argOpers[5]->isReg() == argOpers[4]->isReg());
assert(argOpers[5]->isImm() == argOpers[4]->isImm());
if (argOpers[5]->isReg())
- MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
+ MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
else
- MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
+ MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
if (regOpcH != X86::MOV32rr)
MIB.addReg(tt2);
(*MIB).addOperand(*argOpers[5]);
- MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
MIB.addReg(t1);
- MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
MIB.addReg(t2);
- MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
MIB.addReg(t5);
- MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
MIB.addReg(t6);
- MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
+ MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
(*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
- MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
MIB.addReg(X86::EAX);
- MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
+ MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
MIB.addReg(X86::EDX);
// insert branch
- BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
+ BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
return nextMBB;
@@ -7131,6 +7260,7 @@
newMBB->addSuccessor(nextMBB);
newMBB->addSuccessor(newMBB);
+ DebugLoc dl = mInstr->getDebugLoc();
// Insert instructions into newMBB based on incoming instruction
assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
MachineOperand& destOper = mInstr->getOperand(0);
@@ -7144,7 +7274,7 @@
int valArgIndx = 4;
unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
- MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
+ MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
@@ -7155,37 +7285,37 @@
unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
if (argOpers[valArgIndx]->isReg())
- MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
+ MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
else
- MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
+ MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
(*MIB).addOperand(*argOpers[valArgIndx]);
- MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
+ MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
MIB.addReg(t1);
- MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
+ MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
MIB.addReg(t1);
MIB.addReg(t2);
// Generate movc
unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
- MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
+ MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
MIB.addReg(t2);
MIB.addReg(t1);
// Cmp and exchange if none has modified the memory location
- MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
+ MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]);
MIB.addReg(t3);
assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
(*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
- MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
+ MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
MIB.addReg(X86::EAX);
// insert branch
- BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
+ BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
return nextMBB;
@@ -7195,6 +7325,7 @@
MachineBasicBlock *
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
+ DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");
@@ -7224,7 +7355,7 @@
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
unsigned Opc =
X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
- BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
+ BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
// Update machine-CFG edges by transferring all successors of the current
@@ -7247,7 +7378,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
@@ -7268,22 +7399,23 @@
// mode when truncating to an integer value.
MachineFunction *F = BB->getParent();
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
- addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
// Load the old value of the high byte of the control word...
unsigned OldCW =
F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
- addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
+ addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
+ CWFrameIdx);
// Set the high part to be round to zero...
- addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
+ addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
.addImm(0xC7F);
// Reload the modified control word now...
- addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
// Restore the memory image of control word to original value
- addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
+ addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
.addReg(OldCW);
// Get the X86 opcode to use.
@@ -7322,11 +7454,11 @@
} else {
AM.Disp = Op.getImm();
}
- addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
+ addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
.addReg(MI->getOperand(4).getReg());
// Reload the original control word now.
- addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
return BB;
@@ -7596,6 +7728,7 @@
static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI) {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
+ DebugLoc dl = N->getDebugLoc();
MVT VT = N->getValueType(0);
MVT EVT = VT.getVectorElementType();
SDValue PermMask = N->getOperand(2);
@@ -7607,11 +7740,12 @@
LoadSDNode *LD = cast<LoadSDNode>(Base);
if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
- return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
- LD->getSrcValueOffset(), LD->isVolatile());
- return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
- LD->getSrcValueOffset(), LD->isVolatile(),
- LD->getAlignment());
+ return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
+ LD->getSrcValue(), LD->getSrcValueOffset(),
+ LD->isVolatile());
+ return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
+ LD->getSrcValue(), LD->getSrcValueOffset(),
+ LD->isVolatile(), LD->getAlignment());
}
/// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
@@ -7620,6 +7754,7 @@
const X86Subtarget *Subtarget,
const TargetLowering &TLI) {
unsigned NumOps = N->getNumOperands();
+ DebugLoc dl = N->getDebugLoc();
// Ignore single operand BUILD_VECTOR.
if (NumOps == 1)
@@ -7660,7 +7795,7 @@
SDVTList Tys = DAG.getVTList(VT, MVT::Other);
SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
- SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
+ SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
TargetLowering::TargetLoweringOpt TLO(DAG);
TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
DCI.CommitTargetLoweringOpt(TLO);
@@ -7670,6 +7805,7 @@
/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
const X86Subtarget *Subtarget) {
+ DebugLoc dl = N->getDebugLoc();
SDValue Cond = N->getOperand(0);
// If we have SSE[12] support, try to form min/max nodes.
@@ -7731,7 +7867,7 @@
}
if (Opcode)
- return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
+ return DAG.getNode(Opcode, dl, N->getValueType(0), LHS, RHS);
}
}
@@ -7756,6 +7892,7 @@
SDValue ShAmtOp = N->getOperand(1);
MVT EltVT = VT.getVectorElementType();
+ DebugLoc dl = N->getDebugLoc();
SDValue BaseShAmt;
if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
unsigned NumElts = VT.getVectorNumElements();
@@ -7775,15 +7912,15 @@
}
} else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
isSplatMask(ShAmtOp.getOperand(2).getNode())) {
- BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, ShAmtOp,
+ BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ShAmtOp,
DAG.getIntPtrConstant(0));
} else
return SDValue();
if (EltVT.bitsGT(MVT::i32))
- BaseShAmt = DAG.getNode(ISD::TRUNCATE, MVT::i32, BaseShAmt);
+ BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
else if (EltVT.bitsLT(MVT::i32))
- BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BaseShAmt);
+ BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BaseShAmt);
// The shift amount is identical so we can do a vector shift.
SDValue ValOp = N->getOperand(0);
@@ -7793,39 +7930,39 @@
break;
case ISD::SHL:
if (VT == MVT::v2i64)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
ValOp, BaseShAmt);
if (VT == MVT::v4i32)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
ValOp, BaseShAmt);
if (VT == MVT::v8i16)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
ValOp, BaseShAmt);
break;
case ISD::SRA:
if (VT == MVT::v4i32)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
ValOp, BaseShAmt);
if (VT == MVT::v8i16)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
ValOp, BaseShAmt);
break;
case ISD::SRL:
if (VT == MVT::v2i64)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
ValOp, BaseShAmt);
if (VT == MVT::v4i32)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
ValOp, BaseShAmt);
if (VT == MVT::v8i16)
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
ValOp, BaseShAmt);
break;
@@ -7867,32 +8004,33 @@
}
}
if (Ld) {
+ DebugLoc dl = N->getDebugLoc();
// If we are a 64-bit capable x86, lower to a single movq load/store pair.
if (Subtarget->is64Bit()) {
- SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
+ SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(),
Ld->getBasePtr(), Ld->getSrcValue(),
Ld->getSrcValueOffset(), Ld->isVolatile(),
Ld->getAlignment());
SDValue NewChain = NewLd.getValue(1);
if (TokenFactorIndex != -1) {
Ops.push_back(NewChain);
- NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
Ops.size());
}
- return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
+ return DAG.getStore(NewChain, dl, NewLd, St->getBasePtr(),
St->getSrcValue(), St->getSrcValueOffset(),
St->isVolatile(), St->getAlignment());
}
// Otherwise, lower to two 32-bit copies.
SDValue LoAddr = Ld->getBasePtr();
- SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
+ SDValue HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
DAG.getConstant(4, MVT::i32));
- SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
+ SDValue LoLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), LoAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset(),
Ld->isVolatile(), Ld->getAlignment());
- SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
+ SDValue HiLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), HiAddr,
Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
Ld->isVolatile(),
MinAlign(Ld->getAlignment(), 4));
@@ -7901,23 +8039,23 @@
if (TokenFactorIndex != -1) {
Ops.push_back(LoLd);
Ops.push_back(HiLd);
- NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
Ops.size());
}
LoAddr = St->getBasePtr();
- HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
+ HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
DAG.getConstant(4, MVT::i32));
- SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
+ SDValue LoSt = DAG.getStore(NewChain, dl, LoLd, LoAddr,
St->getSrcValue(), St->getSrcValueOffset(),
St->isVolatile(), St->getAlignment());
- SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
+ SDValue HiSt = DAG.getStore(NewChain, dl, HiLd, HiAddr,
St->getSrcValue(),
St->getSrcValueOffset() + 4,
St->isVolatile(),
MinAlign(St->getAlignment(), 4));
- return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
+ return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoSt, HiSt);
}
}
return SDValue();
@@ -8104,7 +8242,8 @@
if (GA) {
if (hasMemory)
- Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG);
+ Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
+ Offset, DAG);
else
Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
Offset);
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.h?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.h Sat Feb 14 07:20:23 2009
@@ -549,7 +549,7 @@
bool CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall);
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
SDValue Chain, bool IsTailCall, bool Is64Bit,
- int FPDiff);
+ int FPDiff, DebugLoc dl);
CCAssignFn *CCAssignFnForNode(unsigned CallingConv) const;
NameDecorationStyle NameDecorationForFORMAL_ARGUMENTS(SDValue Op);
@@ -566,8 +566,8 @@
SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG);
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
- SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
- SelectionDAG &DAG) const;
+ SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
+ int64_t Offset, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
@@ -612,12 +612,12 @@
void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG, unsigned NewOp);
- SDValue EmitTargetCodeForMemset(SelectionDAG &DAG,
+ SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
const Value *DstSV, uint64_t DstSVOff);
- SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG,
+ SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp Sat Feb 14 07:20:23 2009
@@ -905,6 +905,9 @@
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (I != MBB.end()) DL = I->getDebugLoc();
+
unsigned SubIdx = Orig->getOperand(0).isReg()
? Orig->getOperand(0).getSubReg() : 0;
bool ChangeSubIdx = SubIdx != 0;
@@ -931,7 +934,7 @@
case X86::MOV32r0: Opc = X86::MOV32ri; break;
case X86::MOV64r0: Opc = X86::MOV64ri32; break;
}
- BuildMI(MBB, I, get(Opc), DestReg).addImm(0);
+ BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
Emitted = true;
}
break;
@@ -1038,7 +1041,8 @@
if (B != C) return 0;
unsigned A = MI->getOperand(0).getReg();
unsigned M = MI->getOperand(3).getImm();
- NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
+ .addReg(A, true, false, false, isDead)
.addReg(B, false, false, isKill).addImm(M);
break;
}
@@ -1049,7 +1053,8 @@
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
- NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
+ .addReg(Dest, true, false, false, isDead)
.addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
break;
}
@@ -1062,7 +1067,8 @@
unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
X86::LEA64_32r : X86::LEA32r;
- NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
+ .addReg(Dest, true, false, false, isDead)
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0);
break;
@@ -1084,17 +1090,21 @@
// Build and insert into an implicit UNDEF value. This is OK because
// well be shifting and then extracting the lower 16-bits.
- BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg);
- MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg)
+ BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
+ MachineInstr *InsMI =
+ BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
.addReg(leaInReg).addReg(Src, false, false, isKill)
.addImm(X86::SUBREG_16BIT);
- NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
+ NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
+ .addReg(0).addImm(1 << ShAmt)
.addReg(leaInReg, false, false, true).addImm(0);
- MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG))
+ MachineInstr *ExtMI =
+ BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
.addReg(Dest, true, false, false, isDead)
.addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
+
if (LV) {
// Update live variables
LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
@@ -1106,7 +1116,8 @@
}
return ExtMI;
} else {
- NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
+ NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
+ .addReg(Dest, true, false, false, isDead)
.addReg(0).addImm(1 << ShAmt)
.addReg(Src, false, false, isKill).addImm(0);
}
@@ -1128,7 +1139,7 @@
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
- NewMI = addRegOffset(BuildMI(MF, get(Opc))
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, 1);
break;
@@ -1137,7 +1148,7 @@
case X86::INC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
- NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, 1);
break;
@@ -1147,7 +1158,7 @@
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
- NewMI = addRegOffset(BuildMI(MF, get(Opc))
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, -1);
break;
@@ -1156,7 +1167,7 @@
case X86::DEC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
- NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, -1);
break;
@@ -1167,7 +1178,7 @@
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
- NewMI = addRegReg(BuildMI(MF, get(Opc))
+ NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, Src2, isKill2);
if (LV && isKill2)
@@ -1179,7 +1190,7 @@
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
unsigned Src2 = MI->getOperand(2).getReg();
bool isKill2 = MI->getOperand(2).isKill();
- NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r))
+ NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, Src2, isKill2);
if (LV && isKill2)
@@ -1190,7 +1201,7 @@
case X86::ADD64ri8:
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm())
- NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
break;
@@ -1199,7 +1210,7 @@
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm()) {
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
- NewMI = addRegOffset(BuildMI(MF, get(Opc))
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
}
@@ -1209,7 +1220,7 @@
if (DisableLEA16) return 0;
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm())
- NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
.addReg(Dest, true, false, false, isDead),
Src, isKill, MI->getOperand(2).getImm());
break;
@@ -1227,7 +1238,7 @@
unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
: (MIOpc == X86::SHL32ri
? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
- NewMI = addFullAddress(BuildMI(MF, get(Opc))
+ NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
.addReg(Dest, true, false, false, isDead), AM);
if (isKill)
NewMI->getOperand(3).setIsKill(true);
@@ -1619,6 +1630,8 @@
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc operand
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
@@ -1627,7 +1640,7 @@
if (Cond.empty()) {
// Unconditional branch?
assert(!FBB && "Unconditional branch with multiple successors!");
- BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
return 1;
}
@@ -1637,27 +1650,27 @@
switch (CC) {
case X86::COND_NP_OR_E:
// Synthesize NP_OR_E with two branches.
- BuildMI(&MBB, get(X86::JNP)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
++Count;
- BuildMI(&MBB, get(X86::JE)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
++Count;
break;
case X86::COND_NE_OR_P:
// Synthesize NE_OR_P with two branches.
- BuildMI(&MBB, get(X86::JNE)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
++Count;
- BuildMI(&MBB, get(X86::JP)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
++Count;
break;
default: {
unsigned Opc = GetCondBranchFromCond(CC);
- BuildMI(&MBB, get(Opc)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
++Count;
}
}
if (FBB) {
// Two-way Conditional branch. Insert the second branch.
- BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
+ BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
++Count;
}
return Count;
@@ -1668,6 +1681,9 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
if (DestRC == SrcRC) {
unsigned Opc;
if (DestRC == &X86::GR64RegClass) {
@@ -1699,7 +1715,7 @@
} else {
return false;
}
- BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
return true;
}
@@ -1708,24 +1724,24 @@
if (SrcReg != X86::EFLAGS)
return false;
if (DestRC == &X86::GR64RegClass) {
- BuildMI(MBB, MI, get(X86::PUSHFQ));
- BuildMI(MBB, MI, get(X86::POP64r), DestReg);
+ BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
+ BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
return true;
} else if (DestRC == &X86::GR32RegClass) {
- BuildMI(MBB, MI, get(X86::PUSHFD));
- BuildMI(MBB, MI, get(X86::POP32r), DestReg);
+ BuildMI(MBB, MI, DL, get(X86::PUSHFD));
+ BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
return true;
}
} else if (DestRC == &X86::CCRRegClass) {
if (DestReg != X86::EFLAGS)
return false;
if (SrcRC == &X86::GR64RegClass) {
- BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
- BuildMI(MBB, MI, get(X86::POPFQ));
+ BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(X86::POPFQ));
return true;
} else if (SrcRC == &X86::GR32RegClass) {
- BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
- BuildMI(MBB, MI, get(X86::POPFD));
+ BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(X86::POPFD));
return true;
}
}
@@ -1747,7 +1763,7 @@
return false;
Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
}
- BuildMI(MBB, MI, get(Opc), DestReg);
+ BuildMI(MBB, MI, DL, get(Opc), DestReg);
return true;
}
@@ -1767,7 +1783,7 @@
return false;
Opc = X86::FpSET_ST0_80;
}
- BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
+ BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
return true;
}
@@ -1821,8 +1837,10 @@
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getStoreRegOpcode(RC, isAligned);
- addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
- .addReg(SrcReg, false, false, isKill);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
+ .addReg(SrcReg, false, false, isKill);
}
void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
@@ -1833,7 +1851,8 @@
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getStoreRegOpcode(RC, isAligned);
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, Addr[i]);
MIB.addReg(SrcReg, false, false, isKill);
@@ -1886,7 +1905,9 @@
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getLoadRegOpcode(RC, isAligned);
- addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+ addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
}
void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
@@ -1896,18 +1917,22 @@
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
unsigned Opc = getLoadRegOpcode(RC, isAligned);
- MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
MIB = X86InstrAddOperand(MIB, Addr[i]);
NewMIs.push_back(MIB);
}
bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
+ MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const {
if (CSI.empty())
return false;
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
unsigned SlotSize = is64Bit ? 8 : 4;
@@ -1920,24 +1945,27 @@
unsigned Reg = CSI[i-1].getReg();
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
- BuildMI(MBB, MI, get(Opc))
+ BuildMI(MBB, MI, DL, get(Opc))
.addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
}
return true;
}
bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MI,
+ MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const {
if (CSI.empty())
return false;
-
+
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MI != MBB.end()) DL = MI->getDebugLoc();
+
bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
- BuildMI(MBB, MI, get(Opc), Reg);
+ BuildMI(MBB, MI, DL, get(Opc), Reg);
}
return true;
}
@@ -1997,7 +2025,7 @@
const SmallVectorImpl<MachineOperand> &MOs,
MachineInstr *MI) {
MachineFunction &MF = *MI->getParent()->getParent();
- MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
+ MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
unsigned NumAddrOps = MOs.size();
for (unsigned i = 0; i != NumAddrOps; ++i)
@@ -2257,11 +2285,12 @@
bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
- SmallVectorImpl<MachineInstr*> &NewMIs) const {
+ SmallVectorImpl<MachineInstr*> &NewMIs) const {
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
if (I == MemOp2RegOpTable.end())
return false;
+ DebugLoc dl = MI->getDebugLoc();
unsigned Opc = I->second.first;
unsigned Index = I->second.second & 0xf;
bool FoldedLoad = I->second.second & (1 << 4);
@@ -2360,7 +2389,7 @@
bool
X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
- SmallVectorImpl<SDNode*> &NewNodes) const {
+ SmallVectorImpl<SDNode*> &NewNodes) const {
if (!N->isMachineOpcode())
return false;
@@ -2379,6 +2408,7 @@
std::vector<SDValue> AddrOps;
std::vector<SDValue> BeforeOps;
std::vector<SDValue> AfterOps;
+ DebugLoc dl = N->getDebugLoc();
unsigned NumOps = N->getNumOperands();
for (unsigned i = 0; i != NumOps-1; ++i) {
SDValue Op = N->getOperand(i);
@@ -2399,7 +2429,7 @@
MVT VT = *RC->vt_begin();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned),
+ Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), dl,
VT, MVT::Other,
&AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
@@ -2422,7 +2452,8 @@
if (Load)
BeforeOps.push_back(SDValue(Load, 0));
std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
- SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
+ SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
+ BeforeOps.size());
NewNodes.push_back(NewNode);
// Emit the store instruction.
@@ -2432,7 +2463,7 @@
AddrOps.push_back(Chain);
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned),
+ SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), dl,
MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Store);
}
@@ -3075,13 +3106,16 @@
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = MF->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+ DebugLoc DL = DebugLoc::getUnknownLoc();
+ if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
const TargetInstrInfo *TII = TM.getInstrInfo();
// Operand of MovePCtoStack is completely ignored by asm printer. It's
// only used in JIT code emission as displacement to pc.
- BuildMI(FirstMBB, MBBI, TII->get(X86::MOVPC32r), PC).addImm(0);
+ BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC)
+ .addImm(0);
// If we're using vanilla 'GOT' PIC style, we should use relative addressing
// not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
@@ -3089,7 +3123,7 @@
TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
GlobalBaseReg =
RegInfo.createVirtualRegister(X86::GR32RegisterClass);
- BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg)
+ BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
.addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
} else {
GlobalBaseReg = PC;
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.cpp Sat Feb 14 07:20:23 2009
@@ -396,7 +396,8 @@
MachineInstr *New = 0;
if (Old->getOpcode() == getCallFrameSetupOpcode()) {
- New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
+ New = BuildMI(MF, Old->getDebugLoc(),
+ TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
StackPtr).addReg(StackPtr).addImm(Amount);
} else {
assert(Old->getOpcode() == getCallFrameDestroyOpcode());
@@ -407,7 +408,7 @@
unsigned Opc = (Amount < 128) ?
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
- New = BuildMI(MF, TII.get(Opc), StackPtr)
+ New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
.addReg(StackPtr).addImm(Amount);
}
}
@@ -426,8 +427,10 @@
unsigned Opc = (CalleeAmt < 128) ?
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
+ MachineInstr *Old = I;
MachineInstr *New =
- BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
+ BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
+ StackPtr).addReg(StackPtr).addImm(CalleeAmt);
// The EFLAGS implicit def is dead.
New->getOperand(3).setIsDead();
@@ -537,11 +540,14 @@
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
uint64_t Chunk = (1LL << 31) - 1;
+ // We could pass in a DebugLoc, but this is only called from prolog/epilog.
+ DebugLoc DL = DebugLoc::getUnknownLoc();
while (Offset) {
uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
MachineInstr *MI =
- BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
+ BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
+ .addReg(StackPtr).addImm(ThisVal);
// The EFLAGS implicit def is dead.
MI->getOperand(3).setIsDead();
Offset -= ThisVal;
@@ -721,6 +727,7 @@
bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
!Fn->doesNotThrow() ||
UnwindTablesMandatory;
+ DebugLoc DL = DebugLoc::getUnknownLoc();
// Prepare for frame info.
unsigned FrameLabelId = 0;
@@ -755,7 +762,7 @@
// size is bigger than the callers.
if (TailCallReturnAddrDelta < 0) {
MachineInstr *MI =
- BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
+ BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
// The EFLAGS implicit def is dead.
MI->getOperand(3).setIsDead();
@@ -776,18 +783,19 @@
MFI->setOffsetAdjustment(-NumBytes);
// Save EBP into the appropriate stack slot...
- BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
+ BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
.addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
}
// Update EBP with the new base value...
- BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
- .addReg(StackPtr);
+ BuildMI(MBB, MBBI, DL,
+ TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
+ .addReg(StackPtr);
// Mark the FramePtr as live-in in every block except the entry.
for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
@@ -797,7 +805,7 @@
// Realign stack
if (needsStackRealignment(MF)) {
MachineInstr *MI =
- BuildMI(MBB, MBBI,
+ BuildMI(MBB, MBBI, DL,
TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
StackPtr).addReg(StackPtr).addImm(-MaxAlign);
// The EFLAGS implicit def is dead.
@@ -810,7 +818,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer is ready.
ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
}
// Skip the callee-saved push instructions.
@@ -836,20 +844,22 @@
// necessary to ensure that the guard pages used by the OS virtual memory
// manager are allocated in correct sequence.
if (!isEAXAlive) {
- BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
- BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
+ BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
.addExternalSymbol("_alloca");
} else {
// Save EAX
- BuildMI(MBB, MBBI, TII.get(X86::PUSH32r))
+ BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
.addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
// Allocate NumBytes-4 bytes on stack. We'll also use 4 already
// allocated bytes for EAX.
- BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
- BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
+ BuildMI(MBB, MBBI, DL,
+ TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
.addExternalSymbol("_alloca");
// Restore EAX
- MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
+ MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
+ X86::EAX),
StackPtr, false, NumBytes-4);
MBB.insert(MBBI, MI);
}
@@ -877,6 +887,7 @@
X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
unsigned RetOpcode = MBBI->getOpcode();
+ DebugLoc DL = DebugLoc::getUnknownLoc();
switch (RetOpcode) {
case X86::RET:
@@ -909,7 +920,8 @@
NumBytes = FrameSize - CSSize;
// pop EBP.
- BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
+ BuildMI(MBB, MBBI, DL,
+ TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
} else
NumBytes = StackSize - CSSize;
@@ -940,17 +952,17 @@
MBBI = prior(LastCSPop);
}
- BuildMI(MBB, MBBI,
+ BuildMI(MBB, MBBI, DL,
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
StackPtr).addReg(FramePtr);
} else if (MFI->hasVarSizedObjects()) {
if (CSSize) {
unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
- MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
+ MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
FramePtr, false, -CSSize);
MBB.insert(MBBI, MI);
} else
- BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
+ BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
StackPtr).addReg(FramePtr);
} else {
@@ -964,7 +976,7 @@
MBBI = prior(MBB.end());
MachineOperand &DestAddr = MBBI->getOperand(0);
assert(DestAddr.isReg() && "Offset should be in register!");
- BuildMI(MBB, MBBI,
+ BuildMI(MBB, MBBI, DL,
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
StackPtr).addReg(DestAddr.getReg());
// Tail call return: adjust the stack pointer and jump to callee
@@ -990,12 +1002,12 @@
}
// Jump to label or value in register.
if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
- BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
+ BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
else if (RetOpcode== X86::TCRETURNri64) {
- BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
+ BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
} else
- BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
+ BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
// Delete the pseudo instruction TCRETURN.
MBB.erase(MBBI);
} else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
Modified: llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelDAGToDAG.cpp Sat Feb 14 07:20:23 2009
@@ -158,6 +158,7 @@
SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
+ DebugLoc dl = N->getDebugLoc();
MVT NVT = N->getValueType(0);
if (NVT == MVT::i32) {
switch (N->getOpcode()) {
@@ -165,26 +166,27 @@
case ISD::Constant: {
if (Predicate_immMskBitp(N)) {
SDValue MskSize = Transform_msksize_xform(N);
- return CurDAG->getTargetNode(XCore::MKMSK_rus, MVT::i32, MskSize);
+ return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize);
}
else if (! Predicate_immU16(N)) {
unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
SDValue CPIdx =
CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
TLI.getPointerTy());
- return CurDAG->getTargetNode(XCore::LDWCP_lru6, MVT::i32, MVT::Other,
- CPIdx, CurDAG->getEntryNode());
+ return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, MVT::i32,
+ MVT::Other, CPIdx,
+ CurDAG->getEntryNode());
}
break;
}
case ISD::SMUL_LOHI: {
// FIXME fold addition into the macc instruction
if (!Subtarget.isXS1A()) {
- SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, MVT::i32,
+ SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
- SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, MVT::i32,
- MVT::i32, Ops, 4);
+ SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, dl,
+ MVT::i32, MVT::i32, Ops, 4);
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
return NULL;
@@ -193,11 +195,11 @@
}
case ISD::UMUL_LOHI: {
// FIXME fold addition into the macc / lmul instruction
- SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, MVT::i32,
+ SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32,
CurDAG->getTargetConstant(0, MVT::i32)), 0);
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Zero, Zero };
- SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, MVT::i32,
+ SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, MVT::i32,
MVT::i32, Ops, 4);
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
@@ -207,7 +209,7 @@
if (!Subtarget.isXS1A()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2) };
- return CurDAG->getTargetNode(XCore::LADD_l5r, MVT::i32, MVT::i32,
+ return CurDAG->getTargetNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
Ops, 3);
}
break;
@@ -216,7 +218,7 @@
if (!Subtarget.isXS1A()) {
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2) };
- return CurDAG->getTargetNode(XCore::LSUB_l5r, MVT::i32, MVT::i32,
+ return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
Ops, 3);
}
break;
Modified: llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelLowering.cpp?rev=64552&r1=64551&r2=64552&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/XCore/XCoreISelLowering.cpp Sat Feb 14 07:20:23 2009
@@ -194,17 +194,20 @@
SDValue XCoreTargetLowering::
LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
{
- SDValue Cond = DAG.getNode(ISD::SETCC, MVT::i32, Op.getOperand(2),
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
Op.getOperand(3), Op.getOperand(4));
- return DAG.getNode(ISD::SELECT, MVT::i32, Cond, Op.getOperand(0),
+ return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
Op.getOperand(1));
}
SDValue XCoreTargetLowering::
getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG)
{
+ // FIXME there is no actual debug info here
+ DebugLoc dl = GA.getDebugLoc();
if (isa<Function>(GV)) {
- return DAG.getNode(XCoreISD::PCRelativeWrapper, MVT::i32, GA);
+ return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
} else if (!Subtarget.isXS1A()) {
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
if (!GVar) {
@@ -214,10 +217,10 @@
}
bool isConst = GVar && GVar->isConstant();
if (isConst) {
- return DAG.getNode(XCoreISD::CPRelativeWrapper, MVT::i32, GA);
+ return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
}
}
- return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, GA);
+ return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
}
SDValue XCoreTargetLowering::
@@ -231,8 +234,8 @@
return getGlobalAddressWrapper(GA, GV, DAG);
}
-static inline SDValue BuildGetId(SelectionDAG &DAG) {
- return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32,
+static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
}
@@ -244,6 +247,8 @@
SDValue XCoreTargetLowering::
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
{
+ // FIXME there isn't really debug info here
+ DebugLoc dl = Op.getDebugLoc();
// transform to label + getid() * size
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
@@ -266,15 +271,17 @@
SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
const TargetData *TD = TM.getTargetData();
unsigned Size = TD->getTypePaddedSize(Ty);
- SDValue offset = DAG.getNode(ISD::MUL, MVT::i32, BuildGetId(DAG),
+ SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
DAG.getConstant(Size, MVT::i32));
- return DAG.getNode(ISD::ADD, MVT::i32, base, offset);
+ return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
}
SDValue XCoreTargetLowering::
LowerConstantPool(SDValue Op, SelectionDAG &DAG)
{
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
+ // FIXME there isn't really debug info here
+ DebugLoc dl = CP->getDebugLoc();
if (Subtarget.isXS1A()) {
assert(0 && "Lowering of constant pool unimplemented");
return SDValue();
@@ -288,17 +295,19 @@
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
}
- return DAG.getNode(XCoreISD::CPRelativeWrapper, MVT::i32, Res);
+ return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
}
}
SDValue XCoreTargetLowering::
LowerJumpTable(SDValue Op, SelectionDAG &DAG)
{
+ // FIXME there isn't really debug info here
+ DebugLoc dl = Op.getDebugLoc();
MVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
- return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, JTI);
+ return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, JTI);
}
SDValue XCoreTargetLowering::
@@ -308,30 +317,31 @@
(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
"Unknown operand to lower!");
assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a");
+ DebugLoc dl = N->getDebugLoc();
// Extract components
- SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
- DAG.getConstant(0, MVT::i32));
- SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
- DAG.getConstant(1, MVT::i32));
- SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1),
- DAG.getConstant(0, MVT::i32));
- SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(1),
- DAG.getConstant(1, MVT::i32));
+ SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(0), DAG.getConstant(0, MVT::i32));
+ SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(0), DAG.getConstant(1, MVT::i32));
+ SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(1), DAG.getConstant(0, MVT::i32));
+ SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
+ N->getOperand(1), DAG.getConstant(1, MVT::i32));
// Expand
unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
XCoreISD::LSUB;
SDValue Zero = DAG.getConstant(0, MVT::i32);
- SDValue Carry = DAG.getNode(Opcode, DAG.getVTList(MVT::i32, MVT::i32),
+ SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
LHSL, RHSL, Zero);
SDValue Lo(Carry.getNode(), 1);
- SDValue Ignored = DAG.getNode(Opcode, DAG.getVTList(MVT::i32, MVT::i32),
+ SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
LHSH, RHSH, Carry);
SDValue Hi(Ignored.getNode(), 1);
// Merge the pieces
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
+ return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
}
SDValue XCoreTargetLowering::
@@ -340,41 +350,44 @@
assert(0 && "unimplemented");
// FIX Arguments passed by reference need a extra dereference.
SDNode *Node = Op.getNode();
+ DebugLoc dl = Node->getDebugLoc();
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
MVT VT = Node->getValueType(0);
- SDValue VAList = DAG.getLoad(getPointerTy(), Node->getOperand(0),
+ SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
Node->getOperand(1), V, 0);
// Increment the pointer, VAList, to the next vararg
- SDValue Tmp3 = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
+ SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
DAG.getConstant(VT.getSizeInBits(),
getPointerTy()));
// Store the incremented VAList to the legalized pointer
- Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Node->getOperand(1), V, 0);
+ Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0);
// Load the actual argument out of the pointer VAList
- return DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
+ return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
}
SDValue XCoreTargetLowering::
LowerVASTART(SDValue Op, SelectionDAG &DAG)
{
+ DebugLoc dl = Op.getDebugLoc();
// vastart stores the address of the VarArgsFrameIndex slot into the
// memory location argument
MachineFunction &MF = DAG.getMachineFunction();
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- return DAG.getStore(Op.getOperand(0), Addr, Op.getOperand(1), SV, 0);
+ return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0);
}
SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
+ DebugLoc dl = Op.getDebugLoc();
// Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
return SDValue();
MachineFunction &MF = DAG.getMachineFunction();
const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
- return DAG.getCopyFromReg(DAG.getEntryNode(), RegInfo->getFrameRegister(MF),
- MVT::i32);
+ return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
+ RegInfo->getFrameRegister(MF), MVT::i32);
}
//===----------------------------------------------------------------------===//
@@ -422,6 +435,7 @@
SDValue Chain = TheCall->getChain();
SDValue Callee = TheCall->getCallee();
bool isVarArg = TheCall->isVarArg();
+ DebugLoc dl = Op.getDebugLoc();
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
@@ -454,13 +468,13 @@
default: assert(0 && "Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
- Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::ZExt:
- Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
break;
case CCValAssign::AExt:
- Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
+ Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
break;
}
@@ -473,7 +487,8 @@
int Offset = VA.getLocMemOffset();
- MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, MVT::Other, Chain, Arg,
+ MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
+ Chain, Arg,
DAG.getConstant(Offset/4, MVT::i32)));
}
}
@@ -481,7 +496,7 @@
// Transform all store nodes into one single node because
// all store nodes are independent of each other.
if (!MemOpChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token
@@ -490,7 +505,7 @@
// stuck together.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
- Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
+ Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
@@ -521,7 +536,7 @@
if (InFlag.getNode())
Ops.push_back(InFlag);
- Chain = DAG.getNode(XCoreISD::BL, NodeTys, &Ops[0], Ops.size());
+ Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node.
@@ -546,6 +561,7 @@
LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
unsigned CallingConv, SelectionDAG &DAG) {
bool isVarArg = TheCall->isVarArg();
+ DebugLoc dl = TheCall->getDebugLoc();
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
@@ -556,7 +572,7 @@
// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
- Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
+ Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
RVLocs[i].getValVT(), InFlag).getValue(1);
InFlag = Chain.getValue(2);
ResultVals.push_back(Chain.getValue(0));
@@ -565,7 +581,7 @@
ResultVals.push_back(Chain);
// Merge everything together with a MERGE_VALUES node.
- return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
+ return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
&ResultVals[0], ResultVals.size()).getNode();
}
@@ -601,6 +617,7 @@
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
unsigned CC = MF.getFunction()->getCallingConv();
+ DebugLoc dl = Op.getDebugLoc();
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
@@ -631,7 +648,7 @@
unsigned VReg = RegInfo.createVirtualRegister(
XCore::GRRegsRegisterClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
- ArgValues.push_back(DAG.getCopyFromReg(Root, VReg, RegVT));
+ ArgValues.push_back(DAG.getCopyFromReg(Root, dl, VReg, RegVT));
}
} else {
// sanity check
@@ -650,7 +667,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
- ArgValues.push_back(DAG.getLoad(VA.getLocVT(), Root, FIN, NULL, 0));
+ ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN, NULL, 0));
}
}
@@ -679,13 +696,13 @@
unsigned VReg = RegInfo.createVirtualRegister(
XCore::GRRegsRegisterClass);
RegInfo.addLiveIn(ArgRegs[i], VReg);
- SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
// Move argument from virt reg -> stack
- SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
}
if (!MemOps.empty())
- Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOps[0], MemOps.size());
} else {
// This will point to the next argument passed via stack.
@@ -699,7 +716,8 @@
// Return the new list of results.
std::vector<MVT> RetVT(Op.getNode()->value_begin(),
Op.getNode()->value_end());
- return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
+ return DAG.getNode(ISD::MERGE_VALUES, dl, RetVT,
+ &ArgValues[0], ArgValues.size());
}
//===----------------------------------------------------------------------===//
@@ -714,6 +732,7 @@
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
+ DebugLoc dl = Op.getDebugLoc();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
@@ -740,7 +759,8 @@
// ISD::RET => ret chain, (regnum1,val1), ...
// So i*2+1 index only the regnums
- Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
+ Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
+ Op.getOperand(i*2+1), Flag);
// guarantee that all emitted copies are
// stuck together, avoiding something bad
@@ -749,10 +769,10 @@
// Return on XCore is always a "retsp 0"
if (Flag.getNode())
- return DAG.getNode(XCoreISD::RETSP, MVT::Other,
+ return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
Chain, DAG.getConstant(0, MVT::i32), Flag);
else // Return Void
- return DAG.getNode(XCoreISD::RETSP, MVT::Other,
+ return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
Chain, DAG.getConstant(0, MVT::i32));
}
@@ -764,6 +784,7 @@
XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
+ DebugLoc dl = MI->getDebugLoc();
assert((MI->getOpcode() == XCore::SELECT_CC) &&
"Unexpected instr type to insert");
@@ -785,7 +806,7 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, TII.get(XCore::BRFT_lru6))
+ BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
.addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
@@ -808,7 +829,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII.get(XCore::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
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