[llvm-commits] [llvm] r64431 - in /llvm/trunk/lib/Target/PowerPC: PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.cpp PPCRegisterInfo.cpp
Dale Johannesen
dalej at apple.com
Thu Feb 12 18:27:39 PST 2009
Author: johannes
Date: Thu Feb 12 20:27:39 2009
New Revision: 64431
URL: http://llvm.org/viewvc/llvm-project?rev=64431&view=rev
Log:
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=64431&r1=64430&r2=64431&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp Thu Feb 12 20:27:39 2009
@@ -145,13 +145,14 @@
unsigned CRReg = I->getOperand(1).getReg();
MachineInstr *OldBranch = I;
+ DebugLoc dl = OldBranch->getDebugLoc();
// Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
- BuildMI(MBB, I, TII->get(PPC::BCC))
+ BuildMI(MBB, I, dl, TII->get(PPC::BCC))
.addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
// Uncond branch to the real destination.
- I = BuildMI(MBB, I, TII->get(PPC::B)).addMBB(Dest);
+ I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
// Remove the old branch from the function.
OldBranch->eraseFromParent();
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=64431&r1=64430&r2=64431&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Feb 12 20:27:39 2009
@@ -243,15 +243,16 @@
const TargetInstrInfo &TII = *TM.getInstrInfo();
MachineBasicBlock &EntryBB = *Fn.begin();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Emit the following code into the entry block:
// InVRSAVE = MFVRSAVE
// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
// MTVRSAVE UpdatedVRSAVE
MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
- BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
- BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
+ BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
+ BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
UpdatedVRSAVE).addReg(InVRSAVE);
- BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
+ BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
// Find all return blocks, outputting a restore in each epilog.
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
@@ -265,7 +266,7 @@
IP = I2;
// Emit: MTVRSAVE InVRSave
- BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
+ BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
}
}
}
@@ -280,15 +281,16 @@
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
if (PPCLowering.getPointerTy() == MVT::i32) {
GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
} else {
GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
- BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
}
}
return CurDAG->getRegister(GlobalBaseReg,
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=64431&r1=64430&r2=64431&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Feb 12 20:27:39 2009
@@ -3966,6 +3966,7 @@
unsigned ptrA = MI->getOperand(1).getReg();
unsigned ptrB = MI->getOperand(2).getReg();
unsigned incr = MI->getOperand(3).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -3991,13 +3992,13 @@
// bne- loopMBB
// fallthrough --> exitMBB
BB = loopMBB;
- BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
.addReg(ptrA).addReg(ptrB);
if (BinOpcode)
- BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
- BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
BB->addSuccessor(exitMBB);
@@ -4030,6 +4031,7 @@
unsigned ptrA = MI->getOperand(1).getReg();
unsigned ptrB = MI->getOperand(2).getReg();
unsigned incr = MI->getOperand(3).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -4082,47 +4084,47 @@
if (ptrA!=PPC::R0) {
Ptr1Reg = RegInfo.createVirtualRegister(RC);
- BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
.addReg(ptrA).addReg(ptrB);
} else {
Ptr1Reg = ptrB;
}
- BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
- BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
if (is64bit)
- BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(61);
else
- BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
- BuildMI(BB, TII->get(PPC::SLW), Incr2Reg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
.addReg(incr).addReg(ShiftReg);
if (is8bit)
- BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
else {
- BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
- BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
+ BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
}
- BuildMI(BB, TII->get(PPC::SLW), MaskReg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
.addReg(Mask2Reg).addReg(ShiftReg);
BB = loopMBB;
- BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
+ BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
.addReg(PPC::R0).addReg(PtrReg);
if (BinOpcode)
- BuildMI(BB, TII->get(BinOpcode), TmpReg)
+ BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
.addReg(Incr2Reg).addReg(TmpDestReg);
- BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
.addReg(TmpDestReg).addReg(MaskReg);
- BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
.addReg(TmpReg).addReg(MaskReg);
- BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
.addReg(Tmp3Reg).addReg(Tmp2Reg);
- BuildMI(BB, TII->get(PPC::STWCX))
+ BuildMI(BB, dl, TII->get(PPC::STWCX))
.addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
BB->addSuccessor(exitMBB);
@@ -4130,7 +4132,7 @@
// exitMBB:
// ...
BB = exitMBB;
- BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
+ BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
return BB;
}
@@ -4167,7 +4169,8 @@
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
- BuildMI(BB, TII->get(PPC::BCC))
+ DebugLoc dl = MI->getDebugLoc();
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
@@ -4190,7 +4193,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
+ BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
}
@@ -4266,6 +4269,7 @@
unsigned ptrB = MI->getOperand(2).getReg();
unsigned oldval = MI->getOperand(3).getReg();
unsigned newval = MI->getOperand(4).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -4294,26 +4298,26 @@
// st[wd]cx. dest, ptr
// exitBB:
BB = loop1MBB;
- BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
.addReg(ptrA).addReg(ptrB);
- BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
.addReg(oldval).addReg(dest);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
BB->addSuccessor(loop2MBB);
BB->addSuccessor(midMBB);
BB = loop2MBB;
- BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(newval).addReg(ptrA).addReg(ptrB);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
- BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
+ BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
BB->addSuccessor(loop1MBB);
BB->addSuccessor(exitMBB);
BB = midMBB;
- BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
.addReg(dest).addReg(ptrA).addReg(ptrB);
BB->addSuccessor(exitMBB);
@@ -4333,6 +4337,7 @@
unsigned ptrB = MI->getOperand(2).getReg();
unsigned oldval = MI->getOperand(3).getReg();
unsigned newval = MI->getOperand(4).getReg();
+ DebugLoc dl = MI->getDebugLoc();
MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -4397,69 +4402,73 @@
// srw dest, tmpDest, shift
if (ptrA!=PPC::R0) {
Ptr1Reg = RegInfo.createVirtualRegister(RC);
- BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
.addReg(ptrA).addReg(ptrB);
} else {
Ptr1Reg = ptrB;
}
- BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
.addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
- BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
+ BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
.addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
if (is64bit)
- BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(61);
else
- BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
+ BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
.addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
- BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
.addReg(newval).addReg(ShiftReg);
- BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
.addReg(oldval).addReg(ShiftReg);
if (is8bit)
- BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
else {
- BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
- BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
+ BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
+ BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
+ .addReg(Mask3Reg).addImm(65535);
}
- BuildMI(BB, TII->get(PPC::SLW), MaskReg)
+ BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
.addReg(Mask2Reg).addReg(ShiftReg);
- BuildMI(BB, TII->get(PPC::AND), NewVal3Reg)
+ BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
.addReg(NewVal2Reg).addReg(MaskReg);
- BuildMI(BB, TII->get(PPC::AND), OldVal3Reg)
+ BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
.addReg(OldVal2Reg).addReg(MaskReg);
BB = loop1MBB;
- BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
+ BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
.addReg(PPC::R0).addReg(PtrReg);
- BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg);
- BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0)
+ BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
+ .addReg(TmpDestReg).addReg(MaskReg);
+ BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
.addReg(TmpReg).addReg(OldVal3Reg);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
BB->addSuccessor(loop2MBB);
BB->addSuccessor(midMBB);
BB = loop2MBB;
- BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg);
- BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg);
- BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
+ BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
+ .addReg(TmpDestReg).addReg(MaskReg);
+ BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
+ .addReg(Tmp2Reg).addReg(NewVal3Reg);
+ BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
.addReg(PPC::R0).addReg(PtrReg);
- BuildMI(BB, TII->get(PPC::BCC))
+ BuildMI(BB, dl, TII->get(PPC::BCC))
.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
- BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
+ BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
BB->addSuccessor(loop1MBB);
BB->addSuccessor(exitMBB);
BB = midMBB;
- BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg)
+ BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
.addReg(PPC::R0).addReg(PtrReg);
BB->addSuccessor(exitMBB);
// exitMBB:
// ...
BB = exitMBB;
- BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
+ BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
} else {
assert(0 && "Unexpected instr type to insert");
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=64431&r1=64430&r2=64431&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Feb 12 20:27:39 2009
@@ -292,6 +292,8 @@
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
+ // FIXME this should probably have a DebugLoc argument
+ DebugLoc dl = DebugLoc::getUnknownLoc();
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -300,17 +302,17 @@
// One-way branch.
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch
- BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
+ BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
else // Conditional branch
- BuildMI(&MBB, get(PPC::BCC))
+ BuildMI(&MBB, dl, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return 1;
}
// Two-way Conditional Branch.
- BuildMI(&MBB, get(PPC::BCC))
+ BuildMI(&MBB, dl, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
- BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
+ BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
return 2;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=64431&r1=64430&r2=64431&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Feb 12 20:27:39 2009
@@ -426,18 +426,20 @@
unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
+ MachineInstr *MI = I;
+ DebugLoc dl = MI->getDebugLoc();
if (isInt16(CalleeAmt)) {
- BuildMI(MBB, I, TII.get(ADDIInstr), StackReg).addReg(StackReg).
+ BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
addImm(CalleeAmt);
} else {
MachineBasicBlock::iterator MBBI = I;
- BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
.addImm(CalleeAmt >> 16);
- BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
.addReg(TmpReg, false, false, true)
.addImm(CalleeAmt & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(ADDInstr))
+ BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
.addReg(StackReg)
.addReg(StackReg)
.addReg(TmpReg);
@@ -481,6 +483,7 @@
MachineFrameInfo *MFI = MF.getFrameInfo();
// Determine whether 64-bit pointers are used.
bool LP64 = Subtarget.isPPC64();
+ DebugLoc dl = MI.getDebugLoc();
// Get the maximum call stack size.
unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
@@ -511,20 +514,20 @@
Reg = PPC::R0;
if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
- BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
.addReg(PPC::R31)
.addImm(FrameSize);
} else if (LP64) {
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
- BuildMI(MBB, II, TII.get(PPC::LD), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
.addImm(0)
.addReg(PPC::X1);
else
- BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
+ BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
.addImm(0)
.addReg(PPC::X1);
} else {
- BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
.addImm(0)
.addReg(PPC::R1);
}
@@ -533,39 +536,39 @@
// address of new allocated space.
if (LP64) {
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
- BuildMI(MBB, II, TII.get(PPC::STDUX))
+ BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(Reg, false, false, true)
.addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg());
else
- BuildMI(MBB, II, TII.get(PPC::STDUX))
+ BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
.addReg(PPC::X0, false, false, true)
.addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
- BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
.addReg(PPC::X1)
.addImm(maxCallFrameSize);
else
// Implicitly kill the register.
- BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
.addReg(PPC::X1)
.addImm(maxCallFrameSize)
.addReg(MI.getOperand(1).getReg(), false, true, true);
} else {
- BuildMI(MBB, II, TII.get(PPC::STWUX))
+ BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
.addReg(Reg, false, false, true)
.addReg(PPC::R1)
.addReg(MI.getOperand(1).getReg());
if (!MI.getOperand(1).isKill())
- BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
.addReg(PPC::R1)
.addImm(maxCallFrameSize);
else
// Implicitly kill the register.
- BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
+ BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
.addReg(PPC::R1)
.addImm(maxCallFrameSize)
.addReg(MI.getOperand(1).getReg(), false, true, true);
@@ -590,6 +593,7 @@
MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
// Get the instruction's basic block.
MachineBasicBlock &MBB = *MI.getParent();
+ DebugLoc dl = MI.getDebugLoc();
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
@@ -599,10 +603,10 @@
// We need to store the CR in the low 4-bits of the saved value. First, issue
// an MFCR to save all of the CRBits. Add an implicit kill of the CR.
if (!MI.getOperand(0).isKill())
- BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
+ BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg);
else
// Implicitly kill the CR register.
- BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
.addReg(MI.getOperand(0).getReg(), false, true, true);
// If the saved register wasn't CR0, shift the bits left so that they are in
@@ -610,13 +614,13 @@
unsigned SrcReg = MI.getOperand(0).getReg();
if (SrcReg != PPC::CR0)
// rlwinm rA, rA, ShiftBits, 0, 31.
- BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
+ BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
.addReg(Reg, false, false, true)
.addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
.addImm(0)
.addImm(31);
- addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
+ addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
.addReg(Reg, false, false, MI.getOperand(1).getImm()),
FrameIndex);
@@ -636,6 +640,7 @@
MachineFunction &MF = *MBB.getParent();
// Get the frame info.
MachineFrameInfo *MFI = MF.getFrameInfo();
+ DebugLoc dl = MI.getDebugLoc();
// Find out which operand is the frame index.
unsigned FIOperandNo = 0;
@@ -727,9 +732,9 @@
SReg = PPC::R0;
// Insert a set of rA with the full offset value before the ld, st, or add
- BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
+ BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
.addImm(Offset >> 16);
- BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
+ BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
.addReg(SReg, false, false, true)
.addImm(Offset);
@@ -815,6 +820,7 @@
// transform this into the appropriate ORI instruction.
static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
MachineFunction *MF = MI->getParent()->getParent();
+ DebugLoc dl = MI->getDebugLoc();
unsigned UsedRegMask = 0;
for (unsigned i = 0; i != 32; ++i)
@@ -850,33 +856,33 @@
if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
if (DstReg != SrcReg)
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(SrcReg)
.addImm(UsedRegMask);
else
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(SrcReg, false, false, true)
.addImm(UsedRegMask);
} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
if (DstReg != SrcReg)
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg)
.addImm(UsedRegMask >> 16);
else
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg, false, false, true)
.addImm(UsedRegMask >> 16);
} else {
if (DstReg != SrcReg)
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg)
.addImm(UsedRegMask >> 16);
else
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg, false, false, true)
.addImm(UsedRegMask >> 16);
- BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
+ BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
.addReg(DstReg, false, false, true)
.addImm(UsedRegMask & 0xFFFF);
}
@@ -997,6 +1003,7 @@
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
!MF.getFunction()->doesNotThrow() ||
UnwindTablesMandatory;
@@ -1037,31 +1044,31 @@
if (IsPPC64) {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::STD))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
.addReg(PPC::X31)
.addImm(FPOffset/4)
.addReg(PPC::X1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::STD))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
.addReg(PPC::X0)
.addImm(LROffset / 4)
.addReg(PPC::X1);
} else {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::STW))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
.addReg(PPC::R31)
.addImm(FPOffset)
.addReg(PPC::R1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::STW))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
.addReg(PPC::R0)
.addImm(LROffset)
.addReg(PPC::R1);
@@ -1077,7 +1084,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer: r1 += NegFrameSize.
@@ -1088,30 +1095,30 @@
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
- BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R1)
.addImm(0)
.addImm(32 - Log2_32(MaxAlign))
.addImm(31);
- BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
.addReg(PPC::R0, false, false, true)
.addImm(NegFrameSize);
- BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
.addReg(PPC::R1)
.addReg(PPC::R1)
.addReg(PPC::R0);
} else if (isInt16(NegFrameSize)) {
- BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
.addReg(PPC::R1)
.addImm(NegFrameSize)
.addReg(PPC::R1);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
.addImm(NegFrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
.addReg(PPC::R0, false, false, true)
.addImm(NegFrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
.addReg(PPC::R1)
.addReg(PPC::R1)
.addReg(PPC::R0);
@@ -1121,29 +1128,29 @@
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
- BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
.addReg(PPC::X1)
.addImm(0)
.addImm(64 - Log2_32(MaxAlign));
- BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
.addReg(PPC::X0)
.addImm(NegFrameSize);
- BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
.addReg(PPC::X1)
.addReg(PPC::X1)
.addReg(PPC::X0);
} else if (isInt16(NegFrameSize)) {
- BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
.addReg(PPC::X1)
.addImm(NegFrameSize / 4)
.addReg(PPC::X1);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
.addImm(NegFrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
.addReg(PPC::X0, false, false, true)
.addImm(NegFrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
.addReg(PPC::X1)
.addReg(PPC::X1)
.addReg(PPC::X0);
@@ -1186,7 +1193,7 @@
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));
@@ -1197,11 +1204,11 @@
// If there is a frame pointer, copy R1 into R31
if (HasFP) {
if (!IsPPC64) {
- BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
.addReg(PPC::R1)
.addReg(PPC::R1);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
.addReg(PPC::X1)
.addReg(PPC::X1);
}
@@ -1212,6 +1219,7 @@
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
unsigned RetOpcode = MBBI->getOpcode();
+ DebugLoc dl = DebugLoc::getUnknownLoc();
assert( (RetOpcode == PPC::BLR ||
RetOpcode == PPC::TCRETURNri ||
@@ -1274,73 +1282,75 @@
// value of R31 in this case.
if (FI->hasFastCall() && isInt16(FrameSize)) {
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
.addReg(PPC::R31).addImm(FrameSize);
} else if(FI->hasFastCall()) {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
.addImm(FrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
.addReg(PPC::R0, false, false, true)
.addImm(FrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::ADD4))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
.addReg(PPC::R1)
.addReg(PPC::R31)
.addReg(PPC::R0);
} else if (isInt16(FrameSize) &&
(!ALIGN_STACK || TargetAlign >= MaxAlign) &&
!MFI->hasVarSizedObjects()) {
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
.addReg(PPC::R1).addImm(FrameSize);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
+ .addImm(0).addReg(PPC::R1);
}
} else {
if (FI->hasFastCall() && isInt16(FrameSize)) {
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
.addReg(PPC::X31).addImm(FrameSize);
} else if(FI->hasFastCall()) {
- BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
.addImm(FrameSize >> 16);
- BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
.addReg(PPC::X0, false, false, true)
.addImm(FrameSize & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(PPC::ADD8))
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
.addReg(PPC::X1)
.addReg(PPC::X31)
.addReg(PPC::X0);
} else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
!MFI->hasVarSizedObjects()) {
- BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
.addReg(PPC::X1).addImm(FrameSize);
} else {
- BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
+ .addImm(0).addReg(PPC::X1);
}
}
}
if (IsPPC64) {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
.addImm(LROffset/4).addReg(PPC::X1);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
.addImm(FPOffset/4).addReg(PPC::X1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
} else {
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
.addImm(LROffset).addReg(PPC::R1);
if (HasFP)
- BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
.addImm(FPOffset).addReg(PPC::R1);
if (MustSaveLR)
- BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
}
// Callee pop calling convention. Pop parameter/linkage area. Used for tail
@@ -1358,15 +1368,15 @@
unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
- BuildMI(MBB, MBBI, TII.get(ADDIInstr), StackReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
.addReg(StackReg).addImm(CallerAllocatedAmt);
} else {
- BuildMI(MBB, MBBI, TII.get(LISInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
.addImm(CallerAllocatedAmt >> 16);
- BuildMI(MBB, MBBI, TII.get(ORIInstr), TmpReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
.addReg(TmpReg, false, false, true)
.addImm(CallerAllocatedAmt & 0xFFFF);
- BuildMI(MBB, MBBI, TII.get(ADDInstr))
+ BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
.addReg(StackReg)
.addReg(FPReg)
.addReg(TmpReg);
@@ -1374,31 +1384,31 @@
} else if (RetOpcode == PPC::TCRETURNdi) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILB)).
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
} else if (RetOpcode == PPC::TCRETURNri) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
assert(JumpTarget.isReg() && "Expecting register operand.");
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR));
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
} else if (RetOpcode == PPC::TCRETURNai) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
} else if (RetOpcode == PPC::TCRETURNdi8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILB8)).
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
} else if (RetOpcode == PPC::TCRETURNri8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
assert(JumpTarget.isReg() && "Expecting register operand.");
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8));
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
} else if (RetOpcode == PPC::TCRETURNai8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- BuildMI(MBB, MBBI, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
}
}
More information about the llvm-commits
mailing list