[llvm-commits] [llvm] r63978 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/

Dale Johannesen dalej at apple.com
Fri Feb 6 15:05:02 PST 2009


Author: johannes
Date: Fri Feb  6 17:05:02 2009
New Revision: 63978

URL: http://llvm.org/viewvc/llvm-project?rev=63978&view=rev
Log:
Remove more non-DebugLoc getNode variants.  Use
getCALLSEQ_{END,START} to permit passing no DebugLoc
there.  UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.


Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Feb  6 17:05:02 2009
@@ -377,15 +377,18 @@
   SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
 
   /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
-  /// a flag result (to ensure it's not CSE'd).
+  /// a flag result (to ensure it's not CSE'd).  CALLSEQ_START does not have a
+  /// useful DebugLoc.
   SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
     const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
     SDValue Ops[] = { Chain,  Op };
-    return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2);
+    return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(), 
+                   VTs, 2, Ops, 2);
   }
 
   /// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a
-  /// flag result (to ensure it's not CSE'd).
+  /// flag result (to ensure it's not CSE'd).  CALLSEQ_END does not have
+  /// a useful DebugLoc.
   SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
                            SDValue InFlag) {
     SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
@@ -394,10 +397,16 @@
     Ops.push_back(Op1);
     Ops.push_back(Op2);
     Ops.push_back(InFlag);
-    return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
+    return getNode(ISD::CALLSEQ_END, DebugLoc::getUnknownLoc(), NodeTys,
+                   &Ops[0], 
                    (unsigned)Ops.size() - (InFlag.getNode() == 0 ? 1 : 0));
   }
 
+  /// getUNDEF - Return an UNDEF node.  UNDEF does not have a useful DebugLoc.
+  SDValue getUNDEF(MVT VT) {
+    return getNode(ISD::UNDEF, DebugLoc::getUnknownLoc(), VT);
+  }
+
   /// getNode - Gets or creates the specified node.
   ///
   SDValue getNode(unsigned Opcode, MVT VT);
@@ -421,15 +430,10 @@
   SDValue getNode(unsigned Opcode, DebugLoc DL,
                   const std::vector<MVT> &ResultTys,
                   const SDValue *Ops, unsigned NumOps);
-  SDValue getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
-                  const SDValue *Ops, unsigned NumOps);
   SDValue getNode(unsigned Opcode, DebugLoc DL, const MVT *VTs, unsigned NumVTs,
                   const SDValue *Ops, unsigned NumOps);
-  SDValue getNode(unsigned Opcode, SDVTList VTs,
-                  const SDValue *Ops, unsigned NumOps);
   SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,
                   const SDValue *Ops, unsigned NumOps);
-
   SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs);
   SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N);
   SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Feb  6 17:05:02 2009
@@ -2490,7 +2490,7 @@
     return N0;
   // fold (shl x, c >= size(x)) -> undef
   if (N1C && N1C->getZExtValue() >= OpSizeInBits)
-    return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+    return DAG.getUNDEF(VT);
   // fold (shl x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
@@ -2571,7 +2571,7 @@
     return N0;
   // fold (sra x, (setge c, size(x))) -> undef
   if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
-    return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+    return DAG.getUNDEF(VT);
   // fold (sra x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
@@ -2679,7 +2679,7 @@
     return N0;
   // fold (srl x, c >= size(x)) -> undef
   if (N1C && N1C->getZExtValue() >= OpSizeInBits)
-    return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+    return DAG.getUNDEF(VT);
   // fold (srl x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
@@ -2704,7 +2704,7 @@
     // Shifting in all undef bits?
     MVT SmallVT = N0.getOperand(0).getValueType();
     if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
-      return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
+      return DAG.getUNDEF(VT);
 
     SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
                                      N0.getOperand(0), N1);
@@ -3909,7 +3909,7 @@
       }
       
       if (EltIsUndef)
-        Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT));
+        Ops.push_back(DAG.getUNDEF(DstEltVT));
       else
         Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
     }
@@ -3929,7 +3929,7 @@
   for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
     if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
       for (unsigned j = 0; j != NumOutputsPerInput; ++j)
-        Ops.push_back(DAG.getNode(ISD::UNDEF, BV->getDebugLoc(), DstEltVT));
+        Ops.push_back(DAG.getUNDEF(DstEltVT));
       continue;
     }
 
@@ -4810,16 +4810,14 @@
       // Indexed loads.
       assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
       if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
-        SDValue Undef = DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                                    N->getValueType(0));
+        SDValue Undef = DAG.getUNDEF(N->getValueType(0));
         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
         DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
         DOUT << " and 2 other values\n";
         WorkListRemover DeadNodes(*this);
         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
-                                      DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                                                  N->getValueType(1)),
+                                      DAG.getUNDEF(N->getValueType(1)),
                                       &DeadNodes);
         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
         removeFromWorkList(N);
@@ -5240,9 +5238,7 @@
     SmallVector<SDValue, 8> BuildVecIndices;
     for (unsigned i = 0; i != NumInScalars; ++i) {
       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
-        BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF,
-                                              N->getDebugLoc(),
-                                              TLI.getPointerTy()));
+        BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy()));
         continue;
       }
       
@@ -5273,8 +5269,7 @@
     } else {
       // Use an undef build_vector as input for the second operand.
       std::vector<SDValue> UnOps(NumInScalars,
-                                 DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                                             EltType));
+                                 DAG.getUNDEF(EltType));
       Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
                            &UnOps[0], UnOps.size());
       AddToWorkList(Ops[1].getNode());
@@ -5430,8 +5425,7 @@
     AddToWorkList(ShufMask.getNode());
     return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
                        N->getValueType(0), N0,
-                       DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                                   N->getValueType(0)),
+                       DAG.getUNDEF(N->getValueType(0)),
                        ShufMask);
   }
  

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Feb  6 17:05:02 2009
@@ -345,8 +345,7 @@
         SDValue InOp = Mask.getOperand(i);
         for (unsigned j = 0; j != NumEltsGrowth; ++j) {
           if (InOp.getOpcode() == ISD::UNDEF)
-            Ops.push_back(DAG.getNode(ISD::UNDEF, 
-                                      InOp.getNode()->getDebugLoc(), EltVT));
+            Ops.push_back(DAG.getUNDEF(EltVT));
           else {
             unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
             Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
@@ -1738,7 +1737,7 @@
       for (unsigned i = 0; i != NumElems; ++i) {
         SDValue Arg = Mask.getOperand(i);
         if (Arg.getOpcode() == ISD::UNDEF) {
-          Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+          Ops.push_back(DAG.getUNDEF(EltVT));
         } else {
           assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
           unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
@@ -2896,7 +2895,7 @@
                                   Node->getValueType(0));
         Tmp2 = Tmp1.getValue(1);
       } else {
-        Tmp1 = DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0));
+        Tmp1 = DAG.getUNDEF(Node->getValueType(0));
         Tmp2 = Node->getOperand(0);
       }
       break;
@@ -4532,7 +4531,7 @@
     assert(0 && "Do not know how to promote this operator!");
     abort();
   case ISD::UNDEF:
-    Result = DAG.getNode(ISD::UNDEF, dl, NVT);
+    Result = DAG.getUNDEF(NVT);
     break;
   case ISD::Constant:
     if (VT != MVT::i1)
@@ -5514,7 +5513,7 @@
   if (isOnlyLowElement) {
     // If the low element is an undef too, then this whole things is an undef.
     if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
-      return DAG.getNode(ISD::UNDEF, dl, Node->getValueType(0));
+      return DAG.getUNDEF(Node->getValueType(0));
     // Otherwise, turn this into a scalar_to_vector node.
     return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
                        Node->getOperand(0));
@@ -5564,7 +5563,7 @@
       // Return shuffle(LowValVec, undef, <0,0,0,0>)
       return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, 
                          Node->getValueType(0), LowValVec,
-                         DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
+                         DAG.getUNDEF(Node->getValueType(0)),
                          SplatMask);
     }
   }
@@ -5602,7 +5601,7 @@
       if (Val2.getOpcode() != ISD::UNDEF)
         MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
       else
-        MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, dl, MaskEltVT);
+        MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
     
     SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
                                         &MaskVec[0], MaskVec.size());
@@ -6483,8 +6482,8 @@
     Lo  = ExpandEXTRACT_VECTOR_ELT(Op);
     return ExpandOp(Lo, Lo, Hi);
   case ISD::UNDEF:
-    Lo = DAG.getNode(ISD::UNDEF, dl, NVT);
-    Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+    Lo = DAG.getUNDEF(NVT);
+    Hi = DAG.getUNDEF(NVT);
     break;
   case ISD::Constant: {
     unsigned NVTBits = NVT.getSizeInBits();
@@ -6677,7 +6676,7 @@
         Hi = DAG.getConstant(0, NVT);
       } else /* if (ExtType == ISD::EXTLOAD) */ {
         // The high part is undefined.
-        Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+        Hi = DAG.getUNDEF(NVT);
       }
     }
     break;
@@ -6720,7 +6719,7 @@
     // The low part is any extension of the input (which degenerates to a copy).
     Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
     // The high part is undefined.
-    Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+    Hi = DAG.getUNDEF(NVT);
     break;
   case ISD::SIGN_EXTEND: {
     // The low part is just a sign extension of the input (which degenerates to
@@ -7516,8 +7515,8 @@
 #endif
     assert(0 && "Unhandled operation in SplitVectorOp!");
   case ISD::UNDEF:
-    Lo = DAG.getNode(ISD::UNDEF, dl, NewVT_Lo);
-    Hi = DAG.getNode(ISD::UNDEF, dl, NewVT_Hi);
+    Lo = DAG.getUNDEF(NewVT_Lo);
+    Hi = DAG.getUNDEF(NewVT_Hi);
     break;
   case ISD::BUILD_PAIR:
     Lo = Node->getOperand(0);
@@ -7554,7 +7553,7 @@
     for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
       SDValue IdxNode = Mask.getOperand(i);
       if (IdxNode.getOpcode() == ISD::UNDEF) {
-        Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
+        Ops.push_back(DAG.getUNDEF(NewEltVT));
         continue;
       }
       unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
@@ -7572,7 +7571,7 @@
     for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
       SDValue IdxNode = Mask.getOperand(i);
       if (IdxNode.getOpcode() == ISD::UNDEF) {
-        Ops.push_back(DAG.getNode(ISD::UNDEF, dl, NewEltVT));
+        Ops.push_back(DAG.getUNDEF(NewEltVT));
         continue;
       }
       unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
@@ -7773,7 +7772,7 @@
     bool isVolatile = LD->isVolatile();
 
     assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
-    SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
+    SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
 
     MVT MemNewEltVT = MemoryVT.getVectorElementType();
     MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
@@ -7930,7 +7929,7 @@
     bool isVolatile = LD->isVolatile();
 
     assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
-    SDValue Offset = DAG.getNode(ISD::UNDEF, dl, Ptr.getValueType());
+    SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
     
     Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
                          NewVT, Ch, Ptr, Offset, SV, SVOffset,
@@ -8052,13 +8051,13 @@
     assert(0 && "Unexpected operation in WidenVectorOp!");
     break;
   case ISD::UNDEF:
-    Result = DAG.getNode(ISD::UNDEF, dl, WidenVT);
+    Result = DAG.getUNDEF(WidenVT);
     break;
   case ISD::BUILD_VECTOR: {
     // Build a vector with undefined for the new nodes
     SDValueVector NewOps(Node->op_begin(), Node->op_end());
     for (unsigned i = NumElts; i < NewNumElts; ++i) {
-      NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EVT));
+      NewOps.push_back(DAG.getUNDEF(EVT));
     }
     Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, 
                          &NewOps[0], NewOps.size());    
@@ -8095,7 +8094,7 @@
       }
     }
     for (unsigned i = NumElts; i < NewNumElts; ++i) {
-      NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, PVT));
+      NewOps.push_back(DAG.getUNDEF(PVT));
     }
     
     SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl, 
@@ -8140,7 +8139,7 @@
              "can not widen bit convert that are not multiple of element type");
       unsigned NewNumElts = WidenSize / InSize;
       SmallVector<SDValue, 16> Ops(NewNumElts);
-      SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+      SDValue UndefVal = DAG.getUNDEF(InVT);
       Ops[0] = Tmp1;
       for (unsigned i = 1; i < NewNumElts; ++i)
         Ops[i] = UndefVal;
@@ -8269,7 +8268,7 @@
     // We could widen on a multiple of the incoming operand if necessary.
     unsigned NumConcat = NewNumElts / NumElts;
     assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
-    SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
+    SDValue UndefVal = DAG.getUNDEF(VT);
     SmallVector<SDValue, 8> MOps;
     MOps.push_back(Op);
     for (unsigned i = 1; i != NumConcat; ++i) {
@@ -8299,7 +8298,7 @@
     } else if (NewNumElts % NumElts == 0) {
       // Widen the extracted subvector.
       unsigned NumConcat = NewNumElts / NumElts;
-      SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, VT);
+      SDValue UndefVal = DAG.getUNDEF(VT);
       SmallVector<SDValue, 8> MOps;
       MOps.push_back(Op);
       for (unsigned i = 1; i != NumConcat; ++i) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Feb  6 17:05:02 2009
@@ -592,8 +592,7 @@
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
-  return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                     TLI.getTypeToTransformTo(N->getValueType(0)));
+  return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
@@ -1314,7 +1313,7 @@
   if (Op.getValueType().bitsLE(NVT)) {
     // The low part is any extension of the input (which degenerates to a copy).
     Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
-    Hi = DAG.getNode(ISD::UNDEF, dl, NVT);   // The high part is undefined.
+    Hi = DAG.getUNDEF(NVT);   // The high part is undefined.
   } else {
     // For example, extension of an i48 to an i64.  The operand type necessarily
     // promotes to the result type, so will end up being expanded too.
@@ -1495,7 +1494,7 @@
     } else {
       assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
       // The high part is undefined.
-      Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
+      Hi = DAG.getUNDEF(NVT);
     }
   } else if (TLI.isLittleEndian()) {
     // Little-endian - low bits are at low addresses.

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Fri Feb  6 17:05:02 2009
@@ -332,7 +332,7 @@
   unsigned NumElts = VT.getVectorNumElements();
   SmallVector<SDValue, 16> Ops(NumElts);
   Ops[0] = N->getOperand(0);
-  SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, Ops[0].getValueType());
+  SDValue UndefVal = DAG.getUNDEF(Ops[0].getValueType());
   for (unsigned i = 1; i < NumElts; ++i)
     Ops[i] = UndefVal;
   return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
@@ -433,6 +433,6 @@
   MVT LoVT, HiVT;
   DebugLoc dl = N->getDebugLoc();
   GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
-  Lo = DAG.getNode(ISD::UNDEF, dl, LoVT);
-  Hi = DAG.getNode(ISD::UNDEF, dl, HiVT);
+  Lo = DAG.getUNDEF(LoVT);
+  Hi = DAG.getUNDEF(HiVT);
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Feb  6 17:05:02 2009
@@ -164,8 +164,7 @@
                                N->getExtensionType(),
                                N->getValueType(0).getVectorElementType(),
                                N->getChain(), N->getBasePtr(),
-                               DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                                           N->getBasePtr().getValueType()),
+                               DAG.getUNDEF(N->getBasePtr().getValueType()),
                                N->getSrcValue(), N->getSrcValueOffset(),
                                N->getMemoryVT().getVectorElementType(),
                                N->isVolatile(), N->getAlignment());
@@ -203,16 +202,14 @@
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
-  return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                     N->getValueType(0).getVectorElementType());
+  return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
 }
 
 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
   // Figure out if the scalar is the LHS or RHS and return it.
   SDValue Arg = N->getOperand(2).getOperand(0);
   if (Arg.getOpcode() == ISD::UNDEF)
-    return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
-                       N->getValueType(0).getVectorElementType());
+    return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
   unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
   return GetScalarizedVector(N->getOperand(Op));
 }
@@ -632,7 +629,7 @@
   DebugLoc dl = N->getDebugLoc();
   GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
   Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
-  Hi = DAG.getNode(ISD::UNDEF, dl, HiVT);
+  Hi = DAG.getUNDEF(HiVT);
 }
 
 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
@@ -645,7 +642,7 @@
   ISD::LoadExtType ExtType = LD->getExtensionType();
   SDValue Ch = LD->getChain();
   SDValue Ptr = LD->getBasePtr();
-  SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
+  SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
   const Value *SV = LD->getSrcValue();
   int SVOffset = LD->getSrcValueOffset();
   MVT MemoryVT = LD->getMemoryVT();
@@ -747,7 +744,7 @@
 
       if (Input >= array_lengthof(Inputs)) {
         // The mask element does not index into any input vector.
-        Ops.push_back(DAG.getNode(ISD::UNDEF, dl, IdxVT));
+        Ops.push_back(DAG.getUNDEF(IdxVT));
         continue;
       }
 
@@ -795,7 +792,7 @@
 
         if (Input >= array_lengthof(Inputs)) {
           // The mask element is "undef" or indexes off the end of the input.
-          Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+          Ops.push_back(DAG.getUNDEF(EltVT));
           continue;
         }
 
@@ -811,7 +808,7 @@
       Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, &Ops[0], Ops.size());
     } else if (InputUsed[0] == -1U) {
       // No input vectors were used!  The result is undefined.
-      Output = DAG.getNode(ISD::UNDEF, dl, NewVT);
+      Output = DAG.getUNDEF(NewVT);
     } else {
       // At least one input vector was used.  Create a new shuffle vector.
       SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
@@ -820,7 +817,7 @@
       SDValue Op0 = Inputs[InputUsed[0]];
       // If only one input was used, use an undefined vector for the other.
       SDValue Op1 = InputUsed[1] == -1U ?
-        DAG.getNode(ISD::UNDEF, dl, NewVT) : Inputs[InputUsed[1]];
+        DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
       Output = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, Op0, Op1, NewMask);
     }
 
@@ -1075,7 +1072,7 @@
       for (unsigned i = 0; i < MaskLength; ++i) {
         SDValue Arg = Mask.getOperand(i);
         if (Arg.getOpcode() == ISD::UNDEF) {
-          Ops[i] = DAG.getNode(ISD::UNDEF, dl, OpVT);
+          Ops[i] = DAG.getUNDEF(OpVT);
         } else {
           uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
           Ops[i] = DAG.getConstant(Idx, OpVT);
@@ -1219,7 +1216,7 @@
       unsigned NumConcat = WidenNumElts/InVTNumElts;
       SmallVector<SDValue, 16> Ops(NumConcat);
       Ops[0] = InOp;
-      SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+      SDValue UndefVal = DAG.getUNDEF(InVT);
       for (unsigned i = 1; i != NumConcat; ++i)
         Ops[i] = UndefVal;
       return DAG.getNode(Opcode, dl, WidenVT,
@@ -1245,7 +1242,7 @@
                          DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
                                      DAG.getIntPtrConstant(i)));
 
-  SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+  SDValue UndefVal = DAG.getUNDEF(EltVT);
   for (; i < WidenNumElts; ++i)
     Ops[i] = UndefVal;
 
@@ -1337,7 +1334,7 @@
       // and then widening it. To avoid this, we widen the input only if
       // it results in a legal type.
       SmallVector<SDValue, 16> Ops(NewNumElts);
-      SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
+      SDValue UndefVal = DAG.getUNDEF(InVT);
       Ops[0] = InOp;
       for (unsigned i = 1; i < NewNumElts; ++i)
         Ops[i] = UndefVal;
@@ -1380,7 +1377,7 @@
   SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
   NewOps.reserve(WidenNumElts);
   for (unsigned i = NumElts; i < WidenNumElts; ++i)
-    NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+    NewOps.push_back(DAG.getUNDEF(EltVT));
 
   return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
 }
@@ -1398,7 +1395,7 @@
       // Add undef vectors to widen to correct length.
       unsigned NumConcat = WidenVT.getVectorNumElements() /
                            InVT.getVectorNumElements();
-      SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+      SDValue UndefVal = DAG.getUNDEF(InVT);
       SmallVector<SDValue, 16> Ops(NumConcat);
       for (unsigned i=0; i < NumOperands; ++i)
         Ops[i] = N->getOperand(i);
@@ -1451,7 +1448,7 @@
         Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
                                  DAG.getIntPtrConstant(j));
   }
-  SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+  SDValue UndefVal = DAG.getUNDEF(EltVT);
   for (; Idx < WidenNumElts; ++Idx)
     Ops[Idx] = UndefVal;
   return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
@@ -1495,7 +1492,7 @@
       unsigned NumConcat = WidenNumElts/InVTNumElts;
       SmallVector<SDValue, 16> Ops(NumConcat);
       Ops[0] = InOp;
-      SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+      SDValue UndefVal = DAG.getUNDEF(InVT);
       for (unsigned i = 1; i != NumConcat; ++i) {
         Ops[i] = UndefVal;
       }
@@ -1528,7 +1525,7 @@
                                         SatOp, CvtCode);
   }
 
-  SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+  SDValue UndefVal = DAG.getUNDEF(EltVT);
   for (; i < WidenNumElts; ++i)
     Ops[i] = UndefVal;
 
@@ -1582,7 +1579,7 @@
     }
   }
 
-  SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+  SDValue UndefVal = DAG.getUNDEF(EltVT);
   for (; i < WidenNumElts; ++i)
     Ops[i] = UndefVal;
   return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
@@ -1638,7 +1635,7 @@
     }
 
     // Fill the rest with undefs
-    SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+    SDValue UndefVal = DAG.getUNDEF(EltVT);
     for (; i != WidenNumElts; ++i)
       Ops[i] = UndefVal;
 
@@ -1706,7 +1703,7 @@
 
 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
  MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
- return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), WidenVT);
+ return DAG.getUNDEF(WidenVT);
 }
 
 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
@@ -1737,7 +1734,7 @@
     }
   }
   for (unsigned i = NumElts; i < WidenNumElts; ++i)
-    MaskOps[i] = DAG.getNode(ISD::UNDEF, dl, IdxVT);
+    MaskOps[i] = DAG.getUNDEF(IdxVT);
   SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
                                 MVT::getVectorVT(IdxVT, WidenNumElts),
                                 &MaskOps[0], WidenNumElts);
@@ -2158,7 +2155,7 @@
   if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
     unsigned NumConcat = WidenNumElts / InNumElts;
     SmallVector<SDValue, 16> Ops(NumConcat);
-    SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
+    SDValue UndefVal = DAG.getUNDEF(InVT);
     Ops[0] = InOp;
     for (unsigned i = 1; i != NumConcat; ++i)
       Ops[i] = UndefVal;
@@ -2179,7 +2176,7 @@
     Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
                            DAG.getIntPtrConstant(Idx));
 
-  SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
+  SDValue UndefVal = DAG.getUNDEF(EltVT);
   for ( ; Idx < WidenNumElts; ++Idx)
     Ops[Idx] = UndefVal;
   return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Feb  6 17:05:02 2009
@@ -1366,29 +1366,29 @@
       switch (Cond) {
       default: break;
       case ISD::SETEQ:  if (R==APFloat::cmpUnordered) 
-                          return getNode(ISD::UNDEF, dl, VT);
+                          return getUNDEF(VT);
                         // fall through
       case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
       case ISD::SETNE:  if (R==APFloat::cmpUnordered) 
-                          return getNode(ISD::UNDEF, dl, VT);
+                          return getUNDEF(VT);
                         // fall through
       case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
                                            R==APFloat::cmpLessThan, VT);
       case ISD::SETLT:  if (R==APFloat::cmpUnordered) 
-                          return getNode(ISD::UNDEF, dl, VT);
+                          return getUNDEF(VT);
                         // fall through
       case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
       case ISD::SETGT:  if (R==APFloat::cmpUnordered) 
-                          return getNode(ISD::UNDEF, dl, VT);
+                          return getUNDEF(VT);
                         // fall through
       case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
       case ISD::SETLE:  if (R==APFloat::cmpUnordered) 
-                          return getNode(ISD::UNDEF, dl, VT);
+                          return getUNDEF(VT);
                         // fall through
       case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
                                            R==APFloat::cmpEqual, VT);
       case ISD::SETGE:  if (R==APFloat::cmpUnordered) 
-                          return getNode(ISD::UNDEF, dl, VT);
+                          return getUNDEF(VT);
                         // fall through
       case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
                                            R==APFloat::cmpEqual, VT);
@@ -2133,7 +2133,7 @@
   SDValue PermMask = N->getOperand(2);
   SDValue Idx = PermMask.getOperand(i);
   if (Idx.getOpcode() == ISD::UNDEF)
-    return getNode(ISD::UNDEF, dl, VT.getVectorElementType());
+    return getUNDEF(VT.getVectorElementType());
   unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
   unsigned NumElems = PermMask.getNumOperands();
   SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
@@ -2147,7 +2147,7 @@
   }
   if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
     return (Index == 0) ? V.getOperand(0)
-                      : getNode(ISD::UNDEF, dl, VT.getVectorElementType());
+                      : getUNDEF(VT.getVectorElementType());
   if (V.getOpcode() == ISD::BUILD_VECTOR)
     return V.getOperand(Index);
   if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
@@ -2281,7 +2281,7 @@
            Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
     if (Operand.getValueType() == VT) return Operand;  // noop conversion.
     if (Operand.getOpcode() == ISD::UNDEF)
-      return getNode(ISD::UNDEF, DL, VT);
+      return getUNDEF(VT);
     break;
   case ISD::SIGN_EXTEND:
     assert(VT.isInteger() && Operand.getValueType().isInteger() &&
@@ -2339,14 +2339,14 @@
     if (OpOpcode == ISD::BIT_CONVERT)  // bitconv(bitconv(x)) -> bitconv(x)
       return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0));
     if (OpOpcode == ISD::UNDEF)
-      return getNode(ISD::UNDEF, DL, VT);
+      return getUNDEF(VT);
     break;
   case ISD::SCALAR_TO_VECTOR:
     assert(VT.isVector() && !Operand.getValueType().isVector() &&
            VT.getVectorElementType() == Operand.getValueType() &&
            "Illegal SCALAR_TO_VECTOR node!");
     if (OpOpcode == ISD::UNDEF)
-      return getNode(ISD::UNDEF, DL, VT);
+      return getUNDEF(VT);
     // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
     if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
         isa<ConstantSDNode>(Operand.getOperand(1)) &&
@@ -2575,7 +2575,7 @@
   case ISD::EXTRACT_VECTOR_ELT:
     // EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
     if (N1.getOpcode() == ISD::UNDEF)
-      return getNode(ISD::UNDEF, DL, VT);
+      return getUNDEF(VT);
       
     // EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
     // expanding copies of large vectors from registers.
@@ -3569,7 +3569,7 @@
                               SDValue Chain, SDValue Ptr,
                               const Value *SV, int SVOffset,
                               bool isVolatile, unsigned Alignment) {
-  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  SDValue Undef = getUNDEF(Ptr.getValueType());
   return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
                  SV, SVOffset, VT, isVolatile, Alignment);
 }
@@ -3579,7 +3579,7 @@
                                  const Value *SV,
                                  int SVOffset, MVT EVT,
                                  bool isVolatile, unsigned Alignment) {
-  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  SDValue Undef = getUNDEF(Ptr.getValueType());
   return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
                  SV, SVOffset, EVT, isVolatile, Alignment);
 }
@@ -3605,7 +3605,7 @@
     Alignment = getMVTAlignment(VT);
 
   SDVTList VTs = getVTList(MVT::Other);
-  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  SDValue Undef = getUNDEF(Ptr.getValueType());
   SDValue Ops[] = { Chain, Val, Ptr, Undef };
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3640,7 +3640,7 @@
     Alignment = getMVTAlignment(VT);
 
   SDVTList VTs = getVTList(MVT::Other);
-  SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
+  SDValue Undef = getUNDEF(Ptr.getValueType());
   SDValue Ops[] = { Chain, Val, Ptr, Undef };
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3775,12 +3775,6 @@
                  Ops, NumOps);
 }
 
-SDValue SelectionDAG::getNode(unsigned Opcode,
-                              const MVT *VTs, unsigned NumVTs,
-                              const SDValue *Ops, unsigned NumOps) {
-  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTs, NumVTs, Ops, NumOps);
-}
-
 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
                               const MVT *VTs, unsigned NumVTs,
                               const SDValue *Ops, unsigned NumOps) {
@@ -3789,11 +3783,6 @@
   return getNode(Opcode, DL, makeVTList(VTs, NumVTs), Ops, NumOps);
 }  
   
-SDValue SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
-                              const SDValue *Ops, unsigned NumOps) {
-  return getNode(Opcode, DebugLoc::getUnknownLoc(), VTList, Ops, NumOps);
-}
-
 SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList,
                               const SDValue *Ops, unsigned NumOps) {
   if (VTList.NumVTs == 1)

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Fri Feb  6 17:05:02 2009
@@ -867,7 +867,7 @@
 
     if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
         !V->getType()->isAggregateType())
-      return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
+      return N = DAG.getUNDEF(VT);
 
     if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
       visit(CE->getOpcode(), *CE);
@@ -901,7 +901,7 @@
       for (unsigned i = 0; i != NumElts; ++i) {
         MVT EltVT = ValueVTs[i];
         if (isa<UndefValue>(C))
-          Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
+          Constants[i] = DAG.getUNDEF(EltVT);
         else if (EltVT.isFloatingPoint())
           Constants[i] = DAG.getConstantFP(0, EltVT);
         else
@@ -926,7 +926,7 @@
 
       SDValue Op;
       if (isa<UndefValue>(C))
-        Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT);
+        Op = DAG.getUNDEF(EltVT);
       else if (EltVT.isFloatingPoint())
         Op = DAG.getConstantFP(0, EltVT);
       else
@@ -2438,7 +2438,7 @@
 
     // Pad both vectors with undefs to make them the same length as the mask.
     unsigned NumConcat = MaskNumElts / SrcNumElts;
-    SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT);
+    SDValue UndefVal = DAG.getUNDEF(SrcVT);
 
     SDValue* MOps1 = new SDValue[NumConcat];
     SDValue* MOps2 = new SDValue[NumConcat];
@@ -2540,8 +2540,7 @@
     }
 
     if (RangeUse[0] == 0 && RangeUse[0] == 0) {
-      setValue(&I, DAG.getNode(ISD::UNDEF, 
-                          getCurDebugLoc(), VT));  // Vectors are not used.
+      setValue(&I, DAG.getUNDEF(VT));  // Vectors are not used.
       return;
     }
     else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
@@ -2549,7 +2548,7 @@
       for (int Input=0; Input < 2; ++Input) {
         SDValue& Src = Input == 0 ? Src1 : Src2;
         if (RangeUse[Input] == 0) {
-          Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT);
+          Src = DAG.getUNDEF(VT);
         } else {
           Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
                             Src, DAG.getIntPtrConstant(StartIdx[Input]));
@@ -2589,7 +2588,7 @@
   for (int i = 0; i != MaskNumElts; ++i) {
     SDValue Arg = Mask.getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) {
-      Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT));
+      Ops.push_back(DAG.getUNDEF(EltVT));
     } else {
       assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
       int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
@@ -2631,18 +2630,15 @@
   unsigned i = 0;
   // Copy the beginning value(s) from the original aggregate.
   for (; i != LinearIndex; ++i)
-    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), 
-                                        AggValueVTs[i]) :
+    Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
                 SDValue(Agg.getNode(), Agg.getResNo() + i);
   // Copy values from the inserted value(s).
   for (; i != LinearIndex + NumValValues; ++i)
-    Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), 
-                                        AggValueVTs[i]) :
+    Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
                 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
   // Copy remaining value(s) from the original aggregate.
   for (; i != NumAggValues; ++i)
-    Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), 
-                                        AggValueVTs[i]) :
+    Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
                 SDValue(Agg.getNode(), Agg.getResNo() + i);
 
   setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 
@@ -2670,8 +2666,7 @@
   for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
     Values[i - LinearIndex] =
       OutOfUndef ?
-        DAG.getNode(ISD::UNDEF, getCurDebugLoc(), 
-                    Agg.getNode()->getValueType(Agg.getResNo() + i)) :
+        DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
         SDValue(Agg.getNode(), Agg.getResNo() + i);
 
   setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Feb  6 17:05:02 2009
@@ -780,8 +780,7 @@
   } else if (DemandedMask == 0) {   
     // Not demanding any bits from Op.
     if (Op.getOpcode() != ISD::UNDEF)
-      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, dl,
-                                               Op.getValueType()));
+      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
     return false;
   } else if (Depth == 6) {        // Limit search depth.
     return false;
@@ -1704,7 +1703,7 @@
       case 1:  // Known true.
         return DAG.getConstant(1, VT);
       case 2:  // Undefined.
-        return DAG.getNode(ISD::UNDEF, VT);
+        return DAG.getUNDEF(VT);
       }
     }
     

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Feb  6 17:05:02 2009
@@ -581,8 +581,7 @@
   }
   if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
     // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
-    Chain = DAG.getCopyToReg(Chain, dl, ARM::LR,
-                             DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
+    Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
     InFlag = Chain.getValue(1);
   }
 

Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Fri Feb  6 17:05:02 2009
@@ -882,6 +882,7 @@
                                         SelectionDAG &DAG) {
   CallSDNode *TheCall = dyn_cast<CallSDNode>(Op);
   unsigned NumOps = TheCall->getNumArgs();
+  DebugLoc dl = TheCall->getDebugLoc();
   std::string Name;
   SDValue Arg, StoreAt;
   MVT ArgVT;
@@ -917,7 +918,7 @@
     Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8));
     Ops.push_back(InFlag);
 
-    StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, Tys, &Ops[0], Ops.size());
+    StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size());
 
     Chain = getChain(StoreRet);
     InFlag = getOutFlag(StoreRet);
@@ -1192,15 +1193,16 @@
                                                     SelectionDAG &DAG) {
   SmallVector<SDValue, 8> ArgValues;
   unsigned NumArgs = Op.getNumOperands() - 3;
+  DebugLoc dl = Op.getDebugLoc();
 
   // Creating UNDEF nodes to meet the requirement of MERGE_VALUES node.
   for(unsigned i = 0 ; i<NumArgs ; i++) {
-    SDValue TempNode = DAG.getNode(ISD::UNDEF, Op.getNode()->getValueType(i));
+    SDValue TempNode = DAG.getUNDEF(Op.getNode()->getValueType(i));
     ArgValues.push_back(TempNode);
   }
 
   ArgValues.push_back(Op.getOperand(0));
-  return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), 
+  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 
                      &ArgValues[0],
                      ArgValues.size()).getValue(Op.getResNo());
 }

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Feb  6 17:05:02 2009
@@ -2503,15 +2503,8 @@
 
   // Emit callseq_end just before tailcall node.
   if (isTailCall) {
-    SmallVector<SDValue, 8> CallSeqOps;
-    SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
-    CallSeqOps.push_back(Chain);
-    CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true));
-    CallSeqOps.push_back(DAG.getIntPtrConstant(0, true));
-    if (InFlag.getNode())
-      CallSeqOps.push_back(InFlag);
-    Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
-                        CallSeqOps.size());
+    Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+                               DAG.getIntPtrConstant(0, true), InFlag);
     InFlag = Chain.getValue(1);
   }
 

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri Feb  6 17:05:02 2009
@@ -105,7 +105,7 @@
     case MVT::i32:
       if (I->use_empty()) {                // Argument is dead.
         if (CurArgReg < ArgRegEnd) ++CurArgReg;
-        ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
+        ArgValues.push_back(DAG.getUNDEF(ObjectVT));
       } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
         unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
         MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
@@ -142,7 +142,7 @@
     case MVT::f32:
       if (I->use_empty()) {                // Argument is dead.
         if (CurArgReg < ArgRegEnd) ++CurArgReg;
-        ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
+        ArgValues.push_back(DAG.getUNDEF(ObjectVT));
       } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
         // FP value is passed in an integer register.
         unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
@@ -165,7 +165,7 @@
       if (I->use_empty()) {                // Argument is dead.
         if (CurArgReg < ArgRegEnd) ++CurArgReg;
         if (CurArgReg < ArgRegEnd) ++CurArgReg;
-        ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
+        ArgValues.push_back(DAG.getUNDEF(ObjectVT));
       } else {
         SDValue HiVal;
         if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=63978&r1=63977&r2=63978&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Feb  6 17:05:02 2009
@@ -1624,7 +1624,7 @@
             Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
             Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
             Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
-                              DAG.getNode(ISD::UNDEF, dl, MVT::v2i64), Arg,
+                              DAG.getUNDEF(MVT::v2i64), Arg,
                               getMOVLMask(2, DAG, dl));
             break;
           }
@@ -1790,12 +1790,8 @@
   SmallVector<SDValue, 8> Ops;
 
   if (IsTailCall) {
-    Ops.push_back(Chain);
-    Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
-    Ops.push_back(DAG.getIntPtrConstant(0, true));
-    if (InFlag.getNode())
-      Ops.push_back(InFlag);
-    Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
+    Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
+                           DAG.getIntPtrConstant(0, true), InFlag);
     InFlag = Chain.getValue(1);
  
     // Returns a chain & a flag for retval copy to use.
@@ -2730,7 +2726,7 @@
   for (unsigned i = 0; i != NumElems; ++i) {
     SDValue Arg = Mask.getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) {
-      MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+      MaskVec.push_back(DAG.getUNDEF(EltVT));
       continue;
     }
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
@@ -2757,7 +2753,7 @@
   for (unsigned i = 0; i != NumElems; ++i) {
     SDValue Arg = Mask.getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) {
-      MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
+      MaskVec.push_back(DAG.getUNDEF(EltVT));
       continue;
     }
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
@@ -3067,7 +3063,7 @@
 
   V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
   SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
-                                  DAG.getNode(ISD::UNDEF, PVT), Mask);
+                                  DAG.getUNDEF(PVT), Mask);
   return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
 }
 
@@ -3109,7 +3105,7 @@
 
   V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
   SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
-                                DAG.getNode(ISD::UNDEF, dl, PVT), Mask);
+                                DAG.getUNDEF(PVT), Mask);
   return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
 }
 
@@ -3123,7 +3119,7 @@
   DebugLoc dl = V2.getNode()->getDebugLoc();
   MVT VT = V2.getValueType();
   SDValue V1 = isZero
-    ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getNode(ISD::UNDEF, dl, VT);
+    ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT);
   unsigned NumElems = V2.getValueType().getVectorNumElements();
   MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
   MVT EVT = MaskVT.getVectorElementType();
@@ -3219,7 +3215,7 @@
       if (NumZero)
         V = getZeroVector(MVT::v8i16, true, DAG, dl);
       else
-        V = DAG.getNode(ISD::UNDEF, dl, MVT::v8i16);
+        V = DAG.getUNDEF(MVT::v8i16);
       First = false;
     }
 
@@ -3266,7 +3262,7 @@
         if (NumZero)
           V = getZeroVector(MVT::v8i16, true, DAG, dl);
         else
-          V = DAG.getNode(ISD::UNDEF, dl, MVT::v8i16);
+          V = DAG.getUNDEF(MVT::v8i16);
         First = false;
       }
       V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 
@@ -3337,7 +3333,7 @@
 
   if (NumNonZero == 0) {
     // All undef vector. Return an UNDEF.  All zero vectors were handled above.
-    return DAG.getNode(ISD::UNDEF, dl, VT);
+    return DAG.getUNDEF(VT);
   }
 
   // Special case for single non-zero, non-undef, element.
@@ -3368,7 +3364,7 @@
         // a vector.  If Idx != 0, swizzle it into place.
         if (Idx != 0) {
           SDValue Ops[] = { 
-            Item, DAG.getNode(ISD::UNDEF, dl, Item.getValueType()),
+            Item, DAG.getUNDEF(Item.getValueType()),
             getSwapEltZeroMask(VecElts, Idx, DAG, dl)
           };
           Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3);
@@ -3422,7 +3418,7 @@
       SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
                                    &MaskVec[0], MaskVec.size());
       return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item,
-                         DAG.getNode(ISD::UNDEF, VT), Mask);
+                         DAG.getUNDEF(VT), Mask);
     }
   }
 
@@ -3752,12 +3748,12 @@
       for (unsigned i = 0; i < 8; ++i) {
         SDValue Elt = V1Elts[i];
         if (Elt.getOpcode() == ISD::UNDEF) {
-          MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEVT));
+          MaskVec.push_back(DAG.getUNDEF(MaskEVT));
           continue;
         }
         unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
         if (EltIdx >= 8)
-          MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEVT));
+          MaskVec.push_back(DAG.getUNDEF(MaskEVT));
         else
           MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
       }
@@ -3840,7 +3836,7 @@
         return SDValue();
     }
     if (StartIdx == ~0U)
-      MaskVec.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEltVT));
+      MaskVec.push_back(DAG.getUNDEF(MaskEltVT));
     else
       MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
   }
@@ -3897,7 +3893,7 @@
   MVT MaskEVT = MaskVT.getVectorElementType();
   SmallVector<std::pair<int, int>, 8> Locs;
   Locs.resize(4);
-  SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, dl, MaskEVT));
+  SmallVector<SDValue, 8> Mask1(4, DAG.getUNDEF(MaskEVT));
   unsigned NumHi = 0;
   unsigned NumLo = 0;
   for (unsigned i = 0; i != 4; ++i) {
@@ -3929,7 +3925,7 @@
                      DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
                                  &Mask1[0], Mask1.size()));
 
-    SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, dl, MaskEVT));
+    SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT));
     for (unsigned i = 0; i != 4; ++i) {
       if (Locs[i].first == -1)
         continue;
@@ -3969,9 +3965,9 @@
     }
 
     Mask1[0] = PermMask.getOperand(HiIndex);
-    Mask1[1] = DAG.getNode(ISD::UNDEF, dl, MaskEVT);
+    Mask1[1] = DAG.getUNDEF(MaskEVT);
     Mask1[2] = PermMask.getOperand(HiIndex^1);
-    Mask1[3] = DAG.getNode(ISD::UNDEF, dl, MaskEVT);
+    Mask1[3] = DAG.getUNDEF(MaskEVT);
     V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
                      DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4));
 
@@ -4004,8 +4000,8 @@
 
   // Break it into (shuffle shuffle_hi, shuffle_lo).
   Locs.clear();
-  SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
-  SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
+  SmallVector<SDValue,8> LoMask(4, DAG.getUNDEF(MaskEVT));
+  SmallVector<SDValue,8> HiMask(4, DAG.getUNDEF(MaskEVT));
   SmallVector<SDValue,8> *MaskPtr = &LoMask;
   unsigned MaskIdx = 0;
   unsigned LoIdx = 0;
@@ -4040,7 +4036,7 @@
   SmallVector<SDValue, 8> MaskOps;
   for (unsigned i = 0; i != 4; ++i) {
     if (Locs[i].first == -1) {
-      MaskOps.push_back(DAG.getNode(ISD::UNDEF, dl, MaskEVT));
+      MaskOps.push_back(DAG.getUNDEF(MaskEVT));
     } else {
       unsigned Idx = Locs[i].first * 4 + Locs[i].second;
       MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
@@ -4066,7 +4062,7 @@
   bool V2IsSplat = false;
 
   if (isUndefShuffle(Op.getNode()))
-    return DAG.getNode(ISD::UNDEF, dl, VT);
+    return DAG.getUNDEF(VT);
 
   if (isZeroShuffle(Op.getNode()))
     return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
@@ -4232,7 +4228,7 @@
   if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
     if (V2.getOpcode() != ISD::UNDEF)
       return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1,
-                         DAG.getNode(ISD::UNDEF, VT), PermMask);
+                         DAG.getUNDEF(VT), PermMask);
     return Op;
   }
 
@@ -4246,10 +4242,10 @@
         RVT = MVT::v4i32;
         Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT,
                          DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1),
-                         DAG.getNode(ISD::UNDEF, dl, RVT), PermMask);
+                         DAG.getUNDEF(RVT), PermMask);
       } else if (V2.getOpcode() != ISD::UNDEF)
         Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1,
-                         DAG.getNode(ISD::UNDEF, dl, RVT), PermMask);
+                         DAG.getUNDEF(RVT), PermMask);
       if (RVT != VT)
         Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op);
       return Op;
@@ -4370,17 +4366,16 @@
     IdxVec.
       push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
     IdxVec.
-      push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType()));
+      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
     IdxVec.
-      push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType()));
+      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
     IdxVec.
-      push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType()));
+      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
     SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
                                  &IdxVec[0], IdxVec.size());
     SDValue Vec = Op.getOperand(0);
     Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
-                      Vec, DAG.getNode(ISD::UNDEF, dl, Vec.getValueType()), 
-                      Mask);
+                      Vec, DAG.getUNDEF(Vec.getValueType()), Mask);
     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
                        DAG.getIntPtrConstant(0));
   } else if (VT.getSizeInBits() == 64) {
@@ -4398,12 +4393,12 @@
     SmallVector<SDValue, 8> IdxVec;
     IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
     IdxVec.
-      push_back(DAG.getNode(ISD::UNDEF, dl, MaskVT.getVectorElementType()));
+      push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
     SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
                                  &IdxVec[0], IdxVec.size());
     SDValue Vec = Op.getOperand(0);
     Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
-                      Vec, DAG.getNode(ISD::UNDEF, dl, Vec.getValueType()), 
+                      Vec, DAG.getUNDEF(Vec.getValueType()), 
                       Mask);
     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
                        DAG.getIntPtrConstant(0));
@@ -4595,7 +4590,7 @@
                                              GA->getValueType(0),
                                              GA->getOffset());
   SDValue Ops[] = { Chain,  TGA, InFlag };
-  SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
+  SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
   InFlag = Result.getValue(2);
   Chain = Result.getValue(1);
 
@@ -4611,7 +4606,7 @@
                       DAG.getRegister(X86::EAX, PtrVT),
                       DAG.getRegister(X86::EBX, PtrVT),
                       InFlag };
-  Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
+  Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 5);
   InFlag = Chain.getValue(1);
 
   return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag);
@@ -4630,7 +4625,7 @@
                                              GA->getValueType(0),
                                              GA->getOffset());
   SDValue Ops[]  = { DAG.getEntryNode(), TGA};
-  SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
+  SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
   Chain  = Result.getValue(1);
   InFlag = Result.getValue(2);
 
@@ -4645,7 +4640,7 @@
                                                   PtrVT),
                       DAG.getRegister(X86::RDI, PtrVT),
                       InFlag };
-  Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
+  Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 4);
   InFlag = Chain.getValue(1);
 
   return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag);





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