[llvm-commits] [llvm] r63829 - /llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll

Bill Wendling isanbard at gmail.com
Wed Feb 4 20:41:18 PST 2009


Author: void
Date: Wed Feb  4 22:41:18 2009
New Revision: 63829

URL: http://llvm.org/viewvc/llvm-project?rev=63829&view=rev
Log:
Add testcase.

Added:
    llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll

Added: llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll?rev=63829&view=auto

==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll (added)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-30.ll Wed Feb  4 22:41:18 2009
@@ -0,0 +1,23 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t -f
+; RUN: grep pshufhw %t | grep 161 | count 1
+; RUN: grep pslldq %t | count 1
+
+
+
+; Test case when creating pshufhw, we incorrectly set the higher order bit
+; for an undef,
+define void @test(<8 x i16>* %dest, <8 x i16> %in) {
+entry:
+  %0 = load <8 x i16>* %dest
+  %1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
+  store <8 x i16> %1, <8 x i16>* %dest
+  ret void
+}                              
+
+; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq
+define void @test2(<4 x i32>* %dest, <4 x i32> %in) {
+entry:
+  %0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
+  store <4 x i32> %0, <4 x i32>* %dest
+  ret void
+}       
\ No newline at end of file





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