[llvm-commits] [llvm] r63169 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp LegalizeVectorTypes.cpp

[Dan Gohman]

Author: djg
Date: Tue Jan 27 20:58:31 2009
New Revision: 63169

URL: http://llvm.org/viewvc/llvm-project?rev=63169&view=rev
Log:
Use ZERO_EXTEND instead of ANY_EXTEND when promoting
shift amounts, to avoid implicitly assuming that
target architectures will ignore the high bits.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=63169&r1=63168&r2=63169&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jan 27 20:58:31 2009
@@ -974,7 +974,7 @@
     return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
 
   if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
-    return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
+    return DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
 
   return ShiftAmt;
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=63169&r1=63168&r2=63169&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jan 27 20:58:31 2009
@@ -114,7 +114,7 @@
   if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
     ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
   else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
-    ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
+    ShiftAmt = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
 
   return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt);
 }