[llvm-commits] [llvm] r62459 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Mon P Wang]

Author: wangmp
Date: Sun Jan 18 00:43:40 2009
New Revision: 62459

URL: http://llvm.org/viewvc/llvm-project?rev=62459&view=rev
Log:
Simplify extract element based on comments from Duncan Sands.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=62459&r1=62458&r2=62459&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jan 18 00:43:40 2009
@@ -4880,14 +4880,9 @@
 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
   // (vextract (scalar_to_vector val, 0) -> val
   SDValue InVec = N->getOperand(0);
-  SDValue EltNo = N->getOperand(1);
 
-  if (isa<ConstantSDNode>(EltNo)) {
-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
-    if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && Elt == 0) {
-      return InVec.getOperand(0);
-    }
-  }
+ if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR)
+   return InVec.getOperand(0);
 
   // Perform only after legalization to ensure build_vector / vector_shuffle
   // optimizations have already been done.
@@ -4896,6 +4891,7 @@
   // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
   // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
   // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
+  SDValue EltNo = N->getOperand(1);
 
   if (isa<ConstantSDNode>(EltNo)) {
     unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();