[llvm-commits] [llvm] r62281 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/vec_insert-8.ll

[Mon P Wang]

Author: wangmp
Date: Thu Jan 15 15:10:20 2009
New Revision: 62281

URL: http://llvm.org/viewvc/llvm-project?rev=62281&view=rev
Log:
Expand insert/extract of a <4 x i32> with a variable index.

Added:
    llvm/trunk/test/CodeGen/X86/vec_insert-8.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=62281&r1=62280&r2=62281&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jan 15 15:10:20 2009
@@ -766,12 +766,12 @@
     // information.
     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i8, Custom);
     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);
-    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Legal);
+    setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);
     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);
 
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
-    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
+    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
 
     if (Subtarget->is64Bit()) {
@@ -4248,6 +4248,10 @@
                     DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
                                     Op.getOperand(1));
     return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
+  } else if (VT == MVT::i32) {
+    // ExtractPS works with constant index.
+    if (isa<ConstantSDNode>(Op.getOperand(1)))
+      return Op;
   }
   return SDValue();
 }
@@ -4362,6 +4366,10 @@
     //   combine either bitwise AND or insert of float 0.0 to set these bits.
     N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
     return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
+  } else if (EVT == MVT::i32) {
+    // InsertPS works with constant index.
+    if (isa<ConstantSDNode>(N2))
+      return Op;
   }
   return SDValue();
 }

Added: llvm/trunk/test/CodeGen/X86/vec_insert-8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_insert-8.ll?rev=62281&view=auto

==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_insert-8.ll (added)
+++ llvm/trunk/test/CodeGen/X86/vec_insert-8.ll Thu Jan 15 15:10:20 2009
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t -f
+
+; tests variable insert and extract of a 4 x i32
+
+define <4 x i32> @var_insert(<4 x i32> %x, i32 %val, i32 %idx) nounwind  {
+entry:
+	%tmp3 = insertelement <4 x i32> %x, i32 %val, i32 %idx		; <<4 x i32>> [#uses=1]
+	ret <4 x i32> %tmp3
+}
+
+define i32 @var_extract(<4 x i32> %x, i32 %idx) nounwind  {
+entry:
+	%tmp3 = extractelement <4 x i32> %x, i32 %idx		; <<i32>> [#uses=1]
+	ret i32 %tmp3
+}