[llvm-commits] [llvm] r62259 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h
Dan Gohman
gohman at apple.com
Thu Jan 15 08:29:46 PST 2009
Author: djg
Date: Thu Jan 15 10:29:45 2009
New Revision: 62259
URL: http://llvm.org/viewvc/llvm-project?rev=62259&view=rev
Log:
Const-qualify getPreIndexedAddressParts and friends.
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=62259&r1=62258&r2=62259&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Jan 15 10:29:45 2009
@@ -676,7 +676,7 @@
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
return false;
}
@@ -686,7 +686,7 @@
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
return false;
}
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=62259&r1=62258&r2=62259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jan 15 10:29:45 2009
@@ -1726,7 +1726,7 @@
ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
if (Subtarget->isThumb())
return false;
@@ -1760,7 +1760,7 @@
SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
if (Subtarget->isThumb())
return false;
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=62259&r1=62258&r2=62259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Jan 15 10:29:45 2009
@@ -100,7 +100,7 @@
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// getPostIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if this node can be
@@ -108,7 +108,7 @@
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=62259&r1=62258&r2=62259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jan 15 10:29:45 2009
@@ -766,7 +766,7 @@
/// can be more efficiently represented with [r+imm].
bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
SDValue &Index,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
short imm = 0;
if (N.getOpcode() == ISD::ADD) {
if (isIntS16Immediate(N.getOperand(1), imm))
@@ -813,7 +813,8 @@
/// a signed 16-bit displacement [r+imm], and if it is not better
/// represented as reg+reg.
bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
- SDValue &Base, SelectionDAG &DAG){
+ SDValue &Base,
+ SelectionDAG &DAG) const {
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
return false;
@@ -898,7 +899,7 @@
/// represented as an indexed [r+r] operation.
bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
SDValue &Index,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
// Check to see if we can easily represent this as an [r+r] address. This
// will fail if it thinks that the address is more profitably represented as
// reg+imm, e.g. where imm = 0.
@@ -925,7 +926,7 @@
/// [r+imm*4]. Suitable for use by STD and friends.
bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
SDValue &Base,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
// If this can be more profitably realized as r+r, fail.
if (SelectAddressRegReg(N, Disp, Base, DAG))
return false;
@@ -1013,7 +1014,7 @@
bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
// Disabled by default for now.
if (!EnablePPCPreinc) return false;
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=62259&r1=62258&r2=62259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Jan 15 10:29:45 2009
@@ -239,30 +239,30 @@
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// SelectAddressRegReg - Given the specified addressed, check to see if it
/// can be represented as an indexed [r+r] operation. Returns false if it
/// can be more efficiently represented with [r+imm].
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// SelectAddressRegImm - Returns true if the address N can be represented
/// by a base register plus a signed 16-bit displacement [r+imm], and if it
/// is not better represented as reg+reg.
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
/// represented as an indexed [r+r] operation.
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// SelectAddressRegImmShift - Returns true if the address N can be
/// represented by a base register plus a signed 14-bit displacement
/// [r+imm*4]. Suitable for use by STD and friends.
bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
- SelectionDAG &DAG);
+ SelectionDAG &DAG) const;
/// LowerOperation - Provide custom lowering hooks for some operations.
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