[llvm-commits] [llvm] r61896 - in /llvm/trunk: lib/Target/CellSPU/SPUInstrInfo.cpp test/CodeGen/CellSPU/shift_ops.ll

[Misha Brukman]

Author: brukman
Date: Wed Jan  7 17:07:29 2009
New Revision: 61896

URL: http://llvm.org/viewvc/llvm-project?rev=61896&view=rev
Log:
Fix off-by-one error in traversing an array; this fixes a test.
The error was reported by gcc-4.3.0 during compilation.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
    llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=61896&r1=61895&r2=61896&view=diff

==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Wed Jan  7 17:07:29 2009
@@ -678,7 +678,7 @@
 
   unsigned Opc = unsigned(Cond[0].getImm());
   // Pretty dull mapping between the two conditions that SPU can generate:
-  for (int i = sizeof(revconds)/sizeof(revconds[0]); i >= 0; --i) {
+  for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
     if (revconds[i].Opc == Opc) {
       Cond[0].setImm(revconds[i].RevCondOpc);
       return false;

Modified: llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll?rev=61896&r1=61895&r2=61896&view=diff

==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll Wed Jan  7 17:07:29 2009
@@ -16,8 +16,6 @@
 ; RUN: grep -w rotqbybi  %t1.s | count 1
 ; RUN: grep -w sfi       %t1.s | count 3
 
-; XFAIL: alpha|linux|sparc|ia64|arm
-
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"