[llvm-commits] [llvm] r61074 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

[Dan Gohman]

Author: djg
Date: Mon Dec 15 21:31:11 2008
New Revision: 61074

URL: http://llvm.org/viewvc/llvm-project?rev=61074&view=rev
Log:
Remove some special-case logic in ScheduleDAGSDNodes's 
latency computation code that is no longer needed with the
new method for handling latencies.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=61074&r1=61073&r2=61074&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon Dec 15 21:31:11 2008
@@ -196,12 +196,6 @@
   
   // Compute the latency for the node.  We use the sum of the latencies for
   // all nodes flagged together into this SUnit.
-  if (InstrItins.isEmpty()) {
-    // No latency information.
-    SU->Latency = 1;
-    return;
-  }
-
   SU->Latency = 0;
   bool SawMachineOpcode = false;
   for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
@@ -210,10 +204,6 @@
       SU->Latency +=
         InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
     }
-
-  // Ensure that CopyToReg and similar nodes have a non-zero latency.
-  if (!SawMachineOpcode)
-    SU->Latency = 1;
 }
 
 /// CountResults - The results of target nodes have register or immediate