[llvm-commits] [llvm] r60753 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp

[Bill Wendling]

Author: void
Date: Tue Dec  9 01:55:31 2008
New Revision: 60753

URL: http://llvm.org/viewvc/llvm-project?rev=60753&view=rev
Log:
Correct my English.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=60753&r1=60752&r2=60753&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Dec  9 01:55:31 2008
@@ -952,10 +952,10 @@
       default: break;
       case Intrinsic::sadd_with_overflow:
       case Intrinsic::uadd_with_overflow:
-        // Cheat a little. We know that the register for the "add" and "seto"
-        // are allocated sequentially. However, we only keep track of the
-        // register for "add" in the value map. Use the extractvalue's index to
-        // get the correct register for "seto".
+        // Cheat a little. We know that the registers for "add" and "seto" are
+        // allocated sequentially. However, we only keep track of the register
+        // for "add" in the value map. Use extractvalue's index to get the
+        // correct register for "seto".
         UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
         return true;
       }
@@ -971,10 +971,11 @@
   default: return false;
   case Intrinsic::sadd_with_overflow:
   case Intrinsic::uadd_with_overflow: {
-    // Replace these intrinsics with an "add" instruction followed by a
-    // "set[co]" instruction. Later on, when the "extractvalue" instructions are
-    // encountered, we use the fact that two registers were created sequentially
-    // to get the correct registers for the "sum" and the "overflow bit".
+    // Replace "add with overflow" intrinsics with an "add" instruction followed
+    // by a seto/setc instruction. Later on, when the "extractvalue"
+    // instructions are encountered, we use the fact that two registers were
+    // created sequentially to get the correct registers for the "sum" and the
+    // "overflow bit".
     MVT VT;
     const Function *Callee = I.getCalledFunction();
     const Type *RetTy =